JP2008199480A - Phase synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily design constants of elements constituting a filter of a PLL circuit. <P>SOLUTION: Phases of an input signal IN and a reference signal REF are compared by a phase comparator 10 and pulse-like current ID according to phase difference is output. The current ID is smoothed by a capacitor 21 of a voltage current converter 20 and provided to an operational amplifier 22 as control voltage VC. Voltage of a node N2 generated in circuit networks 24-26 by the control current IC is compared with the control voltage VC by the operational amplifier 22 and an NMOS 23 is controlled so that current according to the control voltage VC flows. The current flowing to a PMOS 23 flows to a serially connected PMOS 27 and control current IC with the same magnitude is supplied from a PMOS 28 constituting a current mirror to the PMOS 27 to a current control oscillator 30. Since the capacitor 21 for smoothing is independent of the circuit networks 24-26, the constants of the elements constituting the circuit networks 24-26 are easily designed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase locked loop (hereinafter referred to as “PLL (Phase Locked Loop) circuit”), and more particularly to a configuration of a loop filter thereof.

FIG. 2 is a configuration diagram of a conventional PLL circuit.
This PLL circuit includes a phase comparator 1 that outputs a current ID corresponding to a phase difference between an input signal IN and a reference signal REF, a loop filter 2 that smoothes the current ID and generates a control voltage VC having no high-frequency component, and a control voltage A voltage controlled oscillator (hereinafter referred to as “VCO (Voltage Controlled Oscillator)”) 3 that oscillates an output signal OUT having a frequency corresponding to VC, and the frequency of the output signal OUT is 1 / N (where N is an integer of 2 or more) ) To generate a reference signal REF.

  In this PLL circuit, the phase comparator 1 compares the phases of the input signal IN and the reference signal REF, and outputs a current ID proportional to the phase difference. Since the output current ID is pulsed and includes a high-frequency component, the low-pass loop filter 2 removes the high-frequency component and smoothes it, thereby generating a control voltage VC. The control voltage VC is supplied to the VCO 3, and an output signal OUT having a frequency corresponding to the control voltage VC is generated from the VCO 3.

  Most of the output signal OUT is supplied to a circuit (not shown). A part of the output signal OUT is supplied to the frequency divider 4 and divided by 1 / N, and is fed back to the phase comparator 3 as a reference signal REF. The Thus, the frequency of the output signal OUT is obtained by multiplying the frequency of the input signal IN by the reciprocal of the frequency dividing number (1 / N) of the frequency divider 4, that is, N times the frequency of the input signal IN. When generating the output signal OUT having the same frequency as the input signal IN, the frequency divider 4 is omitted, and the output signal OUT becomes the reference signal REF as it is.

  It is the loop filter 2 that determines the stability (time response characteristic) of the PLL circuit. As shown in FIG. 2, the loop filter 2 is a low-pass filter that combines capacitors C 1 and C 2 and a resistor R, and pulses that flow into and out of the phase comparator 1. The current ID is converted into a control voltage VC that is temporally continuous.

The impedance Z (s) of the loop filter 2 is given by the following equation.
Z (s) = {1 + s · C1 · R + s · C2 · R}
/ {S (C1 + C2 + C1 · C2 · R)}
= {1 + s · τ1} / {s (C1 + C2) (1 + s · τ2)}
Here, τ1 = (C1 + C2) · R and τ2 = C1 · C2 · R / (C1 + C2). Normally, C1 is set to a very large value as compared with C2, and thus approximated to τ1 = C1 · R and τ2 = C2 · R.

  FIG. 3 is a frequency characteristic diagram of the loop filter in FIG. 2, the horizontal axis represents the logarithmic frequency f, and the vertical axis represents the absolute value of the output signal / input signal (ie, control voltage VC / current ID = impedance). Z | (logarithm display) and phase angle θ are shown.

As shown in FIG. 3, the impedance | Z | of the loop filter 2 decreases as the frequency f increases, but there is a region that exhibits a substantially constant value within a certain frequency range. The lower limit frequency f1 and the upper limit frequency f2 at which the impedance | Z | becomes substantially constant are obtained from the time constants τ1 and τ2 of the loop filter 2 as follows.
f1 = 1 / (2π · τ1)
f2 = 1 / (2π · τ2)

  On the other hand, as shown in FIG. 3, the phase angle θ is −45 ° at frequencies f1 and f2, respectively, and is a value on the + side of −45 ° between the frequencies f1 and f2.

Since the open loop characteristic F (s) of the PLL circuit is given by the product of gains in each block, Kd · Z (s) · Kv · (1 / s) · (1 / N), F (s) is It becomes like the following formula.
F (s) = Kd · Z (s) · Kv · (1 / s) · (1 / N)
= {1 + s · τ1} / {s (C1 + C2) (1 + s · τ2)}
× (Kd · Kv) / (N / s)

In designing the loop filter 2, the open loop gain of the PLL system becomes 1 at an intermediate frequency f0 (= √ (f1 · f2)) between the frequencies f1 and f2, and the phase return amount Δθ at that time is set to 40-50. It is effective and important to stabilize the PLL system. If the left side of the above equation is set to 1, the intermediate frequency f0 is obtained, but the following equation is used approximately.
f0 = (1 / 2π) √ {(Kd · Kv) / (N · C1)}

JP-A-5-75451 JP-A-11-122100

  However, in the PLL circuit, since the values of the capacitors C1 and C2 and the resistor R of the loop filter 2 are related to each other, optimal design is difficult. In some cases, these values are set after actually making a prototype. There was a problem that had to be done.

  An object of the present invention is to provide a PLL circuit capable of easily designing the values of elements constituting a filter.

  The phase synchronization circuit of the present invention includes a phase comparator that compares a phase difference between an input signal and a reference signal, a voltage-current converter that outputs a control current based on a comparison result of the phase comparator, and a control circuit that corresponds to the control current. A current-controlled oscillator that outputs an output signal having a frequency and supplies the output signal to the phase comparator as the reference signal, and the voltage-current converter receives a comparison result of the phase comparator; A first filter circuit connected to a common potential supply unit; and a second filter circuit for controlling the control current, wherein the second filter circuit includes at least a first resistor and a first filter circuit. The capacitor is connected in parallel.

  The present invention includes a voltage-current converter that generates a control voltage that is continuous in time by smoothing the current supplied from the phase comparator and outputs a control current corresponding to the control voltage. The voltage-current converter is provided with a second filter circuit for controlling the control current, and the second filter circuit is configured so that the control current has frequency characteristics. As a result, it is possible to separate the first filter circuit for smoothing the pulsed current supplied from the phase comparator and the second filter circuit for outputting the control current according to the change of the control voltage. Thus, there is an effect that the values of elements constituting the filter having a desired frequency characteristic can be easily designed.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a PLL circuit showing an embodiment of the present invention.
The PLL circuit includes a phase comparator 10, a voltage / current converter 20, a current control oscillator 30, and a frequency divider 40.

  The phase comparator 10 compares the phases of the input signal IN and the reference signal REF and outputs a current ID corresponding to the phase difference. For example, flip-flops (hereinafter referred to as “FF”) 11 and 12, AND gates (Hereinafter referred to as “AND”) 13 and a phase comparison unit composed of a delay element (DLY) 14, and a current output unit composed of switches 15 and 16 and constant current sources 17 and 18.

  The FF 11 outputs a signal “H” at a high voltage level (power supply voltage VDD level in this embodiment) from when the input signal IN rises to when the reset signal RST is given. During the period from when the reference signal REF rises to when the reset signal RST is given, the “H” signal DN is output. The reset signal RST is generated by delaying the output signal of the AND 13 that detects that the signal UP and the signal DN are both “H” by the delay element 14 for a predetermined time.

  The switch 15 outputs the current of the constant current source 17 from the node N1 to the voltage-current converter 20 while the signal UP is “H”. The switch 16 allows a current to flow from the voltage-current converter 20 to the constant current source 18 via the node N1 while the signal DN is “H”. As a result, the current ID corresponding to the phase difference between the input signal IN and the reference signal REF flows in a pulsed manner between the phase comparator 10 and the voltage-current converter 20 via the node N1.

  The voltage-to-current converter 20 generates a control voltage VC that is temporally continuous by smoothing the current ID that is input and output in a pulse shape, removes high-frequency components contained in the control voltage VC, and generates the control voltage VC. A corresponding control current IC is output.

  This voltage-current converter 20 is connected between the node N1 and a ground part set to the ground potential GND as a common potential supply part, and has a capacitor 21 that smoothes the pulsed current ID and generates the control voltage VC. The control voltage VC generated by the capacitor 21 is applied to one input side of an operational amplifier (Operational Amplifier, also referred to as an operational amplifier, abbreviated as “OP” in the drawing) 22. . The other input side of the operational amplifier 22 is connected to the node N 2, and the output side is connected to the gate of an N-channel MOS transistor (hereinafter referred to as “NMOS”) 23.

  The source and drain of the NMOS 23 are connected to nodes N2 and N3, respectively. One end of a resistor 24 is further connected to the node N2, and the other end of the resistor 24 is connected to a ground potential portion set to the ground potential GND. In addition, a capacitor 25 and a resistor 26 connected in series are connected to the resistor 24 in parallel. A drain and a gate of a P-channel MOS transistor (hereinafter referred to as “PMOS”) 27 are connected to the node N3, and a source of the PMOS 27 is connected to a power supply potential portion set to the power supply potential VDD. Further, the voltage-current converter 20 has a PMOS 28 that forms a current mirror with respect to the PMOS 27, and a control current IC for the current-controlled oscillator 30 is output from the drain of the PMOS 28.

  The current control oscillator 30 oscillates an output signal OUT whose frequency changes in accordance with the control current IC. The three inverters 31, 32, 33 are connected in a ring shape, and the inverters 31 to 33 are connected to the control current IC. It is configured to be driven by an IC. As a result, when the drive control current IC is increased, the operation speed of each of the inverters 31 to 33 is increased and the oscillation frequency is increased. When the control current IC is decreased, the operation speed is decreased and the oscillation frequency is decreased. It is like that.

  The output signal OUT oscillated by the current control oscillator 30 is supplied to other circuits, and is divided by a frequency divider 40 to 1 / N (where N is an integer of 2 or more), and is used as a reference signal REF as a phase comparator. 10 is given.

  Since the entire oscillation operation in the PLL circuit is the same as that of the PLL circuit of FIG. 2, for example, the operation of the voltage-current converter 20 will be mainly described here.

  The voltage-to-current converter 20 flows the current flowing through the NMOS 23 into the current detection resistor 24, compares the voltage drop with the input signal (control voltage VC), and outputs a control current IC corresponding to the input signal. This is a circuit configured as described above. Since the capacitor 25 and the resistor 26 are connected in parallel to the resistor 24, the control current IC has frequency characteristics.

The frequency characteristics of the voltage-current converter 20 are given by the following equation, where the resistance values of the resistors 24 and 26 are R24 and R26, respectively, and the capacitance value of the capacitor 25 is C25.
IC (s) = VC / Z (s)
= {(1 + s · τ1) / (1 + s · τ2)} × (VC / R24)
Here, τ1 = C25 · R24 and τ2 = C25 · R24 · R26 / (R24 + R26). When R24 is sufficiently larger than R26, it can be approximated as τ2 = C25 · R26.

  FIG. 4 is a frequency characteristic diagram of the voltage-current converter, in which the horizontal axis represents the logarithmic frequency f, and the vertical axis represents the control current IC and the phase angle θ.

  As shown in FIG. 4, when the frequency f is sufficiently low and the impedance of the capacitor 25 is negligibly large compared to the impedance of the resistor 24, the magnitude of the control current IC is VC / R24, and its value is It becomes constant.

  When the frequency f becomes high to some extent and becomes the frequency f1 corresponding to τ1, the impedances of the capacitor 25 and the resistor 24 become the same level, and the equivalent impedance Z of the resistance of the current detection amount starts to become smaller than R24. Since the absolute value | IC | of the control current is VC / | Z |, the control current IC increases as the frequency f increases. When the frequency f further increases and becomes the frequency f2 corresponding to τ2, the impedance of the capacitor 25 becomes smaller than the impedance of the resistor 26, and the impedance Z is equivalent to the resistors 24 and 26 connected in parallel. As a result, the control current IC again becomes a constant value that does not depend on the frequency f.

  During this time, the phase angle θ starts to advance from 0 ° to the plus side as the frequency f increases. However, when the frequency f further increases, the phase angle θ returns to 0 ° again. The phase θ is 45 ° at the frequencies f1 and f2.

The frequency characteristic Kv (s) of the loop filter including the voltage-current converter 20 is not changed in the input / output characteristics of the oscillating unit. Therefore, the frequency characteristic of the control current IC is added. Indicated.
Kv (s) = Kv.IC (s) / IC (0)
= {(1 + s · τ1) / (1 + s · τ2)} · Kv
However, IV (0) = VC / R24.

  In this embodiment, the frequency characteristic of the conventional loop filter is a combination of the impedance frequency characteristic of the capacitor 21 and the frequency characteristic of the voltage-current converter 20.

The open loop characteristic F (s) in this PLL circuit is given by the following equation.
F (s) = Kd · f (s) · Kv (s) / (N · s)
= {1 / (s · C1)} {(1 + s · τ1) / (1 + s · τ2)}
× {(Kd · Kv) / (N · s)}

  FIG. 5 is a frequency characteristic diagram of a loop filter including a voltage-current converter, and FIG. 6 is a frequency characteristic diagram of an open loop gain of the PLL circuit. In FIG. 5, the vertical axis indicates the loop filter impedance | Z | and the phase angle θ, and in FIG. 6, the vertical axis indicates the open loop gain OG and the return angle Δθ.

As shown in FIG. 5, it can be seen that the loop filter of the PLL circuit of the present embodiment exhibits almost the same characteristics as the conventional loop filter. At this time, since τ1 and τ2 are respectively shown in the above equations, the approximate expression of the intermediate frequency f0 (= √ (f1 · f2)) for stably operating the PLL system is as follows: It becomes an expression.
f0 = (1 / 2π) √ {(Kd · Kv) / (N · C21)}
However, C21 is a capacitance value of the capacitor 21.

  As described above, the PLL circuit according to this embodiment includes the voltage / current converter 20 including the resistors 24 and 26 and the capacitor 25 for obtaining a desired frequency characteristic. Thereby, the smoothing capacitor 21, the resistors 24 and 26 for obtaining a desired frequency characteristic, and the capacitor 25 are separated, and the resistance value and the capacitance value can be set independently. Therefore, there is an advantage that the values of elements constituting the filter can be easily designed.

  In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.

(A) Although the voltage-current converter 20 is configured to apply the control voltage VC to the gate of the NMOS 23 via the operational amplifier 22, for example, a modification of the voltage-current converter of FIG. 1 shown in FIG. Thus, the operational amplifier 22 may be eliminated and the control voltage VC may be applied directly to the gate of the NMOS 23.

(B) The circuit network including the resistor and the capacitor connected between the node N2 and the ground potential portion set to the ground potential GND is not limited to the illustrated connection. For example, as shown in FIG. 7, a resistor 26 may be connected in series to a resistor 24 and a capacitor 25 connected in parallel, and this may be connected between the node N2 and the ground potential GND. Alternatively, the resistor 26 may be omitted by using the internal resistance of the output transistor (PMOS 23 or the like) to obtain the same frequency characteristic. In other words, any circuit network may be used as long as the frequency f increases and the impedance decreases and the control current IC increases.

(C) Although only the capacitor 21 is used as a loop filter, it is not limited to this. That is, instead of the capacitor 21, a conventional network of capacitors and resistors may be used. In that case, since independent time constants can be set for both the loop filter and the voltage-current converter, it becomes possible to set higher-order frequency characteristics, high operational stability, and low jitter. A performance PLL circuit can be constructed.

(D) The circuit configuration of the phase comparator 10 and the current control oscillator 30 is an example, and can be replaced with a circuit having a similar function.

(E) When the output signal OUT having the same frequency as the input signal IN is oscillated, the frequency divider 40 is not necessary.

(F) As long as the same effect as the present invention is obtained, the voltage-current converter 20 may be configured such that the NMOS 23 is replaced with PMOS and the PMOSs 27 and 28 are replaced with NMOS. It may be configured by.

(G) Capacitors and resistors in the figure are composed of transistors with capacitors connected or transistors that are always on as long as a sufficient capacitance value or resistance value capable of realizing a necessary function in the circuit configuration can be prepared. A resistor may be used.
(H) The switches 15 and 16 may be composed of transistors.

It is a block diagram of a PLL circuit showing an embodiment of the present invention. It is a block diagram of a conventional PLL circuit. FIG. 3 is a frequency characteristic diagram of the loop filter in FIG. 2. It is a frequency characteristic figure of a voltage current converter. It is a frequency characteristic figure of the loop filter containing a voltage-current converter. It is a frequency characteristic figure of the open loop gain of a PLL circuit. It is a modification of the voltage-current converter of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Phase comparator 20 Voltage-current converter 21, 25 Capacitor 22 Operational amplifier 23 NMOS
27, 28 PMOS
24, 26 Resistor 30 Current control oscillator 40 Divider

Claims (8)

A phase comparator that compares the phase difference between the input signal and the reference signal, a voltage-current converter that outputs a control current based on the comparison result of the phase comparator, and an output signal having a frequency corresponding to the control current. A current controlled oscillator for providing the output signal to the phase comparator as the reference signal,
The voltage-current converter is
A first filter circuit connected between a first node receiving a comparison result of the phase comparator and a common potential supply unit;
A second filter circuit for controlling the control current,
The second filter circuit has a configuration in which at least a first resistor and a first capacitor are connected in parallel;
A phase synchronization circuit characterized by the above.   The phase synchronization circuit according to claim 1, further comprising a frequency divider that divides the output signal to generate the reference signal.   The voltage-current converter causes a current corresponding to the control current to flow through the current detector, and compares the voltage drop of the current detector with the control voltage generated from the comparison result by the first filter circuit. 3. The phase synchronization circuit according to claim 1, wherein the phase synchronization circuit is configured to output a control current corresponding to the control voltage. The voltage-current converter is
An operational amplifier that outputs a signal corresponding to the difference between the control voltage and the voltage of the second node;
A first transistor having a gate provided with an output signal of the operational amplifier, a first electrode connected to the second node, and a second electrode connected to a third node;
A second transistor connected between the third node and a power supply potential;
A third transistor configured to form a current mirror with respect to the second transistor, and to output the control current according to a current flowing through the second transistor;
3. The phase locked loop circuit according to claim 1, wherein the second filter circuit is connected between the second node and the common potential supply unit. The voltage-current converter is
A first transistor having a gate provided with the control voltage, a first electrode connected to the second node, and a second electrode connected to a third node;
A second transistor connected between the third node and a power supply potential;
A third transistor configured to form a current mirror with respect to the second transistor, and to output the control current according to a current flowing through the second transistor;
3. The phase locked loop circuit according to claim 1, wherein the second filter circuit is connected between the second node and the common potential supply unit. The second filter circuit is
The first resistor connected between the second node and the common potential supply unit;
The second capacitor and the second resistor connected in series between the second node and the common potential supply unit;
6. The phase synchronization circuit according to claim 4, wherein the phase synchronization circuit is configured. The second filter circuit is
The capacitor and the first resistor connected in parallel between the second node and a fourth node;
A second resistor connected between the fourth node and the common potential supply unit;
6. The phase synchronization circuit according to claim 4, wherein the phase synchronization circuit is configured.   The phase according to any one of claims 1 to 7, wherein the first filter circuit includes a second capacitor connected between the first node and the common potential supply unit. Synchronous circuit.

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