JP2007295180A - Charge pump circuit, and pll circuit and dll circuit using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit which constitutes a PLL circuit etc. is capable of making its output current stable, and effectively restraining jitters from occurring in its oscillation output signals; and to provide the PLL circuit etc. using the same. <P>SOLUTION: The charge pump circuit is equipped with a first and a second constant current source, furthermore a first switch which is turned ON to output a current from the first constant current source to the output side of the charge pump circuit when up-signals are at a high level, a second switch which is turned ON to enable a current from the first constant current source to flow through a node having a middle potential between a first and a second power source when up-signals are at a low level, a third switch which is turned ON to make a current flow from the output side of the circuit to the second constant current source when down-signals are at a high level, and a fourth switch which is turned ON to make a current flow from the node having a middle potential between the first and second power sources to the second constant current source when down-signals are at a low level. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a charge pump capable of suppressing the occurrence of jitter in an oscillation signal (hereinafter also referred to as “oscillation output signal”) output from a PLL circuit (Phase Locked Loop) or a DLL circuit (Delay Locked Loop). The present invention relates to a circuit and a PLL circuit and a DLL circuit using the charge pump circuit.

In general, the PLL circuit 20 includes a phase comparison circuit (PFD) 21, a charge pump circuit (CP) 22, a loop filter (LPF) 23, and a voltage controlled oscillation circuit (VCO) 24, as shown in FIG. Is done. The PLL circuit 20 shown in FIG. 1 is supplied with the reference signal _{f in} from the outside, the phase and frequency difference between the oscillating output signal _{f out} from the reference signal _{f in} a voltage controlled oscillator 24 by the phase comparator circuit 21 To be compared. From the phase comparison circuit 21, an up signal Up for increasing the frequency of the oscillation output signal and a down signal Down for decreasing the frequency of the oscillation output signal are output to the charge pump circuit 22 in accordance with the phase / frequency difference. The charge pump circuit 22 charges the loop filter 23 or discharges the charge from the loop filter 23 in accordance with the up signal and the down signal from the phase comparison circuit 21. A control signal VCP determined by the electric charge accumulated in the capacitance of the loop filter 23 is input to the voltage controlled oscillation circuit 24. The voltage controlled oscillation circuit 24 outputs an oscillation output signal f _out having a frequency corresponding to the voltage.

Thus the phase and frequency difference between the oscillating output signal f _out from the reference signal f _in a voltage controlled oscillator circuit 24 is detected, the oscillation output signal f _out from the voltage controlled oscillation circuit 24 in accordance with this The oscillation frequency is adjusted repeatedly. Thus, the phase and frequency between the reference signal f _in the oscillation output signal f _out is consistent, that is synchronized (locked), the oscillation output signal having a constant frequency from the voltage controlled oscillation circuit 24 is output.

Here, FIG. 6 shows a general circuit configuration of the charge pump circuit (CP) 22 constituting the PLL circuit. The charge pump circuit shown in FIG. 6 shows the case of the constant current method. Here, the switch 31a by the transistor between the output I _out side and the constant current source circuit 32 connected to the power supply voltage Vdd of the charge pump circuit, and a constant which is connected to the output I _out side and the GND of the charge pump circuit A switch 33a made of a transistor is provided between the current source circuit 34 and the switch 31a and 33a are opened and closed by an up signal Up and a down signal Down to control the current value of the output I _out of the charge pump circuit.

However, in the configuration of the charge pump circuit shown in FIG. 6, when the switch 31a or the switch 33a is opened by the up signal Up or the down signal Down, no current flows through the transistors constituting the constant current source circuits 32 and 34. An operation of supplying a stable current from the state through the linear region of the transistor in the saturation region is performed. Further, when the switch 31a or the switch 33a is opened, the charge charged in the parasitic capacitance of the transistor of the switch 31a or the switch 33a is released. Due to these factors, current overshoot occurs when the switch 31a or the switch 33a is opened, and this is transmitted to the input of the voltage controlled oscillation circuit (VCO) 24 as fluctuation of the current value of the output I _out of the charge pump circuit 22. As a result, jitter may occur in the oscillation output signal of the PLL circuit.

To solve such a problem, there is a method of reducing the overshoot of the current generated when the switch 31a or the switch 33a is opened by using a circuit configuration as shown in FIG. 7 (see, for example, FIG. 9 of Patent Document 1). ). In the configuration shown in FIG. 7, switches 31b and 33b each including two transistors are added to the configuration shown in FIG. While the switch 31a is closed, the switch 31b is configured to open, so that a current flows from the constant current source circuit 32 connected to the power supply voltage Vdd to GND. When the switch 31a is opened in this state, the switch 31b is closed and the current from the constant current source circuit 32 is output to the output I _out side of the charge pump circuit. By adopting such a configuration, since a current always flows through the transistors constituting the constant current source circuit 32, a current overshoot when the switch 31a is opened is reduced.

Similarly, the switch 33b is configured to open while the switch 33a is closed, and the current flows from the power supply voltage Vdd to the GND through the constant current source circuit 34. When the switch 33a is opened in this state, the switch 33b is closed and a current from the output I _out side of the charge pump circuit flows to the GND through the constant current source circuit 34. By adopting such a configuration, since a current always flows through the transistors constituting the constant current source circuit 34, current overshoot when the switch 33a is opened is reduced.
Japanese Patent Laying-Open No. 2005-252438 (FIG. 9)

  However, in the charge pump circuit shown in FIG. 7, the potential difference between the source and drain of the transistor constituting the switch 31a and the potential difference between the source and drain of the transistor constituting the switch 31b are about twice as large. Occurs. The same can be said for the potential difference between the source and drain of the transistor constituting the switch 33a and the potential difference between the source and drain of the transistor constituting the switch 33b.

In this case, when the switch 31b is closed and the switch 31a is opened and the current from the constant current source circuit 32 is output to the output I _out side of the charge pump circuit, the potential fluctuation occurs. A certain amount of current overshoot will occur. This is the same when the switch 33b is opened and the switch 33b is closed and the switch 33a is opened so that the current from the output I _out side of the charge pump circuit flows to the GND through the constant current source circuit 34. .

  For this reason, there is a problem that the generation of jitter in the oscillation output signal of the PLL circuit cannot be effectively suppressed.

  Such a problem also occurs in the DLL circuit 200 as shown in FIG. That is, the DLL circuit includes a phase comparison circuit (PFD) 21, a charge pump circuit (CP) 22, a loop filter (LPF) 23, and a voltage control delay circuit (VCDL) 201, and a charge pump circuit that is a component circuit thereof. However, as described above, there is a problem that the generation of jitter cannot be effectively suppressed.

  Therefore, the present invention can effectively suppress the occurrence of jitter in the oscillation output signal of the PLL circuit or DLL circuit by stabilizing the output current from the charge pump circuit constituting the PLL circuit or DLL circuit. An object of the present invention is to provide a charge pump circuit, a PLL circuit using the charge pump circuit, and a DLL circuit.

In order to achieve the above object, a PLL circuit and a DLL circuit according to the present invention have the following characteristics.
[1] The charge pump circuit is connected to a first constant current source connected to a first power source having a high potential and a second power source having a potential lower than a potential connected to the first constant current source. A second constant current source connected,
Further, when the charge pump circuit receives an up signal for increasing the frequency of the oscillation output signal from the phase comparison circuit, the charge pump circuit is turned on when the received up signal is at a high level, and the first constant current source The first switch for outputting the current from the first charge pump circuit to the output side of the charge pump circuit and ON when the received up signal is at the low level, and the current from the first constant current source is A second switch for flowing to a node indicating a potential intermediate between the power source and the second power source;
When a down signal for lowering the frequency of the oscillation output signal is received from the phase comparison circuit, the second constant current source is turned on from the output side of the charge pump circuit when the received down signal is at a high level. And a second switch that turns on when the received down signal is at a low level, and from the node that shows an intermediate potential between the first power source and the second power source. And a fourth switch for passing a current to the source.
[2] In the above [1], a node indicating an intermediate potential between the first power supply and the second power supply is an intermediate potential node obtained by resistance-dividing between the first power supply and the second power supply. It is characterized by being.
[3] Further, in the above [1] or [2], a PLL circuit that includes a phase comparison circuit, a charge pump circuit, a loop filter, and a voltage control oscillation circuit, and generates an oscillation output signal synchronized with a reference signal In
The charge pump circuit according to claim 1 or 2 is used as the charge pump circuit.
[4] Furthermore, in a DLL circuit including a phase comparison circuit, a charge pump circuit, a loop filter, and a voltage control delay circuit,
The charge pump circuit described in [1] or [2] is used as the charge pump circuit.

  According to the present invention, an output current from a charge pump circuit constituting a PLL circuit or DLL circuit is stabilized, and a charge pump circuit in which occurrence of jitter in an oscillation output signal of the PLL circuit or DLL circuit is effectively suppressed, and A PLL circuit and a DLL circuit using the same are provided.

  Hereinafter, an example of the best mode for carrying out the present invention will be described.

  FIG. 1 shows an example of a PLL circuit configuration to which a charge pump circuit according to the present invention is applied. As shown in FIG. 1, the PLL circuit 20 can be configured by a phase comparison circuit (PFD) 21, a charge pump circuit (CP) 22, a loop filter (LPF) 23, and a voltage controlled oscillation circuit (VCO) 24. .

  An example of the circuit configuration of the charge pump circuit 22 according to the present invention applied to such a PLL circuit is shown in FIG. The charge pump circuit 22 includes a first constant current source 2 connected to Vdd which is a first power source having a high potential, and a first constant current source 2 having a potential lower than the potential connected to the first constant current source 2. And a second constant current source 4 connected to GND which is a second power source. Here, the first constant current source 2 and the second constant current source 4 can be configured by a current mirror circuit. The first power supply is not limited to Vdd, and the second power supply is not limited to GND. It is sufficient that the voltage of the first power supply is higher than the voltage of the second power supply.

Further, when the charge pump circuit 22 receives an up signal for increasing the frequency of the oscillation output signal from the phase comparison circuit 21 located on the preceding stage side, the charge pump circuit 22 is turned on when the received up signal is at a high level. The first switch 1a for outputting the current from the first constant current source 2 to the I _out side which is the output of the charge pump circuit 22, and when the received up signal is at the low level, the first switch 1a is turned on. second switch 1b to flow of the current from the constant current source 2, the GND through the first load transistor 8 from node n ₁ showing power and is Vdd and the intermediate potential between GND and a second power supply And have. Here, the switches 1a and 1b can be constituted by transistors. In FIG. 2, the switches 1a and 1b are constituted by P-type transistors, and a signal having a reverse polarity is input to the switch 1b by inverting the signal of the switch 1a via the inverter 5. However, the configuration of the switches 1a and 1b is not limited to the above configuration, and the switch 1b may be configured by an N-type transistor and the inverter 5 may not be provided. In short, when the charge pump circuit 22 receives an up signal from the phase comparison circuit 21, the switch 1a is turned on (at this time, the switch 1b is turned off) when the received up signal is at a high level. Any configuration may be used as long as the switch 1b is ON (the switch 1a is OFF at this time) when the received up signal is at the Low level.

The potential of the node n ₁ flowing the first current from the constant current source 2 when the switch 1b is turned ON, between GND is the first of Vdd and the second power supply is a power supply The potential is not limited to Vdd / 2 as long as the potential indicates a value. However, the switch 1b is switched from the ON state to the ON state (the switch 1b is OFF at this time), and the current from the first constant current source 2 is output from the charge pump circuit 22 as the I _out side. to reduce the overshoot of the output current at the time of output to the output side of the potential and the potential of the node n ₁ of the charge pump circuit 22 is preferably the same potential. However, the potential on the output side of the charge pump circuit 22 varies depending on the charge stored in the capacitor of the loop filter 23 on the rear stage side. Here, in the PLL circuit, the phase and frequency between the reference signal f _in the oscillation output signal f _out is consistent, that is synchronized (locked), the oscillation output signal having a constant frequency from the voltage controlled oscillation circuit 24 is output In this case, the potential on the output side of the charge pump circuit 22 is stabilized at a predetermined potential. Here, the predetermined potential is often designed to be Vdd / 2. Therefore, as the potential of the node _{n 1,} it is preferable to Vdd / 2. Note that the node n ₁ can be configured by positioning the first power supply Vdd and the second power supply GND in the middle of resistance division by the load transistors 7 and 8. The potential of the node n ₁ can be arbitrarily set between Vdd and GND by adjusting the resistance values of the load transistors 7 and 8.

Further, when the charge pump circuit 22 receives a down signal for lowering the frequency of the oscillation output signal from the phase comparison circuit 21 located on the preceding stage side, the charge pump circuit 22 is turned on when the received down signal is at a high level. The third switch 3a that allows current to flow from the I _out side, which is the output of the charge pump circuit, to the second constant current source 4, and is turned on when the received down signal is at a low level, and the first power source A fourth current flows from a node n ₁ indicating an intermediate potential between Vdd as the first power supply and GND as the second power supply to the second constant current source 4 from a certain Vdd through the load transistor 7. Switch 3b. Here, the switches 3a and 3b can be constituted by transistors. In FIG. 2, the switches 3a and 3b are constituted by N-type transistors, and a signal having a reverse polarity is input to the switch 3b by inverting the signal of the switch 3a via the inverter 6. However, the configuration of the switches 3a and 3b is not limited to the above configuration, and the switch 3b may be configured by a P-type transistor and the inverter 6 may be omitted. In short, when the charge pump circuit 22 receives a down signal from the phase comparison circuit 21, the switch 3a is turned on (at this time, the switch 3b is turned off) when the received down signal is at a high level. Any configuration may be used as long as the switch 3b is turned on (the switch 3a is turned off at this time) when the received down signal is at the low level.

Incidentally, the potential of the node n ₁ to flow a second current to a constant current source 4 when the switch 3b is turned ON, as described above, it is preferable that the same potential as the electric potential on the output side of the charge pump circuit 22 Specifically, Vdd / 2 is preferable. Thereby, the switch 3b is switched from the ON state to the ON state (the switch 3b is OFF at this time), and the current from the I _out side, which is the output of the charge pump circuit 22, is supplied to the second constant current source 4. It is possible to reduce the undershoot of the current when flowing.

  In the present invention, with the above-described configuration, a substantially constant current flows through the first constant current source 2 and the second constant current source 4 regardless of whether the switch 1a and the switch 3a are ON or OFF. It has become. Therefore, overshoot and undershoot of the current on the output side when the switch 1a and the switch 3a are switched can be greatly reduced, and the output can be stabilized. As a result, the occurrence of jitter in the oscillation output signal of the PLL circuit is effectively suppressed as a result.

  FIG. 3 shows another example of the circuit configuration of the charge pump circuit 22 according to the present invention. In FIG. 3, the same parts as those in FIG.

3 is different from FIG. 2 in that the node n ₁ shown in FIG. 2 is intermediately divided by load transistors 7 and 8 between Vdd as the first power supply and GND as the second power supply. It is not positioned but positioned in the middle of the resistors 9 and 10 divided by resistance. Here, the potential of the node n ₁ can be arbitrarily set between Vdd and GND by adjusting the resistance values of the resistors 9 and 10.

  The use of the charge pump circuit 22 shown in FIG. 3 provides the same effect as when the charge pump circuit 22 shown in FIG. 2 is used, and the overshoot of the current on the output side when the switch 1a and the switch 3a are switched and Undershoot can be greatly reduced, and the output can be stabilized. As a result, the occurrence of jitter in the oscillation output signal of the PLL circuit is effectively suppressed as a result.

  The case where the charge pump circuit 22 according to the present invention is applied to a PLL circuit has been described above. However, the charge pump circuit 22 according to the present invention can be applied to a DLL circuit in the same manner, and has the same effect.

FIG. 4 shows an example of a DLL circuit configuration to which the charge pump circuit according to the present invention is applied.
The DLL circuit 200 includes a phase comparison circuit 21, a charge pump circuit 22, a loop filter 23, and a voltage control delay circuit 201. The voltage control oscillation circuit 24 in the DLL circuit has the same function as that of the voltage control delay circuit 201 in the PLL circuit except that the voltage control oscillation circuit 24 is changed to the voltage control delay circuit 201. Have

  Therefore, even when the charge pump circuit according to the present invention is applied to a DLL circuit, the occurrence of jitter is effectively suppressed as in the case of application to a PLL circuit.

  As the first example of the present invention, when the charge pump having the circuit configuration shown in FIG. 2 is used in the PLL circuit configuration shown in FIG. 1, the output of the PLL circuit is locked and the loop is stabilized. FIG. 5 shows how the input potential VCP to the voltage controlled oscillation circuit (VCO) changes when the up signal Up to the circuit changes from High level to Low level and at the same time the down signal Down changes from Low level to High level. Shown in a).

  Further, as the present invention example 2, when the charge pump having the circuit configuration shown in FIG. 3 is used in the PLL circuit configuration shown in FIG. 1, when the output of the PLL circuit is locked and the loop is stabilized, The state of the change of the input potential VCP to the voltage controlled oscillation circuit (VCO) when the up signal Up to the charge pump circuit changes from the High level to the Low level and the down signal Down changes from the Low level to the High level at the same time. Shown in 5 (b).

In the above invention examples 1 and 2 was adjusted to Vdd = 3.3V, the node _{n 1} potential = 1.65V.

  As a comparative example 1, when the charge pump having the circuit configuration shown in FIG. 7 is used in the PLL circuit configuration shown in FIG. 1, when the output of the PLL circuit is locked and the loop is stabilized, the charge pump circuit FIG. 5 (c) shows a change in the input potential VCP to the voltage controlled oscillation circuit (VCO) when the up signal Up to the high level changes from the high level to the low level and at the same time the down signal Down changes from the low level to the high level. ).

  As shown in FIG. 5, the fluctuation of the input potential VCP is a voltage based on the opening / closing of the switch by the up signal Up or the down signal Down in any of the first and second invention examples and the first comparative example. A change occurs, and accordingly, the potential of the input voltage VCP to the voltage controlled oscillation circuit (VCO) slightly fluctuates.

  However, the width of the fluctuation was about 1.46 V in Comparative Example 1 according to the prior art, whereas 0.64 V in Invention Example 1 and 0.61 V in Invention Example 2 were suppressed to less than half. The effect of the present invention was confirmed. This effectively suppresses the occurrence of jitter in the oscillation output signal of the PLL circuit.

It is a figure which shows an example of the PLL circuit structure to which the charge pump circuit which concerns on this invention is applied. It is a figure which shows an example of the circuit structure of the charge pump circuit which concerns on this invention. It is a figure which shows another example of the circuit structure of the charge pump circuit which concerns on this invention. It is a figure which shows an example of the DLL circuit structure to which the charge pump circuit which concerns on this invention is applied. It is a figure which shows the Example of this invention, and the change of the input electric potential VCP to the voltage controlled oscillation circuit based on a prior art. It is a figure which shows the general circuit structure of the charge pump circuit which comprises the PLL circuit which concerns on a prior art. It is a figure which shows the other circuit structure of the charge pump circuit which comprises the PLL circuit which concerns on a prior art.

Explanation of symbols

1a, 1b, 3a, 3b Switch 2, 4 Constant current source 5, 6 Inverter 7, 8 Load transistor 9, 10 Resistor 20 PLL (Phase Locked Loop) circuit 21 Phase comparison circuit (PFD)
22 Charge pump circuit (CP)
23 Loop filter (LPF)
24 Voltage controlled oscillator (VCO)
200 DLL (Delay Locked Loop) Circuit 201 Voltage Control Delay Circuit (VCDL)

Claims (4)

The charge pump circuit is connected to a first constant current source connected to a first power source having a high potential and a second power source having a potential lower than a potential connected to the first constant current source. A second constant current source,
Further, when the charge pump circuit receives an up signal for increasing the frequency of the oscillation output signal from the phase comparison circuit, the charge pump circuit is turned on when the received up signal is at a high level, and the first constant current source The first switch for outputting the current from the first charge pump circuit to the output side of the charge pump circuit and ON when the received up signal is at the low level, and the current from the first constant current source is A second switch for flowing to a node indicating a potential intermediate between the power source and the second power source;
When a down signal for lowering the frequency of the oscillation output signal is received from the phase comparison circuit, the second constant current source is turned on from the output side of the charge pump circuit when the received down signal is at a high level. And a second switch that turns on when the received down signal is at a low level, and from the node that shows an intermediate potential between the first power source and the second power source. And a fourth switch for passing a current to the source.   2. The node having an intermediate potential between the first power source and the second power source is a node having an intermediate potential obtained by resistance division between the first power source and the second power source. The charge pump circuit described. In a PLL circuit that includes a phase comparison circuit, a charge pump circuit, a loop filter, and a voltage controlled oscillation circuit, and generates an oscillation output signal synchronized with a reference signal,
3. A PLL circuit using the charge pump circuit according to claim 1 or 2 as the charge pump circuit. In a DLL circuit composed of a phase comparison circuit, a charge pump circuit, a loop filter, and a voltage control delay circuit,
3. A DLL circuit using the charge pump circuit according to claim 1 or 2 as the charge pump circuit.

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