JPH05235758A - Phase locked loop - Google Patents

Abstract

PURPOSE:To double a variable range by using an inverting amplifier and a changeover switch so as to select it that an output of a phase comparator is directly fed to a voltage controlled oscillator and voltage with inverted polarity of a voltage change is applied. CONSTITUTION:An input reference frequency signal fr from a reference oscillator (RO) 1 is fed to a phase comparator (PC) 2 and a voltage controlled oscillation signal fo from a voltage controlled oscillator (VCO) 6 is fed back to the PC 2 and an output proportional to a phase difference resulting from phase comparison is integrated by a filter (LPF) 3 and the result is fed to the VCO 6. In this case, an inverting amplifier (TAMP) 4 in inverting a polarity of a change in an input voltage to the VCO 6 and a changeover switch (SW) 5 selecting an output of the IAMP 4 or an output of the VCO 6 are provided to a pre-stage of the VCO 6 to double the set value of the frequency divider (DIV) 9 arranged in a feedback loop equivalently and to double the variable range of the oscillating frequency of the VCO 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter referred to as PLL) circuit, and particularly to increasing the number of channels without improving the performance of a frequency divider used in a PLL circuit of a mixing system. The present invention relates to such a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, PLL circuits have been widely used in transceivers and the like. The most general conventional PLL circuit constitutes a closed loop control system so that the output is locked to the input reference frequency signal fr.

A configuration shown in FIG. 7 is known as a basic circuit of a PLL circuit. In FIG. 7, 1 is a reference oscillator (hereinafter referred to as R
Input reference frequency signal fr (hereinafter referred to as fr).
Is output). The fr from RO1 is supplied to the phase comparator (hereinafter referred to as PC) 2 at the next stage.

In this PC 2, a feedback frequency signal (hereinafter referred to as f) from a voltage controlled oscillator (hereinafter referred to as VCO) 6 which will be described later.
V) and an output proportional to the phase difference between fr and fv is output from the VCO 6.

Since the output of PC2 contains a lot of high frequency components, it is integrated by a low pass filter (hereinafter referred to as LPF) 3 to form a direct current control signal, which is supplied to VCO 6 to produce VC.
O6 voltage controlled oscillation frequency signal fo (hereinafter referred to as fo)
Is output.

Although there is a method in which a feedback loop is directly fed back from the VCO 6 to the PC 2, a programmable counter or a frequency divider (hereinafter referred to as DIV) 9 is usually provided in the feedback loop.
Is provided. In a PLL circuit with such a configuration, VC
The fo of O6 is equal to fr and fv. Fo = N · fr, fr = Δf where Δf is the channel space and N is the division ratio of DIV9. When this division ratio N is changed by 1, it changes in the loop. Since the phase difference between fv and fr is eliminated, fo = (N + 1) · fr, and fo changes by the channel space of fr = Δf. Further, DIV9 has a problem that the upper limit frequency of use is limited.

Further, in the mixing type PLL circuit, fo
When the frequency is high, the local oscillator frequency signal (hereinafter referred to as f _LO ) from the local oscillator (hereinafter referred to as LO) 8 and fo are mixed down by a frequency mixer (hereinafter referred to as MIX) 7 and mixed into DIV 9. Supply as fl = fo-f _LO . In this case, if the division ratio of DIV9 is 1 / N, D
The output of IV9 is fv = fo−f _LO / N.

[0008]

In the above-mentioned conventional configuration, V is used.
After all, fo of CO6 is fo = f_LO-N · fr or fo = f
_LOCan oscillate only one frequency of + N ・ fr
Yes. That is, the division ratio N of DIV9 is changed from 1 to N._maxChange to
If you do, fo is N at the step of fr_maxStrange on the street
So fo is N_maxYou can change only the street
The number of frequency channels is limited by the number of division ratio N of DIV9
There was a problem that it would be done.

Further, there has been a problem that the variation width of fo which is the voltage controlled oscillation frequency in the above-mentioned case is limited by the upper limit of the input frequency which the DIV 9 can divide.

The present invention is intended to provide a PLL circuit which solves the above problems, and its object is to increase the number of channels without improving the performance of the DIV9 inserted in the feedback loop of the PLL circuit. By doubling the VCO 6, the variable range of the VCO 6 can be doubled to the input frequency band that can be divided by the DIV 9.

[0011]

The PLL circuit of the present invention has a reference oscillating means (RO) 1 as shown in FIG.
Input reference frequency signal fr from the phase comparison means (PC)
2 and the voltage controlled oscillation signal fo from the voltage controlled oscillation means (VCO) 6 is fed back to the phase comparison means (PC) 2 and an output proportional to the phase difference obtained by phase comparison is filtered (LP).
F) In the phase-locked loop circuit which is integrated by 3 and supplied to the voltage controlled oscillator (VCO) 6, the inverting means (inverts the polarity of the change of the input voltage with respect to the voltage controlled oscillator (VCO) 6 ( IAMP) 4, and switching means (SW) 5 for switching the output of the inverting means (IAMP) 4 and the output of the phase comparison means (VCO) 6 are provided in the preceding stage of the voltage controlled oscillation means (VCO) 6 and are provided in the feedback loop. The setting value of the arranged frequency dividing means (DIV) 9 is equivalently doubled, and the variable range of the oscillation frequency of the voltage controlled oscillation means (VCO) 6 is doubled.

An example of the second PLL circuit of the present invention is shown in FIG.
As shown in FIG. 3, the inverting means (IAMP) 4 and the switching means (SW) 5 are provided after the filtering means (LPF) 3.

An example of the third PLL circuit of the present invention is shown in FIG.
As shown in FIG. 3, the inverting means (hereinafter referred to as IAMP) 4 and the switching means (hereinafter referred to as SW) 5 are provided in front of the filtering means (LPF) 3.

[0014]

The PLL circuit of the present invention is provided with IAMP4 and SW5 to directly supply the output of PC2 to VCO6 and P
The voltage obtained by inverting the polarity of the voltage change of the output of C2 is VCO
The number of channels is set to twice the number of division ratios of DIV9 by switching the state of supplying to 6 by IAMP4 and SW5, and the variable range of fo of VCO6 is set to 2 of the input frequency band in which DIV6 can divide. It is designed to be doubled.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit in which an embodiment of the present invention is applied to a transceiver will be described in detail below.

In FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and duplicate description will be omitted. In FIG. 1, the output terminal from the LPF3 provided in the latter stage of the PC2 to which fr is supplied from the RO1 is I
Connected to fixed contact a of AMP4 and SW5, IAMP
The output end of 4 is connected to the fixed contact b of SW5, and the movable contact piece of SW5 is connected to the input terminal of VCO6.

IAMP4 and SW in the above configuration
The operation of No. 5 will be described.

When the movable contact piece of SW5 is tilted to the fixed contact piece a side, it is a mixing type PLL circuit similar to the conventional structure, and the output of LPF3 is directly supplied to VCO6.
The fo of CO6 is fo = f _LO + N · fr (or f _LO −N ·
fr).

Next, when the movable contact piece of SW5 is switched to the fixed contact b side, the output of LPF3 is supplied to IAMP4 which inverts the polarity of the voltage and is supplied to VCO6, so fo is fo = f _LO. −N · fr (or f _LO + N · fr).

FIG. 2 shows the relationship between the input voltage Vin applied to the VCO 6 by switching with the SW 5 and fo of the oscillation frequency signal from the VCO 6. In FIG. 2, the horizontal axis indicates Vin and the vertical axis indicates fo.

As can be seen from FIG. 2, when the movable contact piece of SW5 is set to the fixed contact a side, the range of change of Vin is the range shown from V ₂ to V ₃ , and the movable contact piece of SW5 is fixed contact. When set to the b side, the range of change of Vin is from V ₁ to V ₂
The range is up to.

Further, in the range of, the division ratio N of DIV9 is
Vin increases to V₂To V ₁Direction to decrease
, Fo decreases. In the range of
When the ratio N is increased, Vin becomes V₂To V₃Increase to
As the direction changes, fo increases. Thus, I
The AMP4 reverses the increase / decrease in the division ratio N and the increase / decrease in the input voltage Vin.
Has the effect of turning. Input / output characteristics of IAMP4
Is expressed as Vo = Vc-kVi, where the input voltage is Vi and the output voltage is Vo. However, k and Vc are constants, and k> 0.
Is.

Further, in the conventional circuit without SW5,
Although it was possible to oscillate only one of the frequencies fo = f _LO −N · fr or f _LO + N · fr, provision of SW5 enables oscillation at any frequency. When the frequency division ratio N is changed from I to N _max , fo changes in N _max ways in the step of fr. Therefore, the oscillation frequency fo, which has not been changed up to N _max in the past, can be changed to 2 · N _max according to the present invention.

The change width of fo at this time is 2 · N _max
· Fr, which is twice the conventional change width N _max · fr. At this time, the maximum input frequency of DIV9 is N _max · fr
Therefore, the same as the maximum input frequency of the frequency divider in the conventional PLL circuit is sufficient. Further, when fr is set to fr / 2, the variation width of the oscillation frequency remains N _max · fr,
The frequency step is fr / 2, which is 1/2 of the conventional frequency step. That is, fine frequency control becomes possible.

Next, the above-mentioned LPF3, IAMP4 and S
A specific configuration of W5 will be described with reference to FIG.

In FIG. 3, the comparison output from PC3 is a resistor R ₁
Is supplied to the inverting input terminal of an operational amplifier (hereinafter, referred to as OP) via OP, the non-inverting input terminal of OP is grounded, and a resistor R ₂ and a capacitor C are provided between the output terminal of OP and the inverting input terminal.
The series circuit of ₁ is connected to form the LPF 3.

The output terminal of the OP is connected to one end of the resistor R _3, the other end of the resistor R ₃ is connected to the base of NPN transistor Q ₁ is grounded via a capacitor C _2. The collector of the transistor Q ₁ is a resistor R ₄
Is connected to the Vcc voltage source via the and is also connected to the fixed contact b of SW5, and the emitter is directly grounded. The connection point of OP and the resistor R ₃ and the fixed contact a of SW5 are directly connected, and the movable contact piece of SW5 is connected to VCO6 to make it
AMP4 and SW5 are configured.

In the above-mentioned configuration, in the transceiver, the fr of RO is 10 KHz, and fo = 50 MHz at the time of transmission,
This shows the configuration of the PLL circuit for oscillating fo = 59 MHz from the VCO 6 at the time of reception. The fr (10 KHz) input from RO1 is input to the LPF3 of the OP and integrated, and the output of the LPF3 uses the NPN transistor Q ₁ . Is supplied to the IAMP4, and the output voltage of the LPF3 is inverted and output to the collector of the transistor Q ₁ . This output is supplied to the VCO 6 as the inversion voltage of the LPF via the fixed contact b of SW5 → the movable contact piece.

On the other hand, the output of the LPF3 of the OP is directly supplied through the fixed contact a → movable contact piece of the SW5 without passing through the IAMP4 to supply the common mode voltage of the LPF3 to the VCO6.

However, the Vin of the LPF 3 shown in FIG. 2 is V ₂
At this time, the resistors R ₃ and R ₃ are arranged so that the output of IAMP4 becomes V _2.
4, by selecting the value of capacitor C _2, the same Vin = V ₂ be in contact SW5 to the fixed contact a or b side of the movable contact piece SW5 of when the output V ₂ of LPF3 is VCO6
Is supplied to.

As a result, the output of the LPF ₃ changes from V ₂ to V ₃ , while the output of the IAMP 4 reverses the polarity of the input voltage (inverts the increasing / decreasing direction of change) so as to change from V ₂ to V ₁ . Will change.

Table 1 shown below shows the positional relationship between the frequency division ratio N and SW5 for obtaining fo of VCO 6 shifted by 9 MHz between 50 MHz and 59 MHz during transmission and reception.

[0033]

[Table 1]

That is, in this example, SW5 is switched to b at the time of transmission and switched to a at the time of reception, whereby the frequency division ratio N = 450,
fr = 10 KHz, f _LO = 54.5 MHz, fl = 4.
9MHz of fo = 50 and 59MHz if 5MHz
The shifted fo is obtained.

FIG. 4 shows another structure of the present invention.
Corresponding parts are designated by the same reference numerals and redundant description will be omitted.

In this configuration, I is connected between the PC2 and the LPF3.
This is the case where SW5 is provided in the same manner as AMP4. Even in the case of this configuration, it is possible to operate in exactly the same manner as in FIG.

FIG. 5 shows the case of the digital type PC 2.
An example of a circuit diagram of IAMP4, SW5, and LPF3 of the PLL circuit is shown. In this case, since the output of PC2 is either (H) or (L), IAMP4 is set to N as shown in the figure.
Since it is an OT circuit, the design is simple.

FIG. 6 shows an example in which an exclusive OR circuit is used for IAMP4 and SW5. In the exclusive OR circuit of FIG. 6, when the switching control voltage is applied to the switching control input terminal c (H), the exclusive OR circuit functions as a NOT circuit, and is equivalent to when SW5 is set to b in FIG. On the other hand, in FIG. 6, the switching control input terminal c
When the switching control voltage is not applied to (L), the polarity is not inverted in the exclusive OR circuit. Therefore, in FIG.
This is equivalent to when 5 is set to a. As described above, by realizing the NOT circuit and the SW5 by one circuit, not only the circuit can be downsized, but also the polarity can be controlled by the switching control voltage instead of the switching by the SW5. Therefore, the PLL circuit of FIG. 6 can control the frequency more easily than the circuit of FIG.

In the present invention, as described above, the PLL circuit is provided with the IAMP4 for inverting the polarity of the voltage change of the output of the PC2 and the switching SW5 so as to switch the state to be added to the VCO6. The number of ratio N is 2
It is possible to double the number, and it is possible to equivalently increase the number of frequency division ratios N of the DIV 9 to two times. Further, the range in which the oscillation frequency fo of the VCO 6 can be divided by the DIV 9 is input. The frequency band of the DIV 9 can be doubled, and the frequency characteristics of the DIV 9 can be equivalently doubled. Furthermore, if the variable range of the oscillating frequency is not changed, it is possible to obtain the one that can control the frequency step with a fineness of 1/2 of the conventional one.

[0040]

According to the PLL circuit of the present invention, the number of required channels can be doubled without improving the performance of the frequency divider used in the PLL circuit.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a PLL circuit of the present invention.

FIG. 2 is a characteristic diagram of a voltage controlled oscillation frequency signal fo with respect to an input voltage of a VCO.

FIG. 3 is a circuit diagram of IAMP, SW, and LPF used in FIG.

FIG. 4 is a system diagram showing another configuration of the PLL circuit of the present invention.

FIG. 5 is an inverter, SW, and LPF used in FIG.
FIG.

FIG. 6 is another circuit diagram of the inverter and SW used in FIG.

FIG. 7 is a system diagram of a conventional PLL circuit.

[Explanation of symbols]

 1 Reference Oscillator (RO) 2 Phase Comparator (PC) 3 Low Pass Filter (CPF) 4 Inversion Amplifier (IAMP) 5 Changeover Switch (SW) 6 Voltage Controlled Oscillator (VCO) 7 Frequency Mixer (MIX) 8 Local Oscillator (LO) 9 Divider (DIV)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 Z

Claims (3)

[Claims] 1. An output proportional to a phase difference obtained by supplying an input reference frequency signal from the reference oscillating means to the phase comparing means and feeding back the voltage controlled oscillating signal from the voltage controlled oscillating means to the phase comparing means. In a phase-locked loop circuit that integrates the signal with the filtering means and supplies the voltage-controlled oscillation means with the inverting means for inverting the polarity of the change in the input voltage to the voltage oscillation controlling means, and the output of the inverting means. And a switching means for switching the output of the phase comparison means in front of the voltage controlled oscillating means to equivalently double the set value of the frequency dividing means arranged in the feedback loop and to perform the voltage control. A phase locked loop circuit characterized in that the variable range of the oscillation frequency of the oscillation means is doubled. 2. The phase-locked loop circuit according to claim 1, wherein the inverting means is arranged at a stage subsequent to the filtering means in the loop. 3. The phase-locked loop circuit according to claim 1, wherein the inverting means is arranged in the loop before the filtering means.