JPH05235757A - Phase locked loop - Google Patents

Abstract

PURPOSE:To double an input frequency band capable of frequency division by providing a changeover circuit to a pre-stage of a phase comparator and replacing a reference side input terminal of the phase comparator with a comparator side input terminal of the phase comparator. CONSTITUTION:An input reference frequency signal fr from a reference oscillator (RO) 1 is fed to a phase comparator (PC) 2 and a voltage controlled oscillator signal fo from a voltage controlled oscillator (VCO) 6 is fed back to the PC2 via a frequency divider (DIV) 9 to implement phase comparison and an output proportional to the phase difference is integrated by a filter (LPF) 3 and the result is fed to the VCO 6. In this case, a changeover circuit (SW) 5 is provided to input outputs of the RO1, the DIV9 to the reference side input terminal and the comparator side input terminal of the PC2 while switching them mutually, the set value of the DIV9 is doubled equivalently thereby doubling the variable range of the oscillating frequency. Thus, the required number of channels in doubled without improving the performance of the DIV 9 used for the PLL circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter referred to as PLL) circuit, and particularly to increasing the number of channels without improving the performance of a frequency divider used in a PLL circuit of a mixing system. The present invention relates to such a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, PLL circuits have been widely used in transceivers and the like. The most general conventional PLL circuit constitutes a closed loop control system so that the output is locked to the input reference frequency signal fr.

A configuration shown in FIG. 5 is known as a basic circuit of a PLL circuit. In FIG. 5, reference numeral 1 is a reference oscillator (hereinafter R
Input reference frequency signal fr (hereinafter referred to as fr).
Is output). The fr from RO1 is supplied to the phase comparator (hereinafter referred to as PC) 2 at the next stage.

In this PC 2, a feedback frequency signal (hereinafter referred to as f) from a voltage controlled oscillator (hereinafter referred to as VCO) 6 which will be described later.
V) and an output proportional to the phase difference between fr and fv is output from the VCO 6.

Since the output of PC2 contains a lot of high frequency components, it is integrated by a low pass filter (hereinafter referred to as LPF) 3 to form a direct current control signal, which is supplied to VCO 6 to produce VC.
A voltage controlled oscillation frequency signal fo (hereinafter referred to as fo) is output from O6.

Although there is a method in which a feedback loop is directly fed back from the VCO 6 to the PC 2, a programmable counter or a frequency divider (hereinafter referred to as DIV) 9 is usually provided in the feedback loop.
Is provided. In a PLL circuit with such a configuration, VC
The fo of O6 is equal to fr and fv. Fo = N · fr, fr = Δf where Δf is the channel space and N is the division ratio of DIV9. When this division ratio N is changed by 1, it changes in the loop. Since the phase difference between fv and fr is eliminated, fo = (N + 1) · fr, and fo changes by the channel space of fr = Δf. Further, DIV9 has a problem that the upper limit frequency of use is limited.

Further, in the mixing type PLL circuit, fo
Local oscillation frequency signal (hereinafter referred to as f _LO) frequency mixer to fo and (hereinafter referred to as MIX) 7 mixed frequency mixes down DIV9 in from the local oscillator (hereinafter referred to as LO) 8 like when high Provide as signal fl = fo-f _LO . In this case, if the division ratio of DIV9 is 1 / N,
The output of DIV9 is fv = fo−f _LO / N.

[0008]

In the above-mentioned conventional configuration, V is used.
After all, fo of CO6 is fo = f_LO-N · fr or fo = f
_LOCan oscillate only one frequency of + N ・ fr
Yes. That is, the division ratio N of DIV9 is changed from 1 to N._maxChange to
If you do, fo is N at the step of fr_maxStrange on the street
So fo is N_maxYou can change only the street
The number of frequency channels is limited by the number of division ratio N of DIV9
There was a problem that it would be done.

Further, there has been a problem that the variation width of fo which is the voltage controlled oscillation frequency in the above-mentioned case is limited by the upper limit of the input frequency which the DIV 9 can divide.

The present invention is intended to provide a PLL circuit which solves the above problems, and its object is to increase the number of channels without improving the performance of the DIV9 inserted in the feedback loop of the PLL circuit. By doubling the VCO 6, the variable range of the VCO 6 can be doubled to the input frequency band that can be divided by the DIV 9.

[0011]

The PLL circuit of the present invention has a reference oscillating means (RO) 1 as shown in FIG.
Input reference frequency signal fr from the phase comparison means (PC)
2 and supplies the voltage-controlled oscillation signal fo from the voltage-controlled oscillation means (VCO) 6 to the phase comparison means (PC) 2 via the (D1V) 9 of the frequency division means to compare the phases to obtain a phase difference. In the phase locked loop circuit in which the proportional output is integrated by the filtering means (LPF) 3 and supplied to the voltage controlled oscillation means (VCO) 6, the reference oscillation means (RO) 1
And a switching means (SW) 5 for inputting the output of the variable frequency dividing means (DIV) 9 to the reference side input terminal of the phase comparing means (PC) 2 and the comparing side input terminal, and inputting the variable frequency dividing means. The setting value of (DIV) 9 is equivalently doubled to double the variable range of the oscillation frequency.

[0012]

In the PLL circuit of the present invention, SW5 is provided in front of the PC2 and the reference side input end and the comparison side input end of the PC2 are exchanged. Therefore, the number of channels is not twice the number of the division ratio of DIV9. , VCO6 fo variable range DIV9
Can be increased to twice the input frequency band that can be divided.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit in which an embodiment of the present invention is applied to a transceiver will be described in detail below.

In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and duplicate description will be omitted.

In the PLL circuit of this example, fr supplied from RO1 is two double-pole double-throw switches SW1 and SW2.
Is supplied to the switching circuit (SW) 5. Switch S
The fixed contact a _{1 of} W1 and the fixed contact b _{2 of the} switch SW2 are commonly connected to each other, and the input terminal c is supplied with the fr of RO1.
It is connected to the.

Fixed contact b of the switch SW1 of the switching circuit 5
₁ and fixed contact a ₂ of switch SW ₂ are commonly connected and D
It is connected to the input terminal d to which fv of IV9 is supplied.

The movable contact pieces of the switches SW1 and SW2 of the switching circuit 5 are connected to the output terminals e and f. The output terminal e is a plus (+) input terminal of PC2 and the output terminal f is a minus (-) input terminal of PC2. It is connected to the. Other configurations are the same as those in FIG.

2A for explaining the operation of the switching circuit having the above-mentioned configuration with reference to FIG. 2, the switching circuit 5 of FIG. 1 is extracted and shown, and the movable contact pieces of the switches SW1 and SW2 are fixed in conjunction with each other. When the contacts are switched to the contacts a ₁ and a ₂ , the signals supplied to the input terminals c and d are output to the output terminals e and f as shown in FIG. 2B.

Similarly, when the movable contact pieces of the switches SW1 and SW2 are interlocked and switched to the fixed contacts b ₁ and b ₂ side, FIG.
As shown in FIG. 5, the signals supplied to the input terminals c and d are inverted and output to the output terminals f and e.

The operation of the PC2 described above will be described. The PC2 has two ± input terminals, and the output of the PC2 is supplied to the LPF3.

When the phase of the input signal supplied to the-input terminal is delayed as compared with the input signal supplied to the + input terminal of PC2, PC2 increases the output voltage to LPF3. Conversely, if the phase of the input signal supplied to the-input terminal is ahead of the phase of the input signal supplied to the + input terminal of PC2, PC2 decreases the output voltage to LPF3, and the + input terminal and-input. If the phases of the input signals supplied to the terminals match, the output voltage of the LPF 3 has a constant value.

As described with reference to FIG. 5, the output frequency of RO1 is fr, the output frequency of DIV9 is fv, and MIX7.
Output frequency of fl, LO8 output frequency is f _LO , VC
O6 dividing ratio of the output frequency is fo DIV9 of the N, the maximum value of the frequency dividing ratio N _{ma x.} Also, VCO6
Is a characteristic that monotonically increases fo as the input voltage increases, the fl of MIX7 is Shall be Further, the component of f _LO + fo generated in MIX7 is removed by a filter or the like provided in MIX7.

In the PLL circuit, the operation of PC2 causes P
By operating so that the phase of the input supplied to the + input terminal of C2 and the phase of the input supplied to the − input terminal match, the oscillation frequency fo of the VCO 6 becomes constant and locked.

[0024] Killing movable contact piece of the switch SW1 and SW2 of the switching circuit 5 to a ₁ and a ₂ side, is fr, which is the output of RO1 to PC2 positive input terminal, - DIV9 input terminal
Fv is supplied, but at this time fo of VCO6

Fo = f _LO + N · fr (2) or fo = f _LO −N · fr (3)

When, the PLL circuit is locked.

On the other hand, the switches SW1 and S of the switching circuit 5
When the movable contact piece of W2 is tilted toward the fixed contacts b ₁ and b ₂ ,
While the fv which is the output of DIV9 is supplied to the + input terminal of C2 and the fr which is the output of RO1 is supplied to the − input terminal, the fo of VCO6 is fo = f _LO −N · fr (4) or fo = f _LO + N · fr (5)

When, the PLL circuit is locked. Whether fo becomes the expression (2), (4) or the expression (3), (5) depending on the switching of the switching circuit 5 is determined by the relationship between the input and output polarities of the MIX 7 and the DIV 9.

Switches SW1 and SW of this switching circuit 5
It will be described below that the operation of the PLL circuit differs depending on the difference between the two switching states. Now switches SW1 and SW2
Let us consider the value of fo depending on the switching state of the above equations (2) and (4). In this case, when fv is lower than fr, the phase relationship is such that the phase of the − input terminal is delayed as compared with the phase to the + input terminal of PC2.

[0030] switching the movable contact piece of the switch SW1 and SW2 of the switching circuit 5 to a ₁ and a ₂ side, PC2 of the + input terminal RO1 of fr is - fv of DIV9 is applied to the input terminal, the fv The value is fv = fo-f _LO / N. In this equation, if fo is smaller than the value of equation (2), fv becomes lower than fr.

Therefore, the-input phase lags behind the + input terminal phase of PC2. As a result, the output voltage of the LPF 3 is increased by the action of the PC 2 and the fo of the VCO 6 is increased. Conversely, when fo is higher than the value of expression (2), f
Since v becomes higher than fr, VCO is generated by the function of PC2.
The fo of 6 is reduced.

In this way, the PLL circuit operates so that fv = fr by the operation of PC2, and as a result fo is (2)
The value of the formula becomes constant and the lock state is maintained. In this case, the PLL circuit does not lock when fo is the value of the expression (3).

On the other hand, the switches SW1 and SW of the switching circuit 5
2 movable contact pieces to fixed contact b₁And b ₂Switch to the side,
Fv of DIV9 to + input terminal of PC2 and R to-input terminal
The fr of O1 is added, and the output fv of DIV9 at this time is
fv = f_LO-Fo / N. From equation (4), fo is f
_LOIs smaller than fv = fo−f_LOCompared with / N
Then fo and f_LOIs reversed. With this formula
If fo is smaller than the value of expression (4), fv is fr
Will be higher than.

Therefore, the-input phase leads the phase of the + input terminal of PC2. As a result, the output voltage of LPF3 is reduced by the action of PC2, and fo of VCO6 is reduced. On the contrary, when fo is higher than the value of the equation (4), fv becomes lower than fr, and therefore the PC2 acts to increase fo of the VCO 6.

In this way, the PLL circuit operates so that fv = fr by the operation of PC2, and as a result fo is (4)
The value of the formula becomes constant and the lock state is maintained. In this case, the PLL circuit does not lock when fo is the value of the expression (5). Thus, the switch SW1 or SW2 of the switching circuit 5 reverses the input supplied to the + input terminal and the − input terminal of the PC2, and the PC2 operates in the opposite direction with respect to the phase relationship between the output fr of the RO1 and the output fv of the DIV9. Have the effect of Therefore, by switching the switches SW1 and SW2, it is selected whether fo is larger or smaller than f _LO, and fo takes a value of the expression (2) or the expression (4).

In the conventional PLL circuit not provided with the switching circuit 5, only the frequency of fo = f _LO −N · fr or f _LO + N · fr can be oscillated.
By providing W1 and SW2, it becomes possible to oscillate by selecting any frequency. Then, when N is changed from 1 to N _max , fo changes in N _max ways in the step of fr. Therefore, according to the present invention, the oscillation frequency can be changed only up to N _max.
It can be changed as N _max .

Further, the change width of the frequency at this time is 2N _max.
· Fr, which is twice the conventional change width N _max · fr. At this time, the maximum input frequency of DIV9 is N _max · fr, which is the same as the maximum input frequency of DIV9 in the conventional PLL circuit. If fr is fr / 2, f
While the change width of o remains N _max · fr, the frequency step becomes fr / 2, which is ½ of the conventional value. That is, fine frequency control becomes possible.

The VCO is switched by the switching circuit as described above.
FIG. 3 shows the relationship between the input voltage Vin supplied to 6 and fo of the oscillation frequency signal from the VCO 6. In Figure 3, the horizontal axis is V
In, the vertical axis represents fo.

As can be seen from FIG. 2, the range of change of Vin when the movable contact pieces of the switches SW1 and SW2 of the switching circuit 5 are set to the fixed contact a side is the range shown from V ₂ to V ₃ , When the movable contact pieces of the switches SW1 and SW2 of the switching circuit 5 are set to the fixed contact b side, the change range of Vin is V
_The range is from ₁ to V ₂ .

Further, in the range of, the division ratio N of DIV9 is
Vin increases to V₂To V ₁Direction to decrease
, Fo decreases. In the range of
When the ratio N is increased, Vin becomes V₂To V₃Increase to
As the direction changes, fo increases. Like this
The replacement circuit 5 reverses the increase / decrease in the division ratio N and the increase / decrease in the input voltage Vin.
Has the effect of turning. Next, the components of the switching circuit 5 described above
The physical structure will be described with reference to FIG.

In FIG. 4, c and d are the same output terminals as the input terminals e and f of the switching circuit 5 shown in FIG. 1, and g is the switching control input terminal. The input terminals c and d are connected to one input terminals of the first to fourth AND circuits 41, 42, 43 and 44, and the switching control input terminal g is connected to each of the AND circuits 41 and 44 via a knot circuit 47. It is connected to the other input terminal and is directly connected to the AND circuit 4 from the switching control input terminal g.
It is connected to the other input terminal of each of 2 and 43.

The output terminals of the AND circuits 41 and 42 are connected to the input terminals of the OR circuit 45, and the AND circuit 43
The output terminals of 44 and 44 are connected to the input terminals of the OR circuit 46. Further, the output terminals of the OR circuits 45 and 46 are connected to the output terminals e and f of the switching circuit 5.

The AND circuits 41 and 42, the OR circuit 45, and the knot circuit 47 having the above-described configuration form a first selector similar to the switch SW1.
4, switch the OR circuit 46 and the knot circuit 47, and switch SW
A second selector similar to that of No. 2 is configured. When the control signal LOW (L) is supplied to the switching control input terminal g, fr supplied to the input terminal c of the switching circuit 5 is the output coal terminal e.
Is output to the output terminal f and is supplied to the input terminal d.
2 and the movable contact pieces of SW1 and SW2 are tilted to a in FIG.

Next, the switching control input terminal g is supplied with H of the control signal.
When high (H) is supplied, fr supplied to the input terminal c of the switching circuit 5 is output to the output terminal f, fv supplied to the input terminal d is output to the output terminal e, and SW1 in FIG.
Also, the input / output state is switched in the same manner as when the movable contact piece of SW2 is switched to b. In this case, since the input signal of the PC 2 is binarized to either H or L, the switching circuit 5 can use the selector circuit as shown in the figure and does not need to use a mechanical switch circuit. There is an effect that the reliability of the circuit is increased.

By using the switching circuit 5 as described above, 50 MHz is received at the time of transmission of the transceiver and 59 MH is changed to 9 HM at the time of reception.
Table 1 below shows the frequency division ratio and the switching state of the switching circuit 5 when the VCO 6 is oscillated by being shifted.

[0046]

[Table 1]

That is, in this example, the switches SW1 and SW
The frequency division ratio N = 450, fr = 10 KHz, f _LO = 54.5 by switching 2 to b during transmission and to a during reception.
MHz and fl = 4.5 MHz, fo = 50 and 5
The fo obtained by shifting 9 MHz from 9 MHz is obtained.

As described above, in the PLL circuit of the present invention, the switching circuit 5 is provided, and the output fr of RO1 is input to the + input of PC2 as DI.
RO1 and the state in which the output fv of V9 is applied to the-input of PC2
Of the output fv of DIV9 to the-input of PC2
The number of channels can be increased to twice the number of frequency division ratios N of DIV9 because it is switched to the + input of C2, and the number of frequency division ratios N of DIV9 can be equivalently increased to twice. It is possible to increase the variable range of the oscillation frequency fo of the VCO 6 to twice the band of the input frequency that can be divided by the DIV 9, and the frequency characteristic of the DIV 9 is equivalently improved to 2 times. It can be done. Furthermore, if the variable range of the oscillating frequency is not changed, it is possible to obtain the one that can control the frequency step with a fineness of 1/2 of the conventional one.

[0049]

According to the PLL circuit of the present invention, the number of required channels can be doubled without improving the performance of the frequency divider used in the PLL circuit.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a PLL circuit of the present invention.

FIG. 2 is an operation explanatory diagram of a switching circuit used in the present invention.

FIG. 3 is a characteristic diagram of a voltage controlled oscillation frequency signal fo with respect to an input voltage of a VCO.

FIG. 4 is a circuit diagram showing another embodiment in which a switching circuit used in the present invention is digitized.

FIG. 5 is a system diagram of a conventional PLL circuit.

[Explanation of symbols]

 1 Reference Oscillator (RO) 2 Phase Comparator (PC) 3 Low Pass Filter (LPF) 5 Switching Circuit (SW) 6 Voltage Controlled Oscillator (VCO) 7 Frequency Mixer (MIX) 8 Local Oscillator (LO) 9 min Circulator (DIV)

Claims (1)

[Claims] 1. A reference frequency signal from a reference oscillating means is supplied to a phase comparing means, and a voltage controlled oscillating frequency signal from a voltage controlling oscillating means is fed back to the phase comparing means via a frequency dividing means for phase comparison. In a phase-locked loop circuit in which the output proportional to the phase difference is integrated by the filtering means and supplied to the voltage controlled oscillating means, the phase comparison between the outputs of the reference oscillating means and the frequency dividing means is performed. The reference side input end of the means and the comparison side input end are replaced with switching means for inputting, and the set value of the frequency dividing means is equivalently doubled to double the variable range of the oscillation frequency. A phase-locked loop circuit characterized in that