JP2740001B2 - Frequency adjustment circuit of signal processing filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a signal processing filter such as an active filter built in, for example, an IC (integrated circuit). The present invention relates to improvement of a frequency adjustment circuit for automatically adjusting.

(Prior Art) As is well known, as a means for automatically adjusting the center frequency of a signal processing filter such as an active filter built in an IC, for example, an automatic frequency adjustment circuit using a PLL (phase locked loop) circuit is known. is there.

Further, among automatic frequency adjustment circuits using a PLL circuit, there are a type using a VCO (voltage controlled oscillator) and a type using a VCF (voltage control filter) instead of the VCO.

The time constants of the VCO and VCF are both configured by the same circuit as the signal processing filter. Therefore, VCO or V
By applying a voltage for controlling the frequency response of the CF to the signal processing filter, the frequency response of the signal processing filter is controlled to have desired characteristics.

FIG. 4 shows a conventional automatic frequency adjustment circuit using a VCO. That is, the reference clock supplied to the input terminal 11, the phase comparison circuit 12, the loop filter 13, and the VCO 14
To the PLL circuit 15.

At this time, if the PLL circuit 15 is in a phase locked (locked) state, the closed loop control is performed so that the oscillation frequency fVCO of the VCO 14 becomes equal to the frequency fS of the reference clock.

Then, the output voltage of the loop filter 13 at this time is
By supplying the signal to the time constant circuit of the signal processing filter 16, the center frequency f0 of the signal processing filter 16 can be made equal to the oscillation frequency fVCO of the VCO.

FIG. 5 shows a conventional automatic frequency adjustment circuit using a VCF. That is, by supplying the reference clock supplied to the input terminal 17 to the PLL circuit 21 including the phase comparison circuit 18, the loop filter 19, and the VCF 20, the VCF 2
The closed loop control is performed so that the cutoff frequency fVCF of 0 becomes equal to the frequency fS of the reference clock.

Here, when the VCF 20 is, for example, a second-order LPF (low-pass filter), the input / output phase difference becomes 90 ° at the cutoff frequency fVCF of the VCF 20. Also, if a multiplication circuit is used as the phase comparison circuit 18, the PLL circuit 21 will have a phase difference between the two inputs of 9
When it is 0 °, it is in the synchronized state.

Then, the output voltage of the loop filter 19 at this time is
By supplying the signal to the time constant circuit of the signal processing filter 22, the center frequency fO of the signal processing filter 16 can be made equal to the cutoff frequency fVCF of the VCF 20.

However, in the conventional automatic frequency adjustment circuit as described above, the oscillation frequency fVCO of VCO14 and the cut-off frequency of VCF20
fVCF is controlled by the closed loop control by the PLL circuits 15 and 21 so as to be equal to the frequency fS of the reference clock, while the center frequency fO of the signal processing filters 16 and 22 is
The closed loop control is performed only by adding the output voltages of the loop filters 13 and 19.

Therefore, no matter how the time constant circuit of the VCO 14 or VCF 20 and the time constant circuit of the signal processing filters 16 and 22 are formed by the same circuit, the oscillation frequency fVCO And VCF20 cut-off frequency fVC
There is a problem that F, that is, the frequency fS of the reference clock and the center frequency fO of the signal processing filters 16 and 22 are not equal.

(Problems to be Solved by the Invention) As described above, in the conventional frequency adjustment circuit, the VCO and the VCF
Since the open-loop control only supplies the control voltage supplied to the filter to the signal processing filter, there is a problem that the center frequency of the signal processing filter does not become equal to the frequency of the reference clock due to variations in circuit elements. .

Therefore, the present invention has been made in consideration of the above circumstances, and provides a very good frequency adjustment circuit of a signal processing filter that can correct the center frequency of the signal processing filter to be equal to the frequency of the reference clock. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) A frequency adjustment circuit for a signal processing filter according to the present invention should guide an input signal to a signal processing filter and process the input signal with the signal processing filter. Switching means for guiding a first reference clock of a constant frequency to a signal processing filter during a blanking period when there is no signal, wherein the switching means guides the first reference clock to the signal processing filter; A first control signal for controlling the center frequency of the signal processing filter such that the output of the filter for use and the first reference clock have a phase difference component of a predetermined value; The first control signal is held and supplied to the signal processing filter in a state where the switching means is switched to guide the input signal to the signal processing filter. That.

(Operation) According to the above configuration, the signal processing filter is
Since the switching means guides the first reference clock to the signal processing filter and uses it as the VCF of the PLL circuit, the center frequency of the signal processing filter is set to the first reference clock by closed loop control by the PLL circuit. Negative feedback control can be performed so as to be equal.

In a state where the switching means is switched to guide the input signal to the signal processing filter, the first control signal is held and supplied to the signal processing filter, and the signal processing filter is used for signal processing of the input signal. Since the input signal is used, the signal processing of the input signal can be performed at the correct center frequency.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 23 denotes an input terminal, to which an input signal such as a television signal in which a signal period and a blanking period alternately exist is supplied. In FIG. 1, reference numeral 24 denotes a clock input terminal to which a reference clock having a constant frequency fS is supplied.

Then, the input signal and the reference clock are selectively supplied to the signal processing filter 26 by the switch 25. The output of the signal processing filter 26 is selectively supplied to an output terminal 28 and one input terminal of a phase comparison circuit 29 by a switch 27. A reference clock is supplied to the other input terminal of the phase comparison circuit 29.

Further, the output of the phase comparison circuit 29 is
And a time constant circuit for setting the center frequency fO of the signal processing filter 26 via an S / H (sample / hold) circuit 31.

Here, the gate pulses supplied to the pulse input terminal 32 are supplied to the switches 25 and 27 and the S / H circuit 31. This gate pulse is a signal for determining the signal period of the input signal and the blanking period.

The switches 25 and 27 are set to the first during the blanking period.
The position is switched to the position shown in the figure, and is switched to the position opposite to that shown in the signal period. The S / H circuit 31 is controlled so as not to perform the sample / hold operation during the blanking period, but to perform the sample / hold operation during the signal period.

The operation of the configuration as in the above embodiment will be described below. First, during the blanking period of the input signal, the switches 25 and 27 are switched to the positions shown in FIG.
Reference numeral 31 indicates that the sample / hold operation is not performed.

Therefore, the reference clock is supplied to the phase comparison circuit 29 via the switch 25, the signal processing filter 26, and the switch 27, and the phase is compared with the reference clock. Then, an output voltage corresponding to the phase difference component is generated from the loop filter 30 and supplied to the signal processing filter 26 via the S / H circuit 31, where the center frequency fO of the signal processing filter 26 is used as a reference. It is controlled to be equal to the clock frequency fS.

That is, during the blanking period of the input signal, the signal processing filter 26 is connected to the VCF 20 of the PLL circuit 21 shown in FIG.
Therefore, the closed-loop control by the PLL circuit 21 enables the negative feedback control so that the center frequency of the signal processing filter 26 becomes equal to the frequency fO of the reference clock.

Next, during the signal period of the input signal, the switches 25 and 27 are switched to the positions opposite to the positions shown in FIG. 1, and the S / H circuit 31 performs the sample / hold operation.

Therefore, the S / H circuit 31 holds the output voltage of the loop filter 30 at the time of switching from the blanking period to the signal period, and the center frequency fO of the signal processing filter 26 is fixed by the hold voltage.

The input signal is signal-processed by the signal processing filter 26 via the switch 25, and then is taken out from the output terminal 28 via the switch 27. That is, during the signal period of the input signal, the signal processing filter 26 processes the input signal with the center frequency fO fixed based on the hold voltage of the S / H circuit 31.

Therefore, according to the configuration as in the above embodiment, the signal processing filter 26 is connected to the PLL during the blanking period of the input signal.
Since it is used as the VCF of the circuit, the center frequency f
Negative feedback control can be performed so that O becomes equal to the frequency fS of the reference clock, and accurate signal processing can be performed.

FIG. 2 shows another embodiment of the present invention.
The same parts as those in the drawings are denoted by the same reference numerals. In this embodiment, the case where a reference clock having a frequency equal to the center frequency fO of the signal processing filter 26 cannot be obtained from the outside,
This is particularly effective when the Q of the signal processing filter 26 is high and the capture range cannot be sufficiently widened.

That is, reference numeral 33 in FIG. 2 denotes a clock input terminal, and a frequency fS1 not equal to the center frequency fO of the signal processing filter 26.
Are supplied.

This clock is divided by a frequency divider 3 having a frequency division ratio of 1 / n, 1 / m.
The reference clock is converted into a reference clock having a frequency equal to the center frequency fO of the signal processing filter 26 by a PLL circuit 39 including 4, 35, a phase comparison circuit 36, a loop filter 37 and a VCO 38.

In this conversion, since the oscillation frequency fVCO of the VCO 38 of the PLL circuit 39 can be expressed as fVCO = (m / m) fS1, the values of n and m, which are the division ratios of the frequency dividers 34 and 35, are controlled. By doing so, it is sufficient that fVCO = fO.

Further, the control voltage supplied to the VCO 38, that is, the output voltage of the loop filter 37 is supplied to the signal processing filter 26 via the addition circuit 40, so that the signal processing The center frequency fO of the filter 26 is VCO3
Rough adjustment is made to approximate the oscillation frequency fVCO of FIG.

Further, a control voltage for controlling the signal processing filter 26 as VCF during the blanking period of the input signal, that is, the output voltage of the loop filter 30 is added to the addition circuit 40.
, Fine adjustment for making the center frequency fO of the signal processing filter 26 equal to the oscillation frequency fVCO of the VCO 38 is performed.

For this reason, the signal processing filter 26 operating as a VCF
Even when the Q is high and the capture range is narrow, the fluctuation of the center frequency fO can be suppressed within the capture range by the coarse adjustment by the PLL circuit 39 using the output voltage of the loop filter 37.

The oscillation output of the VCO 38, that is, the reference clock is supplied to the phase comparison circuit 29 via the phase shift circuit 41. When the input / output phase difference at the center frequency fO of the signal processing filter 26 is not 90 °, the phase shift circuit 41 corrects the two input signals of the phase comparison circuit 29 so that the phase difference becomes 90 °. It is for.

FIG. 3 is a partial modification of the embodiment shown in FIG. That is, the switch 27 is deleted, the output of the signal processing filter 26 is supplied to the output terminal 28 and the phase comparison circuit 29, respectively, and the phase comparison circuit 29 is provided with a sample / hold function. The configuration is simplified by controlling the hold operation.

It should be noted that the present invention is not limited to the above embodiments, and can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] As described above in detail, according to the present invention, a very good frequency adjustment circuit of a signal processing filter capable of correcting the center frequency of the signal processing filter to be equal to the frequency of the reference clock. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frequency adjusting circuit of a signal processing filter according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 4 and 5 are block diagrams showing a conventional automatic frequency adjusting circuit. FIG. 11 ... input terminal, 12 ... phase comparator, 13 ... loop filter, 14 ... VCO, 15 ... PLL circuit, 16 ... signal processing filter, 17 ... input terminal, 18 ... phase comparator , 19 ...
... Loop filter, 20 ... VCF, 21 ... PLL circuit, 22 ...
Signal processing filter, 23 input terminal, 24 clock input terminal, 25 switch, 26 signal processing filter, 27 switch, 28 output terminal, 29 phase comparison circuit, 30 …… Loop filter, 31… S / H circuit, 32 ……
Pulse input terminal, 33 input terminal, 34, 35 frequency divider circuit, 36 phase comparator circuit, 37 loop filter, 38
... VCO, 39 ... PLL circuit, 40 ... Addition circuit, 41 ... Phase shift circuit.

Claims (2)

(57) [Claims] An input signal is guided to a signal processing filter, and a first frequency signal having a constant frequency is supplied to the input signal during a blanking period in which there is no signal to be processed by the signal processing filter.
Switching means for guiding the reference clock to the signal processing filter, and an output of the signal processing filter and the first reference clock in a state where the switching means guides the first reference clock to the signal processing filter. And a control unit for generating a first control signal for controlling a center frequency of the signal processing filter so that a phase difference component of the input signal becomes a predetermined value. Holding means for holding the first control signal output from the control means and supplying the first control signal to the signal processing filter in a state where the control signal is switched to be guided to the signal processing filter. Frequency adjustment circuit of the signal processing filter. 2. A phase locked loop means for generating the first reference clock from a second reference clock having a frequency different from that of the first reference clock by dividing ratio control, and a voltage of the phase locked loop means. Adding means for adding the second control signal supplied to the control oscillator and the first control signal output from the control means and leading the signal to the signal processing filter; and Phase shift means for shifting the phase of the first reference clock so as to have a predetermined phase difference with respect to the output of the signal processing filter and supplying the output to the control means. Claim 1
A frequency adjustment circuit of the filter for signal processing according to the above.