JPH04165717A - Phase locked loop circuit - Google Patents

Phase locked loop circuit

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Publication number
JPH04165717A
JPH04165717A JP2291633A JP29163390A JPH04165717A JP H04165717 A JPH04165717 A JP H04165717A JP 2291633 A JP2291633 A JP 2291633A JP 29163390 A JP29163390 A JP 29163390A JP H04165717 A JPH04165717 A JP H04165717A
Authority
JP
Japan
Prior art keywords
phase
loop
signal
filter
pass filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2291633A
Other languages
Japanese (ja)
Inventor
Makoto Nishikawa
誠 西川
Akio Inoue
明夫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP2291633A priority Critical patent/JPH04165717A/en
Publication of JPH04165717A publication Critical patent/JPH04165717A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce the time for phase synchronization establishment and to establish the synchronization of the phase locked loop by providing a loop changeover circuit selecting a loop circuit system having a low pass filter only with a control signal at phase asynchronization. CONSTITUTION:When a phase of a frequency division signal S2 of a frequency divider 2 and a phase of an output signal S3 of a reference signal generator 3 are not synchronized, an output signal S4 of a phase comparator passes through a low pass filter 5 only and when the phase synchronization establishment is detected by a switching control circuit 8 is detected, the signal passes through the low pass filter 5 and a loop filter 6 to control a voltage controlled oscillator 1. Thus, the low pass filter 5, the loop changeover device 9 and the switching control circuit 8 are provided to select the combination of the low pass filter 5 and the loop filter 6 with the loop changeover device 9 thereby preventing phase synchronization unestablishment due to leakage of a reference signal without delaying the establishment time of phase synchronization even when the phase comparison frequency is low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は位相同期ループ回路に関し、特に位相比較周波
数が低速度の場合でも位相同期確立時間の短縮をはかり
、かつ、基準周波数等のもれ込みによる位相同期不確立
を防止できる位相同期ループ回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop circuit, and particularly to a phase-locked loop circuit that aims to shorten the time to establish phase locking even when the phase comparison frequency is low speed, and to prevent leakage of reference frequencies, etc. The present invention relates to a phase-locked loop circuit that can prevent failure of phase synchronization due to interference.

〔従来の技術〕[Conventional technology]

従来の位相同期ループ回路は、第2図に示すように、電
圧制御発振器1の出力信号s1は分周器2により1/N
分周され分周信号s2となり位相比較器4に入力され、
基準信号発振器3の出力信号S3と分周信号S2とが位
相比較器4によって比較される。今、基準信号発振器3
の出力信号V、の振幅VIN角周波数ω2、初期位相θ
In the conventional phase-locked loop circuit, as shown in FIG. 2, the output signal s1 of the voltage controlled oscillator 1 is divided into 1/N
The frequency is divided and becomes a frequency-divided signal s2, which is input to the phase comparator 4.
The output signal S3 of the reference signal oscillator 3 and the frequency-divided signal S2 are compared by the phase comparator 4. Now, reference signal oscillator 3
output signal V, amplitude VIN angular frequency ω2, initial phase θ
.

(1)とするa、viは(1)式で表される。In (1), a and vi are expressed by equation (1).

Vi =V+ s in (ω1 を十θ+ (t) 
) ・H)vcotの出力信号S1をN分周した分周信
号v0の振幅VC+、角周波数ω。初期位相θ。(1)
とすると、VOは(2)式で表される。
Vi =V+ s in (ω1 to 1θ+ (t)
) H) Amplitude VC+ and angular frequency ω of a frequency-divided signal v0 obtained by dividing the output signal S1 of vcot by N. Initial phase θ. (1)
Then, VO is expressed by equation (2).

VO=Vo COs (ω。を十〇。(t) )−(2
)位相比較器4の出力信号Veは位相比較器の変換利得
をKdとすると、(3)式で表される。
VO=Vo COs (ω. 10.(t) )−(2
) The output signal Ve of the phase comparator 4 is expressed by equation (3), where Kd is the conversion gain of the phase comparator.

Ve =Kd (s i n (((IJ、 +ω。)
+θ1(t)十〇。(1))) +5in((ω1−ω。)+01(t)−〇。(1))
 )            ・・・(3)この出力は
ループフィルタ6により高域を除去されるので、ループ
フィルタ6の出力信号Vdは、今ω、=ω。とすると(
4)式で表される。
Ve = Kd (s i n (((IJ, +ω.)
+θ1(t) 10. (1))) +5in((ω1-ω.)+01(t)-〇.(1))
)...(3) Since the high frequency band of this output is removed by the loop filter 6, the output signal Vd of the loop filter 6 is now ω,=ω. If (
4) It is expressed by the formula.

Vd=KdF(S)s i n CO,(t)−θo(
t))・・・(4) この信号がさらに増幅器7により増幅された出力信号v
d′は増幅率Aとすると(5)式で表される。
Vd=KdF(S)s in CO,(t)−θo(
t))...(4) This signal is further amplified by the amplifier 7 to produce an output signal v
When d' is an amplification factor A, it is expressed by equation (5).

Vd’ =AKdF(S)s i n [:θ+D)−
〇、(1))・・・(5) すなわち出力信号vd′は電圧制御発振器1の制御信号
となる。(4)式の86信号(vd)はS3 (vt 
)と82 (v、)との位相差、すなわち、θ、(t)
−〇。(t)= Oとなるように電圧制御発振器の発振
周波数fを制御して位相同期ループを形成していた。
Vd' = AKdF(S) sin [:θ+D)-
〇, (1))...(5) That is, the output signal vd' becomes a control signal for the voltage controlled oscillator 1. The 86 signal (vd) in equation (4) is S3 (vt
) and 82 (v, ), that is, θ, (t)
−〇. A phase-locked loop was formed by controlling the oscillation frequency f of the voltage-controlled oscillator so that (t)=O.

C発明が解決しようとする課題〕 上述した従来の位相同期ループ回路は、電圧制御発振器
1の発振周波数の分周信号S2と基準信号発振器の出力
信号S3と比較して位相を同期させているので、位相比
較する周波数(分周信号)が低くなるにつれループフィ
ルタの帯域幅を狭くしなければならない。したがってル
ープフィルタ通過時の遅延により位相同期確立に時間が
かかる欠点がある。また、位相比較器の出力に基準信号
のもれがあった場合には、(1)式で示すViが出力さ
れるので、(5)式のve1′は(6)式のvd′のよ
うになる。
Problems to be Solved by the Invention C] The conventional phase-locked loop circuit described above synchronizes the phase by comparing the divided signal S2 of the oscillation frequency of the voltage controlled oscillator 1 with the output signal S3 of the reference signal oscillator. As the frequency (divided signal) for phase comparison becomes lower, the bandwidth of the loop filter must be narrowed. Therefore, there is a drawback that it takes time to establish phase synchronization due to the delay when passing through the loop filter. Also, if there is a leakage of the reference signal in the output of the phase comparator, Vi shown in equation (1) is output, so ve1' in equation (5) becomes vd' in equation (6). become.

Va ” =AKdF(S)s i n CO1(t)
−〇、(1)+V+ s in (ωt を十θI(t
)) )−(Gしたがってvt(U=θ。(1)となる
ように位相同期ループが働いても、vdがほぼA K 
d F (S)なる制御電圧とはならず、位相同期ルー
プの同期が確立できないという欠点があった。
Va ”=AKdF(S)s in CO1(t)
−〇, (1) +V+ s in (ωt to 1θI(t
)) ) - (G Therefore, even if the phase-locked loop works so that vt (U = θ. (1)), vd is almost A K
The control voltage does not become d F (S), and there is a drawback that synchronization of the phase-locked loop cannot be established.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の位相同期ループ回路は電圧制御発振器と、この
電圧制御発振器の出力信号を分周した分周信号と基準信
号との位相比較を行う位相比較器と、この位相比較器の
出力信号を所定帯域のループフィルタを通過させた後に
増幅して前記電圧制御発振器の制御電圧として帰還する
位相同期ループ回路において、前記位相比較器の出力信
号に存在する前記基準信号のもれを除去する低域通過ろ
波器と、前記位相比較器の出力信号を監視し位相同期又
は位相非同期を判定して制御信号を出力する切り替え制
御回路と、前記位相同期時の制御信号では前記低域通過
ろ波器と前記ループフィルタとを直列に接続したループ
回路系統とし、前記位相非同期時の制御信号では前記低
域通過ろ波器のみを有するループ回路系統に切り替るル
ープ切り替え回路とを有する。
The phase-locked loop circuit of the present invention includes a voltage-controlled oscillator, a phase comparator that performs a phase comparison between a frequency-divided signal obtained by dividing the output signal of the voltage-controlled oscillator, and a reference signal, and a phase-locked loop circuit that divides the output signal of the phase comparator into a predetermined value. In a phase-locked loop circuit that passes through a band loop filter and then amplifies it and returns it as a control voltage of the voltage controlled oscillator, a low-pass filter that removes leakage of the reference signal present in the output signal of the phase comparator. a filter, a switching control circuit that monitors the output signal of the phase comparator, determines phase synchronization or phase asynchrony, and outputs a control signal; A loop circuit system is provided in which the loop filter is connected in series, and a loop switching circuit is provided that switches to a loop circuit system having only the low-pass filter in response to a control signal when the phase is not synchronized.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。第1図
において第2図の従来例と同一の符号の回路は同一の構
成と機能を有する。すなわち、本実施例では低域通話ろ
波器5、切り替え制御回路8、ループの形態を変更する
ループ切り替え回路9を追加している。
FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, circuits with the same symbols as those in the conventional example of FIG. 2 have the same configuration and function. That is, in this embodiment, a low frequency filter 5, a switching control circuit 8, and a loop switching circuit 9 for changing the form of the loop are added.

次に本実施例の動作を説明する。分周器2の分周信号S
2と基準信号発生器3の出力信号S3との位相が同期し
ていない時に、ループ切り替え器9は端子2−3側にな
っており、位相比較器の出力信号S4は低域通過ろ波器
5のみを通過し、増幅器7により増幅されて電圧制御発
振器1を制御する。このとき低域通話ろ波器5はループ
フィルタ6に比べて帯域幅を5〜10倍広くしておくこ
とにより、位相同期確立時間を短縮することができる。
Next, the operation of this embodiment will be explained. Frequency division signal S of frequency divider 2
2 and the output signal S3 of the reference signal generator 3 are not synchronized in phase, the loop switch 9 is on the terminal 2-3 side, and the output signal S4 of the phase comparator is passed through the low-pass filter. 5 and is amplified by amplifier 7 to control voltage controlled oscillator 1. At this time, by making the bandwidth of the low-pass filter 5 5 to 10 times wider than that of the loop filter 6, the phase synchronization establishment time can be shortened.

切り替え制御回路8により位相同期確立を検出した時に
は、ループ切り替え器9を端子1−3側に切り替えて出
力信号S4は低域通過ろ波器5及びループフィルタ6を
通過し、増幅器7により増幅され電圧制御発振器1を制
御する。この場合に出力信号S4に基準周波数のもれが
含まれていても低域通過ろ波器5により基準周波数成分
を充分除去できるので、出力信号S7は直流成分のみと
なり、位相同期ループ系が安定に動作して同期確立がで
きる。
When the switching control circuit 8 detects the establishment of phase synchronization, the loop switch 9 is switched to the terminal 1-3 side, and the output signal S4 passes through the low-pass filter 5 and the loop filter 6, and is amplified by the amplifier 7. Controls the voltage controlled oscillator 1. In this case, even if the output signal S4 contains leakage of the reference frequency, the reference frequency component can be sufficiently removed by the low-pass filter 5, so the output signal S7 will have only a DC component, and the phase-locked loop system will be stabilized. can be operated to establish synchronization.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、低域通過ろ波器、ループ
切り替え器及び切り替え制御回路を備えて低域通過ろ波
器とループフィルタの組み合せをループ切り替え器によ
って切り替えることにより、位相比較周波数が低い場合
においても位相同期の確立時間を遅延させることなく、
かつ、基準信号のもれによる位相同期不確立を防止でき
る効果がある。
As explained above, the present invention includes a low-pass filter, a loop switch, and a switching control circuit, and by switching the combination of the low-pass filter and the loop filter using the loop switch, the phase comparison frequency can be adjusted. without delaying the establishment time of phase synchronization even at low
In addition, it is possible to prevent failure of phase synchronization due to reference signal leakage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は従来
の位相同期ループ回路のブロック図である。 1・・・電圧制御発振器、2・・・分周器、3・・・基
準信号発振器、4・・・位相比較器、5・・・低域通過
ろ波器、6・・・ループフィルタ、7・・・増幅器、8
・・・切り替え制御回路、9・・・ループ切り替え器。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional phase-locked loop circuit. DESCRIPTION OF SYMBOLS 1... Voltage controlled oscillator, 2... Frequency divider, 3... Reference signal oscillator, 4... Phase comparator, 5... Low pass filter, 6... Loop filter, 7... Amplifier, 8
...Switching control circuit, 9...Loop switching device.

Claims (1)

【特許請求の範囲】 1、電圧制御発振器と、この電圧制御発振器の出力信号
を分周した分周信号と基準信号との位相比較を行う位相
比較器と、この位相比較器の出力信号を所定帯域のルー
プフィルタを通過させた後に増幅して前記電圧制御発振
器の制御電圧として帰還する位相同期ループ回路におい
て、前記位相比較器の出力信号に存在する前記基準信号
のもれを除去する低域通過ろ波器と、前記位相比較器の
出力信号を監視し位相同期又は位相非同期を判定して制
御信号を出力する切り替え制御回路と、前記位相同期時
の制御信号では前記低域通過ろ波器と前記ループフィル
タとを直列に接続したループ回路系統とし、前記位相非
同期時の制御信号では前記低域通過ろ波器のみを有する
ループ回路系統に切り替るループ切り替え回路とを有す
ることを特徴とする位相同期ループ回路。 2、前記低域通過ろ波器の通過帯域が前記ループフィル
タの通過帯域の5倍から10倍の帯域を有することを特
徴とする請求項1記載の位相同期ループ回路。
[Claims] 1. A voltage controlled oscillator, a phase comparator that performs a phase comparison between a frequency-divided signal obtained by dividing the output signal of the voltage controlled oscillator and a reference signal, and a phase comparator that compares the phase of the divided signal obtained by dividing the output signal of the voltage controlled oscillator with a reference signal, and In a phase locked loop circuit that passes through a band loop filter and then amplifies and returns as a control voltage of the voltage controlled oscillator, a low pass that removes leakage of the reference signal present in the output signal of the phase comparator. a filter, a switching control circuit that monitors the output signal of the phase comparator, determines phase synchronization or phase asynchrony, and outputs a control signal; A loop circuit system in which the loop filter is connected in series, and a loop switching circuit that switches to a loop circuit system having only the low-pass filter in response to a control signal when the phase is not synchronized. Synchronous loop circuit. 2. The phase-locked loop circuit according to claim 1, wherein the passband of the low-pass filter has a passband that is 5 to 10 times larger than the passband of the loop filter.
JP2291633A 1990-10-29 1990-10-29 Phase locked loop circuit Pending JPH04165717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2291633A JPH04165717A (en) 1990-10-29 1990-10-29 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2291633A JPH04165717A (en) 1990-10-29 1990-10-29 Phase locked loop circuit

Publications (1)

Publication Number Publication Date
JPH04165717A true JPH04165717A (en) 1992-06-11

Family

ID=17771485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2291633A Pending JPH04165717A (en) 1990-10-29 1990-10-29 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPH04165717A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0278322A (en) * 1988-09-14 1990-03-19 Nec Corp Loop switching circuit for phase locked loop oscillator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0278322A (en) * 1988-09-14 1990-03-19 Nec Corp Loop switching circuit for phase locked loop oscillator

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