JPH0653828A - Frequency divider - Google Patents

Abstract

PURPOSE:To provide a frequency divider capable of highly accurately setting up frequency while holding high loop gain by the small number of frequency divider steps and accelerating a channel switching time for a synthesizer without increasing the size of a circuit. CONSTITUTION:A fractional frequency divider is constituted of a counter 10, a shift register 12 for inputting a counter output signal as a clear signal and inputting a counter input signal as a clock and an AND circuit 11 for inputting an output signal from the register 12 and the counter input signal. When both coefficients of a denominator and a numerator for the frequency divider concerned are simultaneously controlled, the channel switching time of the synthesizer can be accelerated without increasing the size of the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider used in a phase-locked loop (PLL) type frequency synthesizer which constitutes a high-frequency multi-channel radio or the like.

[0002]

2. Description of the Related Art A frequency synthesizer is an important constituent element of a multi-channel radio and is widely used in various radio equipments and devices. In order to shorten the channel switching time of the frequency synthesizer, it is effective to increase the loop gain, that is, decrease the frequency division number (increase the reference frequency).

A conventional frequency synthesizer will be described below. FIG. 3 shows the configuration of a conventional frequency synthesizer. In FIG. 3, 1 is a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, 2 is a high frequency output terminal, 3 is a first frequency divider for dividing the output of the voltage controlled oscillator 1, and 4 is a reference signal. A oscillating reference oscillator (usually a temperature-compensated crystal oscillator) 4a is a second frequency divider that divides the output of the reference oscillator 4. 5 is a third frequency divider having a frequency division number that divides the output of the second frequency divider 4;
It is formed by two frequency dividers 5a and 5b. 6 is a phase comparator (normally a digital phase / frequency comparator) that detects the output phases of the first and third frequency dividers 3 and 5, and 7 is the output of the phase comparator 6 that drives the integrator. A charge pump that serves as a signal, and 8 is an integrator (that is, a loop filter) that removes the high frequency component of the output of the charge pump 7 and feeds it back to the voltage controlled oscillator 1. These form the phase synchronization circuit 9.

The third frequency divider 5 having the conventional frequency division number will be described below. FIG. 4 shows an example of the fractional frequency divider 5a that constitutes the third conventional frequency divider 5.
In FIG. 4, 10 is a counter and 11 is an AND circuit. FIG. 5 shows the operation of the frequency divider, which is shown in FIG.
Is a waveform diagram of the output signal of the reference oscillator 4 input to the counter 10, FIG. 7B is a waveform diagram of the output of the counter 10, and FIG. 7C is a waveform diagram of the output of the AND circuit 11. As is clear from FIG. 5, the output of the reference oscillator 4 and the counter 10
By synthesizing the output of 1 by the AND circuit 11, the operation of removing the pulse for one cycle of the output of the reference oscillator 4 is performed.

[0005]

However, since the number of pulses to be removed by the conventional fractional frequency divider is 1, there is a problem in that the accuracy of the output frequency is poor when the number of stages of the fractional frequency divider is small. . As an example, the comparison frequency is 4.5 MH
The case of setting the z level will be described. Here, the third frequency divider has a two-stage configuration, and the output frequency of the reference oscillator is 10 MHz.
z, the frequency division number of the first frequency divider is 200, the frequency division number of the second frequency divider is 2, and the desired frequency is 915 MHz. The frequency division number (M1) of the frequency divider 5a is set to 14/13, and the frequency divider 5b
By setting the frequency division number (M2) of 68/67,
The output frequency (fref) of the frequency divider is 4.57458MHz
The external output is 914.9160MHz, M2 is 69
By setting / 68, fref becomes 4.557557 MHz, and the external output obtains 915.1139 MHz. The deviation generated between the set frequency and the external output frequency depends on the number of stages of the third frequency divider, and the accuracy can be improved by increasing the number of stages, but the circuit scale becomes large.

The present invention is intended to solve the above-mentioned problems of the prior art. A high-speed frequency pull-in for obtaining a highly accurate external output frequency without increasing the number of stages of the third frequency divider while keeping the loop gain high. It is an object of the present invention to provide a frequency divider that realizes a synthesizer.

[0007]

In order to achieve this object, the present invention, in a frequency divider having a frequency division number, removes any period of a signal input to the frequency divider, It has a configuration that controls both the denominator and numerator coefficients.

[0008]

According to the present invention, since the number of frequency divisions can be arbitrarily set by the above-mentioned configuration, it is possible to set the frequency with high precision while maintaining a high loop gain with a small number of frequency divider stages, and to increase the circuit scale. Therefore, it is possible to shorten the frequency switching time between channels of the synthesizer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block connection diagram of a fractional frequency divider according to an embodiment of the present invention. In FIG. 1, the numbers of the counter 10 and the AND circuit 11 are the same as those in FIG. 1 is different from the configuration in FIG. 4 in that a shift register 12 is newly provided.

The operation of the fractional frequency divider configured as above will be described. In this embodiment, it is assumed that the shift register output uses the QB terminal which rises at the second clock.

FIG. 2 is a waveform diagram of the essential parts of the operation of the fractional frequency divider of this embodiment. The output (TCXO) of the reference oscillator shown in FIG. 2A is input to the counter 10.
Next, as shown in FIG. 2B, the shift register 12 is cleared for each output (fr) of the counter 10. The output (fr0) of the shift register 12 rises by the second signal input to the clock terminal after clearing, as shown in FIG. 2 (c). Then, by synthesizing the output of the shift register 12 (fr0) and the output of the reference oscillator (TCXO) by the AND circuit 11, as shown in FIG. 2D, the pulse of the reference oscillator output for two cycles is removed. be able to.

Although the above embodiment has described the removal of pulses for two cycles, it is possible to remove one or more arbitrary number of pulses by selecting the output.

Next, the effect of improving the output frequency accuracy by the configuration of this embodiment will be described. The comparison is performed under the same conditions as described in the conventional example. For easier understanding of the operation, the third frequency divider 5 is composed of two fractional frequency dividers 5a and 5b, and the fractional frequency divider having the configuration of this embodiment is used only for 5b. .

M1 is 14/13, M2 is 137/135
As a result, fref becomes 4.57508 MHz, and the external output obtains 915.0156 MHz, but this value greatly improves the frequency accuracy compared to the conventional example. further,
In this example, the circuit configuration is applied only to the frequency divider of 5b, but the frequency accuracy can be further improved by applying the circuit configuration to the frequency divider of 5a as described above. According to the present embodiment, in a frequency divider having a frequency division number, any period of the signal input to the frequency divider is removed,
Since the frequency division number can be set arbitrarily by controlling both the denominator and numerator coefficients, it is possible to set the frequency with high accuracy while maintaining high loop gain with a small number of frequency divider stages.
It is possible to shorten the frequency switching time between channels of the synthesizer without increasing the circuit scale.

Needless to say, the number of stages of the third frequency divider 5 is arbitrary, and the circuit for controlling both coefficients of the denominator and the numerator is not limited to this embodiment.

[0017]

As described above, according to the present invention, in a frequency divider having a fractional frequency division number that constitutes a multi-channel frequency synthesizer, any period of a signal input to the frequency divider is removed. By controlling both the denominator and numerator coefficients, it is possible to set the frequency with high accuracy while maintaining a high loop gain with a small number of divider stages, and to increase the frequency between the channels of the synthesizer without increasing the circuit scale. It is possible to realize an excellent frequency divider capable of speeding up the switching time.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a frequency divider according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of the main part of the frequency divider.

FIG. 3 is a block connection diagram of a conventional frequency synthesizer.

FIG. 4 is a block connection diagram of a frequency divider, which is a main part of a frequency synthesizer.

FIG. 5 is a waveform diagram of main parts of the frequency divider.

[Explanation of symbols]

 1 Voltage Controlled Oscillator 2 High Frequency Output Terminal 3 1st Divider 4 Reference Oscillator 4a 2nd Divider 5 3rd Divider 6 Phase Comparator of 7 Charge Pump 8 Loop Filter 9 Phase Synchronous Circuit 10 Counter 11 AND circuit 12 shift register

Claims (2)

[Claims] 1. A frequency divider having a fractional frequency division number, removing an arbitrary period of an input signal, and controlling both coefficients of a denominator and a numerator. 2. A counter that inputs the output of a reference oscillator to count the number of pulses, a shift register that uses the count output signal of the counter as a clear signal and that uses the output of the reference oscillator as a clock, and the shift. 2. The frequency divider according to claim 1, wherein the frequency divider is configured by a logical product circuit that obtains a logical product of a count output signal of a register and an output of the reference oscillator.