JP2601096B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a frequency synthesizer used for a high-frequency multi-channel radio, etc.
More specifically, the present invention relates to a phase locked loop (PLL) type frequency synthesizer characterized by high-speed frequency pull-in.

[0002]

2. Description of the Related Art A frequency synthesizer is an important component of a multi-channel radio, and is widely used in various radio apparatuses and devices. In recent years, wireless communication has been shifting from analog to digital, but a time division multiple access (TDMA) method has been adopted as a communication method thereof, and a frequency synthesizer has a characteristic of pulling in a channel. High speed is an important issue.

[0003] A conventional frequency synthesizer will be described below. FIG. 4 shows a configuration of a conventional frequency synthesizer. In FIG. 4, 1 is a voltage controlled oscillator, 2
Is a high frequency output terminal, 3 is a variable frequency divider for dividing the output of the voltage controlled oscillator 1 (hereinafter simply referred to as a frequency divider) , 4 is a reference oscillator (usually a temperature compensated crystal oscillator is used), 5
Is a second frequency divider for dividing the output of the reference oscillator 4, 6 is a phase comparator for detecting the output phase of the first and second frequency dividers (usually a digital phase / frequency comparator), 7 Is a charge pump that converts the output of the phase comparator 6 and uses it as a drive signal for the integrator, 8 is an integrator that removes high-frequency components of the output of the charge pump 7 and feeds back to the voltage controlled oscillator 1, that is, a loop filter Reference numeral 9 denotes a first phase locked loop composed of the above elements.

The operation of the frequency synthesizer configured as described above will be described below.

At the time of phase synchronization, the output frequencies (comparison frequencies) and phases of the first and second frequency dividers match, and the output of the charge pump is in a high impedance state. On the other hand, when the channel is switched, the two output frequencies are deviated, but the phase comparator performs a frequency correction operation so as to pull in near the target frequency, and charges and discharges the loop filter via the charge pump (frequency pull-in mode). Further, the phase comparator performs a phase correction operation so as to pull in the target frequency, and charges and discharges the loop filter via the charge pump (phase pull-in mode).

[0006] The above series of operations is faster as the loop gain is higher, that is, the sensitivity of the voltage controlled oscillator is higher, the frequency division number is smaller (the comparison frequency is higher), or the time constant of the loop filter is smaller. Below, loop gain, voltage controlled oscillation
Sensitivity, frequency division number (comparison frequency), loop filter
To briefly explain the relationship between the constants, the loop gain (L
The natural angle ωn) is determined by the sensitivity Kφ of the phase comparator,
The sensitivity Kv of the pressure controlled oscillator, the frequency division number N,
The time constant T is represented by the following equation. ωn = {(Kφ · Kv) / (N · T)} ^1/2 As is clear from the above equation, increasing Kφ and Kv
However, the smaller N and T, the higher the loop gain.
Thus, high-speed acquisition of the frequency synthesizer can be realized.
The frequency division number N is the ratio of the output frequency f0 to the comparison frequency fREF.
(N = f0 / fref), and the lower the f0, the higher the fref
It gets smaller.

[0007]

However, in a multi-channel radio, the comparison frequency is uniquely determined by the channel interval and cannot be set freely. Also, if the sensitivity of the voltage controlled oscillator is increased, the S / N and C / N of the voltage controlled oscillator itself are deteriorated. If the time constant of the loop filter is reduced, the noise bandwidth is increased, and the S / N as a frequency synthesizer is reduced. There was a problem that C / N deteriorated.

The present invention solves the above-mentioned problems of the prior art, and provides a frequency synthesizer which realizes a high-speed channel pull-in characteristic while securing characteristics such as S / N and C / N in a steady state. The purpose is to do.

[0009]

In order to achieve the above object, the present invention provides a first voltage controlled oscillator, a first frequency divider for dividing the output of the first voltage controlled oscillator, and a reference oscillator. A second frequency divider for dividing an output, a first phase comparator for detecting output phases of the first and second frequency dividers, and an output of the integrator for converting an output of the first phase comparator. A first phase-locked loop comprising a first charge pump serving as a drive signal, and a first loop filter that removes a high-frequency component of the output of the first charge pump and feeds back the first voltage-controlled oscillator A second voltage controlled oscillator, a third frequency divider for dividing the output of the second voltage controlled oscillator, a fourth frequency divider for dividing the output of the reference oscillator, the third and fourth A second phase comparator for detecting the output phase of the frequency divider of the second embodiment, converting the output of the second phase comparator and multiplying Second charge pump to drive signals of vessels, and a second which is fed back to the high-frequency component is removed a second voltage controlled oscillator output of the second charge pump
A second phase-locked loop comprising a loop filter, a first voltage-controlled oscillator output, and a mixer for mixing the frequency of the second voltage-controlled oscillator output to obtain an intermediate frequency output, and removing unnecessary frequency components from the mixer output Filter, a fifth frequency divider for dividing the filter output, and the fourth and fifth frequency dividers.
A third phase comparator for detecting an output phase of the frequency divider, a third charge pump for converting an output of the third phase comparator to a drive signal for an integrator, and the first loop filter. A third phase-locked loop, and a switch for switching between the first and third phase-locked loops are provided before the first loop filter, and the sensitivity of the second voltage-controlled oscillator is increased by the first voltage-controlled oscillator. Higher than the sensitivity of
The oscillation frequency of the second voltage controlled oscillator is changed to the first voltage.
Is set near the oscillation frequency of the pressure-controlled oscillator.
You . Second, a first voltage controlled oscillator, a first frequency divider for dividing the output of the first voltage controlled oscillator, a second frequency divider for dividing the output of the reference oscillator, 1, a first phase comparator that detects an output phase of a second frequency divider, a first charge pump that converts an output of the first phase comparator and uses it as a drive signal for an integrator, A first phase-locked loop comprising a first loop filter for removing a high-frequency component of the output of the charge pump and feeding back to the first voltage-controlled oscillator, a second voltage-controlled oscillator, and the second voltage A third divider for dividing the output of the control oscillator, a fourth divider for dividing the output of the reference oscillator, and a second phase for detecting the output phase of the third and fourth dividers A comparator, a second charge pump that converts an output of the second phase comparator and generates a drive signal for an integrator, A second phase-locked loop including a second loop filter that removes a high-frequency component of the output of the second charge pump and feeds back to the second voltage-controlled oscillator; and an output of the first voltage-controlled oscillator. A mixer for mixing the output of the second voltage controlled oscillator to obtain an intermediate frequency output, a filter for removing unnecessary frequency components from the mixer output, a fifth frequency divider for dividing the filter output, the fourth and fifth A third phase comparator for detecting an output phase of the frequency divider, a third charge pump for converting an output of the third phase comparator to a drive signal for an integrator, and the first loop filter. A third phase locked loop circuit and a switch for switching between the first and third phase locked loop circuits are provided before the first loop filter, and the time constant of the second loop filter is set to Time constant Remote with reduced, the oscillation frequency of the second voltage controlled oscillator
Is set near the oscillation frequency of the first voltage controlled oscillator.
It was done.

[0010]

According to the present invention, the second phase-locked circuit is started before the channel is switched, and the frequency is switched at high speed by the third phase-locked circuit including the mixer when the channel is switched. By switching the circuit and performing a phase matching operation, it is possible to reduce the inter-channel frequency switching time without deteriorating characteristics such as S / N and C / N in a steady state.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a frequency synthesizer according to a first embodiment of the present invention. In FIG. 1, 1 to 9
The components denoted by reference numerals are the same as those in FIG. 1 differs from the configuration of FIG. 4 in that the second voltage-controlled oscillator 10 and a third variable frequency divider 11 that divides the output of the second voltage-controlled oscillator (hereinafter simply referred to as a third frequency-divided oscillator)
A fourth frequency divider 12 for dividing the output of the reference oscillator 4, a second phase comparator 13 for detecting the output phases of the third and fourth frequency dividers, and a second Second charge pump 1 that converts the output of the phase comparator and uses it as a drive signal for the integrator
4. a second phase-locked loop 16 composed of a second integrator, ie, a loop filter 15, which removes high-frequency components of the output of the second charge pump and feeds back to the second voltage-controlled oscillator 10; 17a that obtains an intermediate frequency output by frequency mixing the output of the voltage controlled oscillator 1 and the output of the second voltage controlled oscillator 10, the filter 17b that removes unnecessary frequency components from the output of the mixer 17a, and the output of the filter 17b are divided. A fifth frequency divider 18, a third phase comparator 19 for detecting output phases of the fourth and fifth frequency dividers, and an output of the third phase comparator 19 are converted into a driving signal of an integrator and A third phase-locked loop 21 composed of a third charge pump 20 and a first integrator, ie, a loop filter 8, and a switch for switching between the first phase-locked loop 9 and the third phase-locked loop 21 2 is that the provided.

Further, assuming that the oscillation frequency of the first voltage controlled oscillator 1 is f1, the oscillation frequency f2 of the second voltage controlled oscillator 10 is near f1, and fm = | f1-f2 |
Is set so that the frequency becomes constant. This
As described above, the oscillation frequency f1 of the first voltage-controlled
The difference fm between the oscillation frequencies f2 of the two voltage-controlled oscillators 10 is one.
The first and second phase synchronization circuits 9 and 16
The wavenumber change steps must be the same, resulting in a ratio
The comparison frequency is uniquely determined.

The operation of the frequency synthesizer configured as described above will be described. The operating conditions in the embodiment of the present invention are as follows: (A) The sensitivity of the second voltage controlled oscillator 10 is made higher than the sensitivity of the first voltage controlled oscillator 1. (B) The time constant of the second loop filter 15 is made smaller than the time constant of the first loop filter 8. (C) changing the oscillation frequency of the second voltage controlled oscillator to the first voltage
Set near the oscillation frequency of the control oscillator. In the condition (1), it can be implemented by a combination of the condition (A) and the condition (C) or a combination of the condition (B) and the condition (C). Before the channel switching, the second phase synchronization circuit 16
Start up. The second phase-locked loop 16 is used for a third phase-locked loop 21 used for a transient response after frequency switching.
Since it is a local oscillation source of the mixer 17a included in the above, the frequency stability is required, but high-performance S / N and C / N are not required. Therefore, the comparison frequency needs to be set to the same value as that of the first phase-locked loop 9, but the sensitivity of the second voltage-controlled oscillator 10 is increased (the above condition (A)) or the second
It is possible to increase the loop gain by setting the time constant of the loop filter 15 to be small (the above condition (B)), and realize high-speed frequency pull-in. At the time of channel switching, only a frequency component of fm is extracted by connecting a filter 17b to an output of a mixer 17a that receives an output of the first voltage controlled oscillator 1 and an output of the second voltage controlled oscillator 10, and outputs this output. Third phase synchronization circuit 21 used
To switch the frequency. In order not to impair the characteristics of the first phase locked loop circuit 9 in a steady state, the degree of freedom in setting the sensitivity of the first voltage controlled oscillator 1 and the time constant of the first loop filter 8 is small. On the other hand, the comparison frequency is also uniquely determined by the first phase locked loop 9, but fm is equal to the first frequency.
Is much smaller than the frequency of the voltage-controlled oscillator 1 of FIG. As a result, the loop gain of the third phase locked loop 21 automatically becomes higher than the loop gain of the first phase locked loop 9, and extremely high-speed frequency switching can be realized. After that, the switching to the first phase synchronization circuit 9 is performed via the switch 22 by the phase synchronization circuit switching signal. As described above, according to the configuration of FIG. 1, the oscillation
First and second voltage controlled oscillators 1 and 10 having similar frequencies
, The first and second phase locked loops 9, 1
Set the frequency so that the output frequency difference of 6 becomes constant.
Next, at the time of channel switching, the second phase synchronization circuit
Is locked to the set frequency, and the above condition (A) or
According to the condition (B), the second phase locked loop 16 operates at a high frequency.
Pull in numbers. Next, the first phase-locked loop 9 and the second phase
Third phase synchronization with respect to the frequency difference fm of the phase synchronization circuit 16
The circuit performs phase synchronization, and fm is the first phase synchronization circuit.
Significantly lower than the output frequency of the road. For this reason, the loop gain can be made extremely higher than in the conventional example, and an ultra-high-speed pull-in can be realized.

[0015] In addition, the first phase synchronization circuit at the time of switching 9
And the third phase locked loop 21 have the same frequency, but a phase error occurs and a transient response for phase correction occurs, so that the frequency switching time becomes longer. In order to solve this problem, a means for phase matching is required at the time of switching.

FIG. 2 is a configuration diagram of a phase matching circuit which is a main part of FIG. 2 are the same as those in FIG. 1 and the description is omitted. 29 is a loop switch for switching between the first charge pump 7 and the first loop filter 8, 30 is a first switch disposed between the first voltage controlled oscillator 1 and the first frequency divider 3. A gate circuit, 31 is a second gate circuit placed between the reference oscillator 4 and the second frequency divider 5, and 32 is a phase locked loop switching signal and the first frequency divider 3 or the second frequency divider 5 and the output of the phase comparator 6 as inputs, the loop switch 2
9 and a control circuit for controlling the gate circuits 30 and 31.

The operation of the phase matching circuit configured as described above will be described. When switching from the third phase locked loop 21 to the first phase locked loop 9, the control circuit 32 which receives the output of the phase comparator 6 and the phase locked loop switching signal as inputs receives the first frequency divider 3. And the gate circuits 30 and 31 for controlling the inputs of the second frequency divider 5 are controlled for the time corresponding to the phase error, and the two inputs of the phase comparator 6 are brought into the in-phase state. In addition, the control circuit 32 generates a loop control signal that changes with a certain time delay from the rise of the phase synchronization circuit switching signal. The loop switch 29 is directly controlled by the loop control signal. By these operations, the phase is adjusted at the beginning of the loop switching control, a short pull-in time is required, and then the normal frequency synthesizer mode is set. As described above, the phase matching shown in FIG.
The circuit is provided from the third phase locked loop 21 to the first phase locked loop.
When switching to road 9, the frequency is almost the same but the phase
Error causes transient response for phase correction
Between the first voltage controlled oscillator 1 and the first frequency divider 3,
Gate circuit 3 between reference oscillator 4 and second frequency divider 5
0 and 31 are provided, and the phase is advanced by a time corresponding to the phase difference.
To match the phase by blocking the input on the side
Therefore, high-speed frequency switching is possible.

FIG. 3 is a detailed block diagram of the control circuit in FIG. In FIG. 3, reference numeral 40 denotes a 3-bit shift register which uses the output of the first frequency divider 3 or the second frequency divider 5 as a clock input and a phase synchronization circuit switching signal as a reset input, and 41 and 42 denote shift registers 40. Output and the first
Is a gate circuit that receives the output of the phase comparator 6 as an input.

The operation of the control circuit 32 configured as described above will be described. The 3-bit shift register 40 generates a loop control signal that is delayed by three cycles of the phase comparison frequency from the rise of the phase synchronization circuit switching signal. The loop switch 29 is directly controlled by the loop control signal. Further, the control signals of the gate circuits 30 and 31 are controlled so that the loop control signal and the output of the phase comparator 6 are gated by the gate circuits 41 and 42 and the phase is adjusted for three periods of the rising edge of the phase synchronization circuit switching signal. create. With these operations, the phase is adjusted at the beginning of the switching of the phase-locked loop, and a short pull-in time is required, and then the normal synthesizer mode is set.

As described above, according to the present embodiment, in the multi-channel frequency synthesizer, the first and second phase synchronization circuits and the third phase synchronization circuit including the mixer are provided.
In addition, by setting the loop gain of the second phase locked loop higher than that of the first phase locked loop and providing a phase matching circuit in the first phase locked loop, the inter-channel frequency switching time can be shortened. it can.

Hereinafter, a second embodiment of the present invention will be described. Since the basic configuration is the same as that of the first embodiment, the description is omitted. The difference from the first embodiment is that when the oscillation frequency f2 of the second voltage controlled oscillator 10 is fixed, that is, when the oscillation frequency of the first voltage controlled oscillator 1 is f1, fm = |
f1−f2 | changes with f1.

The operation of the frequency synthesizer configured as described above will be described. Since fm changes with the switching of the frequency f1 of the first voltage controlled oscillator 1, the frequency division number of the fifth frequency divider 18 is also switched at the same time as the switching of f1,
Control is performed such that the output frequency of the fifth frequency divider 18 always corresponds to the comparison frequency. The other basic operations are the same as those of the first embodiment, and the description is omitted.

As described above, according to the present embodiment, in the multi-channel frequency synthesizer, the first and second phase synchronization circuits and the third phase synchronization circuit including the mixer are provided.
In addition, by setting the loop gain of the second phase locked loop higher than that of the first phase locked loop and providing a phase matching circuit in the first phase locked loop, the inter-channel frequency switching time can be shortened. it can.

In the present embodiment, the second phase-locked loop 16 is started up before the channel is switched, but it may be always running. Also, the first, second,
In order to match the phases of the comparison frequencies of the third phase locked loop, it is necessary to use the same reference oscillator.

Further, the phase matching circuit is not limited to the embodiment, and it is needless to say that the first and second frequency dividers have a function of performing phase matching at the time of switching.

[0026]

As described above, according to the present invention, in a multi-channel frequency synthesizer, a third phase synchronization circuit including first and second phase synchronization circuits and a mixer is provided.
In addition, by setting the loop gain of the second phase-locked loop higher than that of the first phase-locked loop and providing the first phase-locked loop with a phase matching circuit, the channel in the steady state can be maintained without impairing the characteristics. An excellent frequency synthesizer capable of shortening the inter-frequency switching time can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a phase matching circuit which is a main part of the frequency synthesizer.

FIG. 3 is a block diagram of a control circuit which is a main part of FIG. 2;

FIG. 4 is a block diagram of a conventional frequency synthesizer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage controlled oscillator 2 high frequency output terminal 3 frequency divider 4 reference oscillator 5 frequency divider 6 phase comparator 7 charge pump 8 loop filter 9 phase locked loop 10 voltage controlled oscillator 11 frequency divider 12 frequency divider 13 phase comparator 14 Charge pump 15 Loop filter 16 Phase synchronization circuit 17a Mixer 17b Filter 18 Divider 19 Phase comparator 20 Charge pump 21 Phase synchronization circuit 22 Switch 29 Loop switch 30 Gate circuit 31 Gate circuit 32 Control circuit 40 Shift register 41 Gate circuit 42 Gate circuit

Claims (9)

(57) [Claims] 1. A first voltage controlled oscillator, a first frequency divider for dividing the output of the first voltage controlled oscillator, a second frequency divider for dividing the output of a reference oscillator, and the first A first phase comparator for detecting an output phase of the second frequency divider, and a first phase comparator for converting an output of the first phase comparator to a drive signal for an integrator.
A first phase-locked loop comprising a charge pump, a first loop filter for removing a high-frequency component of the output of the first charge pump and feeding back the first voltage-controlled oscillator, and a second voltage. A controlled oscillator, a third divider for dividing the output of the second voltage controlled oscillator, a fourth divider for dividing the output of the reference oscillator, and outputs of the third and fourth dividers A second phase comparator for detecting a phase, a second charge pump for converting an output of the second phase comparator to a drive signal for an integrator, and a high-frequency component of an output of the second charge pump. A second phase-locked loop comprising a second loop filter for removing and feeding back to the second voltage-controlled oscillator; A mixer for obtaining a frequency output; A filter for removing a frequency component, a fifth frequency divider for dividing the output of the filter, a third phase comparator for detecting output phases of the fourth and fifth frequency dividers, and a third phase comparison A third charge pump that converts the output of the integrator into a drive signal for the integrator, a third phase-locked loop including the first loop filter, and a switch that switches between the first and third phase-locked loops The second voltage controlled oscillator is provided before the first loop filter so that the sensitivity of the second voltage controlled oscillator is higher than the sensitivity of the first voltage controlled oscillator, and the oscillation frequency of the second voltage controlled oscillator is set to the first frequency.
A frequency synthesizer set near the oscillation frequency of the voltage-controlled oscillator . 2. A first voltage controlled oscillator, a first frequency divider for dividing the output of the first voltage controlled oscillator, a second frequency divider for dividing the output of a reference oscillator, and the first frequency controlled oscillator. A first phase comparator for detecting an output phase of the second frequency divider, and a first phase comparator for converting an output of the first phase comparator to a drive signal for an integrator.
A first phase-locked loop comprising a charge pump, a first loop filter for removing a high-frequency component of the output of the first charge pump and feeding back the first voltage-controlled oscillator, and a second voltage. A controlled oscillator, a third divider for dividing the output of the second voltage controlled oscillator, a fourth divider for dividing the output of the reference oscillator, and outputs of the third and fourth dividers A second phase comparator for detecting a phase, a second charge pump for converting an output of the second phase comparator to a drive signal for an integrator, and a high-frequency component of an output of the second charge pump. A second phase-locked loop comprising a second loop filter for removing and feeding back to the second voltage-controlled oscillator; A mixer for obtaining a frequency output; A filter for removing a frequency component, a fifth frequency divider for dividing the output of the filter, a third phase comparator for detecting output phases of the fourth and fifth frequency dividers, and a third phase comparison A third charge pump that converts the output of the integrator into a drive signal for the integrator, a third phase-locked loop including the first loop filter, and a switch that switches between the first and third phase-locked loops Provided before the first loop filter, the time constant of the second loop filter is made smaller than the time constant of the first loop filter, and the oscillation frequency of the second voltage-controlled oscillator is reduced.
A frequency synthesizer set near the oscillation frequency of the first voltage controlled oscillator . 3. A phase matching circuit for matching output phases of a first frequency divider and a second frequency divider immediately after switching from a third phase locked loop circuit to a first phase locked loop circuit. 3. The frequency synthesizer according to claim 1, wherein the frequency synthesizer is provided in a phase locked loop. 4. A first gate circuit provided between a first voltage controlled oscillator and a first frequency divider, and a second gate circuit provided between a reference oscillator and a second frequency divider. And the first char
A loop switch provided between the dipump and the first loop filter; a 3-bit or more bit shift register for receiving the output of the first or second frequency divider and a phase synchronization circuit switching signal; 4. The frequency synthesizer according to claim 3, further comprising a phase matching circuit including a control circuit including third and fourth gate circuits that receive an output of a comparator and an output of the shift register as inputs. 5. The frequency of the second voltage controlled oscillator is set such that the difference between the frequency of the first voltage controlled oscillator and the frequency of the second voltage controlled oscillator is constant. The frequency synthesizer according to claim 2. 6. The frequency synthesizer according to claim 1, wherein the frequency of the second voltage controlled oscillator is fixed. 7. The frequency synthesizer according to claim 1, wherein a loop gain of the second phase locked loop is set higher than that of the first phase locked loop. 8. The frequency synthesizer according to claim 1, wherein a reference oscillator used for the first, second and third phase locked loops is shared. 9. The frequency synthesizer according to claim 1, wherein the power of the second phase locked loop circuit is cut off when the frequency switching is completed, and is restarted immediately before the next frequency switching.