JP3473413B2 - Phase locked loop - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit using a coarse tuning circuit, and more particularly to a phase locked loop circuit capable of high speed coarse tuning.

[0002]

2. Description of the Related Art A conventional phase locked loop circuit using a coarse tuning circuit uses a coarse tuning circuit when phase synchronization is out of phase, and lowers the oscillation frequency when the oscillation frequency of a voltage controlled oscillator is higher than an upper limit frequency. Such a control signal is supplied to the voltage controlled oscillator. On the other hand, when the oscillation frequency of the voltage controlled oscillator is lower than the lower limit frequency, a control signal for raising the oscillation frequency is supplied to the voltage controlled oscillator. As a result, the oscillation frequency of the voltage controlled oscillator can be controlled to a synchronizable range, so that phase synchronization can be achieved in a short time.

FIG. 3 is a block diagram showing an example of such a conventional phase locked loop circuit, which is described in "Japanese Patent Application No. 3-43642" filed by the applicant of the present application.
In FIG. 3, 1 is a phase comparator, 2 is an adder, 3 is a loop filter, 4 is a voltage controlled oscillator, 5 is a frequency converter, and 6
Is a coarse tuning circuit, 100 is a reference signal input, 101 is an output signal, 102 is a frequency signal, and 103 is a control signal which is the output of the coarse tuning circuit 6.

The reference signal input 100 is connected to one input terminal of the phase comparator 1, and the output of the phase comparator 1 is the adder 2
Connected to one of the input terminals. The output of the adder 2 is connected to the voltage controlled oscillator 4 via the loop filter 3.
The voltage controlled oscillator 4 outputs the output signal 101, and the output signal 101 is connected to the frequency converter 5 and the coarse tuning circuit 6.

The frequency signal 102 which is the output of the frequency converter 5 is connected to the other input terminal of the phase comparator 1, and the control signal 103 which is the output of the coarse tuning circuit 6 is the other input terminal of the adder 2. Connected to.

Now, the operation of the conventional example shown in FIG. 3 will be briefly described. The output signal 101 of the voltage controlled oscillator 4 is frequency-converted by the frequency converter 5 and compared with the reference signal input 100 by the phase comparator 1. The output of the phase comparator 1 is the adder 2
Is added to the control signal 103 of the coarse tuning circuit 6 and becomes the control input of the voltage controlled oscillator 4 via the loop filter 3.

The coarse tuning circuit 6 adjusts the frequency of the output signal 101 of the voltage controlled oscillator 4 to a synchronizable frequency range (capture range). As a result, the frequency of the output signal 101 of the voltage controlled oscillator 4 is controlled to a predetermined frequency determined by the frequency division ratio of the frequency converter 5 with respect to the frequency of the reference signal input 100.

In the phase locked loop circuit shown in FIG. 3, when phase locking is performed, the frequency signal 102, which is the output of the frequency converter 5, becomes equal to the frequency of the reference signal input 100. In this case, the control signal 103 of the coarse tuning circuit 6 becomes “0”, and the output of the phase comparator 1 is directly input to the voltage controlled oscillator 4 via the loop filter 3.

On the other hand, when the oscillation frequency of the voltage controlled oscillator 4 is higher than the upper limit frequency in the state where the phase synchronization is lost, the control signal 103 for lowering the oscillation frequency is provided.
To the voltage controlled oscillator 4, while the voltage controlled oscillator 4
If the oscillation frequency is lower than the lower limit frequency, the control signal 103 for raising the oscillation frequency is supplied to the voltage controlled oscillator 4.

The details of the coarse tuning circuit 6 will be described. FIG. 4 is a block diagram showing an example of the coarse tuning circuit described in Japanese Patent Application No. 3-43642. 4, 101 and 103 are denoted by the same reference numerals as those in FIG.
7 is a counter, 8 is a register, 9 and 10 are data selectors, 11 is a gate generation circuit, 12, 18, 19, 2
0, 21, 22, and 23 are switch circuits, 13 and 14
Is a digital comparator, 15 and 16 are AND circuits, and 17 is a switching circuit.

The output signal 101 is connected to the clock terminal of the counter 7, the output of the counter 7 is connected to the register 8, and the output of the register 8 is connected to one input terminal "A" of the digital comparators 13 and 14, respectively. .

The output of the data selector 9 is connected to the other input terminal "B" of the digital comparator 13, and the output of the data selector 10 is connected to the other input terminal "B" of the digital comparator 14.

"A <B" of the digital comparator 13
Is connected to one input terminal of the AND circuit 15 and the input terminal of the switching circuit 17, and the digital comparator 1
The output of “A ≧ B” of 3 is connected to one input terminal of the AND circuit 16 and the input terminal of the switching circuit 17.

Further, the digital comparator 14 "A"
The output of> B ”is connected to the other input terminal of the AND circuit 16 and the input terminal of the switching circuit 17, and the output of“ A ≦ B ”of the digital comparator 14 is the other input terminal of the AND circuit 15 and the switching circuit 17. Connected to the input terminal.

The outputs of the AND circuits 15 and 16 are connected to the input terminals of the switch circuits 18 and 19, one output of the switch circuit 18 is connected to the control terminal of the switch circuit 20, and the other output of the switch circuit 18 is a switch. Circuit 2
2 control terminals. Also, one output of the switch circuit 19 is connected to the control terminal of the switch circuit 21,
The other output of the switch circuit 19 is connected to the control terminal of the switch circuit 23.

One end of the switch circuit 20 is connected to the first positive voltage source, and one end of the switch circuit 21 is connected to the first negative voltage source. Further, one end of the switch circuit 22 is connected to the second positive voltage source, and one end of the switch circuit 23 is connected to the second negative voltage source.
The other ends of 1, 22, and 23 output the control signal 103.

The first and second gate signals of the gate generation circuit 11 are connected to the two input terminals of the switch circuit 12, respectively, and the output of the switch circuit 12 is connected to the clear terminal of the counter 7 and the clock terminal of the register 8, respectively. To be done. The output of the switching circuit 17 is the select terminals of the data selectors 9 and 10 and the switch circuits 12, 18 and 19.
Are respectively connected to the control terminals of.

The operation of the coarse tuning circuit shown in FIG. 4 will now be described with reference to FIGS. 5 and 6. FIG. 5 is an explanatory diagram showing the relationship between the capture range and the control signal 103, and FIG. 6 is a timing diagram illustrating the operation of the coarse tuning circuit.

The voltage controlled oscillator 4 is set by a new frequency setting.
When the oscillation frequency "fvco" of the output signal 101 is changed, the switching circuit 17 switches the coarse tuning circuit 6 to the fast coarse tuning mode.

At this time, the faster gate signal "T1" of the two gate signals of the gate generation circuit 11 is selected by the switch circuit 12 and supplied to the counter 7 etc., and the frequency data "D1" and ”
D3 "is selected. Also, the switch circuits 18 and 19 are selected.
Thus, the output terminal on the "a" side in FIG. 4 is selected.

Assuming that the capture range is "fc", the target frequency is "ft", and the window width ratio shown in "W1" and "W2" in FIG. 5 is "N", the lower limit data "D" is set.
1 ”and the upper limit data“ D3 ”are D1 = (ft−N · fc) · T1 (1) D3 = (ft + N · fc) · T1 (2).

Further, the count value "Qvc" in the counter 7
Since o ″ is Qvco = fvco · T1 (3), when fvco <ft−N · fc (4), the digital comparators 13 and 14 have “
A <B ”and“ A ≦ B ”are“ 1 ”, and“ A ≧ B ”and“ A> ”
B ”and“ 0 ”, the switch circuit 20 is“ ON ”, and the control signal 103 is the voltage value of the first positive voltage source“
+ V1 "is output.

Therefore, as shown in FIG. 5, since the voltage added with "+ V1" is supplied to the voltage controlled oscillator 4, the frequency "fvco" of the output signal 101 rises.

Similarly, when fvco> ft + Nfc (5), the digital comparators 13 and 14 "A"
≧ B ”and“ A> B ”are“ 1 ”,“ A <B ”and“ A ≦ B ”
Become "0", the switch circuit 21 becomes "ON", and the control signal 103 has the voltage value "-" of the first negative voltage source.
V1 "is output.

Therefore, as shown in FIG. 5 and FIG. 6, the voltage "f1" is added to the voltage controlled oscillator 4, and the frequency "fvco" of the output signal 101 is lowered.

When ft-Nfc≤fvco≤ft + Nfc (6), the switching circuit 17 switches the coarse tuning operation to the high resolution coarse tuning mode. That is, the gate generation circuit 11
"T2", which is longer than "T1", is selected by the switch circuit 12 and supplied to the counter 7 and the like, and the frequency data "in the data selectors 9 and 10".
D2 "and" D4 "are selected. Further, the switch circuits 18 and 19 select the output terminal on the" b "side in FIG.

Here, the lower limit data "D2" and the upper limit data "D4" are D2 = (ft-fc) .multidot.T1 (7) D4 = (ft + fc) .multidot.T1 (8).

Further, the count value "Qvc" in the counter 7
Since o ″ is Qvco = fvco · T2 (9), when fvco <ft−fc (10), the digital comparators 13 and 14 have “
A <B ”and“ A ≦ B ”are“ 1 ”, and“ A ≧ B ”and“ A> ”
B ”becomes“ 0 ”, the switch circuit 22 becomes“ ON ”, and the voltage value of the second positive voltage source becomes“ the control signal 103 ”.
+ V2 "is output.

For this reason, as shown in FIG. 5, the voltage "+ V2" is added to the voltage controlled oscillator 4, and the frequency "fvco" of the output signal 101 rises.

Similarly, when fvco> ft + fc (11), "A" of the digital comparators 13 and 14 is obtained.
≧ B ”and“ A> B ”are“ 1 ”,“ A <B ”and“ A ≦ B ”
Become "0", the switch circuit 23 becomes "ON", and the voltage value of the second negative voltage source becomes "-" as the control signal 103.
V2 ″ is output.

For this reason, as shown in FIGS. 5 and 6, the voltage-controlled oscillator 4 is supplied with the voltage to which "-V2" is added, so that the frequency "fvco" of the output signal 101 is lowered.

And finally, ft-fc ≦ fvco ≦ ft + fc (12) Then, the coarse tuning circuit 6 finishes its operation.

As a result, the coarse tuning operation is performed in two stages, the coarse tuning is performed in a short counting time when the oscillation frequency of the voltage controlled oscillator 4 is far from the capture range, and the long counting time is performed when the oscillation frequency approaches the capture range. It is possible to shorten the coarse tuning time by performing coarse tuning with high resolution.

[0034]

However, in the conventional coarse tuning circuit shown in FIG. 4, the output signal 101 of the voltage controlled oscillator 4 is used.
When the oscillation frequency "fvco" of the above is greatly different from the target frequency "ft", "ft-Nfc≤fvco≤ft + N" with the gate signal "T1" as described above.
Since coarse tuning is performed until fc "is reached, there is a problem that the coarse tuning time becomes longer than when the oscillation frequency" fvco "is close to the target frequency" ft ".

Further, the window width at the time of coarse tuning with high resolution corresponding to "W2" in FIG. 5 must be set within the capture range, and the above-mentioned window width ratio "N" is also for stable operation. Therefore, when the capture range is very narrow, the window width during fast coarse tuning corresponding to "W1" in FIG. 5 is also narrowed.

As described above, when the oscillation frequency "fvco" of the voltage controlled oscillator 4 is largely changed at high speed when the window width is narrow, the oscillation frequency "fvco" is close to the target frequency "ft" due to the delay of the coarse tuning operation. There is a problem that the oscillation frequency "fvco" needs to be changed slowly because it may vibrate, so that the coarse tuning time becomes long. Therefore, the problem to be solved by the present invention is to realize a phase locked loop circuit capable of high-speed coarse tuning.

[0037]

In order to achieve the above object, the invention according to claim 1 of the present invention provides a phase for controlling an oscillation frequency of a voltage controlled oscillator to a synchronizable range by a coarse tuning circuit. In the synchronizing circuit, the coarse tuning circuit counts the oscillation frequency of the voltage controlled oscillator, a gate generation circuit that gives two or more kinds of counting times to the counter, and upper and lower limits that correspond to the counting times. A digital comparator for comparing the frequency data with the count value of the counter, an output circuit for generating a first control signal of different magnitude corresponding to each count time based on the output of the digital comparator, and the first comparator. A filter circuit for smoothing a control signal, and a D / A for adding an output to the output of this filter circuit to generate a second control signal.
A converter and a switching circuit for switching the counting time of the gate generation circuit and the control signal of the output circuit corresponding to the output of the digital comparator, and the first coarse tuning is performed by the output of the D / A converter, By performing the second coarse tuning with a short counting time and the high resolution third coarse tuning with a long counting time, the capture range is narrow and the oscillation frequency "f"
The coarse tuning time can be shortened even when vco "is far from the target frequency" ft ".

According to a second aspect of the present invention, in the phase-locked circuit in which the coarse tuning circuit controls the oscillation frequency of the voltage controlled oscillator to a synchronizable range, the coarse tuning circuit counts the oscillation frequency of the voltage controlled oscillator. A counter, a gate generation circuit that gives a long counting time to the counter, a digital comparator that compares the upper and lower limit frequency data with the count value of the counter, and an output circuit that generates a first control signal based on the output of the digital comparator. When,
A filter circuit for smoothing the first control signal, a D / A converter for adding an output to the output of the filter circuit to generate a second control signal, and the output circuit corresponding to the digital comparator output. And a switching circuit for switching the control signal, and the first coarse tuning is performed by the output of the D / A converter, and the second coarse tuning with high resolution is performed with a long counting time, thereby narrowing the capture range and oscillating. frequency"
Even when fvco "is far from the target frequency" ft ", the coarse tuning time can be shortened.

According to a third aspect of the invention, in the phase locked loop circuit according to the first and second aspects of the invention, the phase locked loop is disconnected during the adjustment inspection so that the output of the D / A converter is directly controlled by the voltage control. By supplying to the oscillator, it becomes possible to easily perform the adjustment inspection of the oscillation frequency.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a coarse tuning circuit portion of a phase locked loop according to the present invention. In FIG. 1, 7 to 23, 101 and 103 are denoted by the same reference numerals as in FIG. 4, 24 is a filter circuit, 25, 26 and 27.
Is a switch circuit, 28 is an amplifier, 29 is a D / A converter,
104 is a control signal. Further, 7 to 23 are conventional coarse tuning circuits 50, and 25 to 27 are switch means 51, 15,
Reference numerals 16, 18 to 23 constitute the output circuit 52, respectively.

The connection relationship of the coarse tuning circuit 50 is shown in FIG.
Since it is the same as the conventional example shown in FIG. The control signal 103 output from the coarse tuning circuit 50 is the filter circuit 2
4 to the output terminal of the switch circuit 25 and the input terminal of the switch circuit 26, respectively.
The output of 6 is connected to the output terminal of the switch circuit 27 and a voltage controlled oscillator (not shown). The output of the D / A converter 29 is connected to the input terminals of the switch circuits 25 and 27 via the amplifier 28. Further, the lock detection signal of the switching circuit 17 is connected to the control terminal of the switch circuit 25.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the coarse tuning circuit shown in FIG. However, the conventional coarse tuning circuit 50
The description of the operation of is omitted.

In the normal state, the switch circuits 26 and 27
Are "ON" and "OFF", and when the oscillation frequency "fvco" of the voltage controlled oscillator 4 is far from the target frequency "ft", the switch circuit 25 is turned "ON". At this time, the output from the D / A converter 29 is the amplifier 28.
Is added to the output of the filter circuit 24 via the output signal and output as the control signal 104.

The output of the filter circuit 24 is the control signal 103.
Is a smoothed signal, and the D / A converter 29 is added to this signal.
The first coarse tuning is performed by adding the outputs of the above. That is, the oscillation frequency "fvc of the voltage controlled oscillator 4"
An appropriate value is set in the D / A converter 29 so that o "is outside the window width shown by" W1 "in FIG. 5 which is selected when the coarse tuning circuit 50 is in the fast coarse tuning mode.

That is, fvco << ft (13) In Case of, fvco <ft-N · fc (14) Set a value such that fvco >> ft (15) In Case of, fvco> ft + N · fc (16) Set a value such that

For example, in "T001" in FIG. 2, the oscillation frequency "fvco" is much higher than the target frequency "ft" (fvco >> ft), so that the switch circuit 25 is "T002" at the time "T002" in FIG. When it is turned "ON" and the set value is "Vda", the output of the D / A converter 29 is "
Since it becomes Vda ”and is added to the output of the filter circuit 24 and supplied to the voltage controlled oscillator as the control signal 104, the oscillation frequency“ fvco ”of the voltage controlled oscillator is lowered. Therefore, from the equations (15) and (16), As can be seen, the oscillation frequency “fvco” is “fvco> ft + N · fc”.
Changes to

Then, as in the conventional example, "T00" in FIG.
At the time of 3 ", the output of the control signal 103 becomes" -V1 ", and the second coarse tuning is performed. For example, the D / A converter 2
9 and the control signal 104 is added to the output of FIG.
As shown in 1 ", it decreases according to the time constant of the filter circuit 24 and becomes" V2nd "at the time" T004 "in FIG.

Similarly, at the time of "T005" in FIG. 2, the output of the control signal 103 becomes "-V2", and the third coarse tuning is performed. For example, the output of the D / A converter 29 is added, and the control signal 104 decreases according to the time constant of the filter circuit 24 as shown by "SL02" in FIG.
It becomes "V3rd" at the time of T006 ".

At this point, the oscillation frequency of the voltage controlled oscillator ”
Since "fvco" is in the capture range, the coarse tuning operation of three stages is completed, and the switch circuit 25 receives "OF" by the lock detection signal of the switching circuit 17 in order to reduce the influence of noise.
It becomes F ".

That is, first, the outputs of the D / A converters 29 are added, and the oscillation frequency "fvco" is roughly tuned to near the window width at the time of fast coarse tuning shown by "W1" in FIG. 2 coarsely tuned with a short counting time, and thirdly, when approaching the capture range, coarsely tuned with high resolution with a long counting time, so that the capture range is narrow and the oscillation frequency "fvco" is the target frequency "ft". It is possible to shorten the coarse tuning time even when the distance is significantly different from.

As a result, by performing coarse tuning in three steps, the capture range is narrow and the oscillation frequency
Even when fvco "is far from the target frequency" ft ", the coarse tuning time can be shortened.

In the explanation of FIG. 1, the D / A converter 29 is arranged so that the oscillation frequency "fvco" of the voltage controlled oscillator 4 is outside the window width selected by the coarse tuning circuit 50 in the fast coarse tuning mode. An appropriate value is set, but inside the window width selected in the fast coarse tuning mode of the coarse tuning circuit 50, in other words, the window indicated by "W2" in FIG. 5 selected for the high resolution of the coarse tuning circuit 50. An appropriate value may be set so that it is outside the width.

In this case, the coarse tuning operation is performed by the first coarse tuning by the D / A converter 29 and the second coarse tuning by which the coarse tuning is performed at a high resolution with a long counting time when approaching the capture range. The coarse tuning time is further shortened because the fast coarse tuning operation is omitted after completion, and the coarse tuning time is shortened even when the capture range is narrow and the oscillation frequency “fvco” is far from the target frequency “ft”. It can be shortened.

In addition, when the voltage-controlled oscillator is individually adjusted and checked, the switch circuits 25 and 26 are turned "OFF" and the switch circuit 27 is turned "ON" to disconnect the phase locked loop, and the output of the D / A converter 29 is output. Since the voltage is directly supplied to the voltage controlled oscillator, the oscillation frequency adjustment test can be easily performed by setting an appropriate value in the D / A converter 29.

Further, as for the switch circuit 25, it is possible to use a switch circuit which turns on / off according to a threshold value of a diode, instead of a switch circuit which turns on / off according to an external control signal.

That is, the switch circuit 25 in FIG. 1 is composed of diodes whose polarities are oppositely connected in parallel. At this time, the threshold value of the diode is set to "Vth", and the oscillation frequency "fvco" of the voltage controlled oscillator 4 is set to the target frequency ".
Data is set in the D / A converter 29 so that the output of the filter circuit 24 when it matches ft ”falls within the range of“ ± Vth ”of the amplifier 28.

As a result, the output of the filter circuit 24 becomes a value "Vth" away from the output of the amplifier 28 at the end of the first coarse tuning, and the output of the filter circuit 24 at the end of the second or the third coarse tuning. The output is the output of the amplifier 28
Since it is within the range of ± Vth ”, the diode forming the switch circuit 25 is turned“ OFF ”.

[0058]

As is apparent from the above description,
The present invention has the following effects. According to the invention of claim 1, by performing the coarse tuning in three steps, the capture range is narrow and the oscillation frequency "fvco".
It is possible to shorten the coarse tuning time even when is far from the target frequency "ft".

According to the second aspect of the invention, the first coarse tuning by the D / A converter and the second coarse tuning by the high resolution with a long counting time when approaching the capture range are performed.
Since the coarse tuning operation is completed by the coarse tuning, the coarse tuning time can be shortened even when the capture range is narrow and the oscillation frequency "fvco" is far from the target frequency "ft". .

According to the third aspect of the present invention, during the adjustment inspection, the phase locked loop is disconnected and the output of the D / A converter is directly supplied to the voltage controlled oscillator, so that the oscillation frequency adjustment inspection is facilitated. It will be possible to do.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a coarse tuning circuit portion of a phase locked loop according to the present invention.

FIG. 2 is a timing diagram showing an operation of the coarse tuning circuit shown in FIG.

FIG. 3 is a configuration block diagram showing an example of a conventional phase synchronization circuit.

FIG. 4 is a configuration block diagram showing an example of a coarse tuning circuit.

5 is an explanatory diagram showing a relationship between a capture range and a control signal 103. FIG.

FIG. 6 is a timing diagram illustrating the operation of the coarse tuning circuit.

[Explanation of symbols]

1 Phase Comparator 2 Adder 3 Loop Filter 4 Voltage Controlled Oscillator 5 Frequency Converter 6 Coarse Tuning Circuit 7 Counter 8 Register 9, 10 Data Selector 11 Gate Generation Circuit 12, 18, 19, 20, 21, 21, 22, 23, 25 , 2
6,27 Switch circuit 13,14 Digital comparator 15,16 AND circuit 17 Switching circuit 24 Filter circuit 28 Amplifier 29 D / A converter 50 Coarse tuning circuit 51 Switch means 52 Output circuit 100 Reference signal input 101 Output signal 102 Frequency signal 103 , 104 Control signal

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-83125 (JP, A) JP-A-5-308282 (JP, A) JP-A-8-51360 (JP, A) JP-A-6- 61852 (JP, A) JP 5-90962 (JP, A) JP 59-231924 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03L 7/00-7 / 26

Claims (3)

(57) [Claims] 1. A phase-locked circuit for controlling an oscillation frequency of a voltage-controlled oscillator to a synchronizable range by a coarse tuning circuit, wherein the coarse tuning circuit counts the oscillation frequency of the voltage-controlled oscillator and a counter for counting the oscillation frequency of the voltage-controlled oscillator. A gate generation circuit for giving two or more kinds of counting time, a digital comparator for comparing different upper and lower limit frequency data corresponding to each counting time with the count value of the counter, and each counting time based on the output of the digital comparator. Corresponding to, an output circuit for generating a first control signal of different magnitude, a filter circuit for smoothing the first control signal, and an output added to the output of the filter circuit to output a second control signal. A D / A converter for generating the count time of the gate generation circuit and the output circuit of the output circuit corresponding to the digital comparator output. A switching circuit for switching the control signal, the first coarse tuning is performed by the output of the D / A converter, the second coarse tuning is performed at a short counting time, and the third coarse tuning having a high resolution is performed at a long counting time. A phase-locked loop circuit characterized by performing. 2. A phase-locked circuit for controlling an oscillation frequency of a voltage-controlled oscillator to a synchronizable range by a coarse-tuned circuit, wherein the coarse-tuned circuit counts an oscillation frequency of the voltage-controlled oscillator and a counter for counting the oscillation frequency of the voltage-controlled oscillator. A gate generation circuit that gives a long counting time, a digital comparator that compares the upper and lower limit frequency data with the count value of the counter, an output circuit that generates a first control signal based on the output of the digital comparator, and the first A filter circuit for smoothing the control signal, a D / A converter for adding an output to the output of the filter circuit to generate a second control signal, and a control signal for the output circuit corresponding to the digital comparator output. A switching circuit for switching, the first coarsely tuned by the output of the D / A converter, and a high resolution first with a long counting time. Phase locked loop circuit and performs the coarse tuning. 3. The phase-locked loop is disconnected during the inspection for adjustment and D
3. The phase locked loop circuit according to claim 1, wherein the output of the A / A converter is directly supplied to the voltage controlled oscillator.