JPH11220390A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit which can maintain the stability of a voltage-controlled oscillation frequency at lock time without increasing a loop gain and shorten a lock-up time. SOLUTION: The phase-locked loop circuit is constituted by connecting a phase comparing circuit 1, a charge pump circuit 2, a low-pass filter(LPF) 3, a voltage-controlled oscillation circuit(VCO) 4, and a frequency dividing circuit 5 in a looped state and providing a voltage decision circuit 6 which decides the output voltage of the low-pass filter 3; and this voltage decision circuit 6 controls the output of the charge pump circuit 2 to put the output voltage of the LPF 3 close to a lock state and then move to PLL operation, thereby shortening the lock-up time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (hereinafter, referred to as a PLL circuit) used for, for example, a frequency synthesizer type electronic tuning tuner, and more particularly to an output of a phase comparison circuit in a phase locked loop. The present invention relates to a PLL circuit having a charge pump circuit for generating a voltage level having a corresponding DC component.

[0002]

2. Description of the Related Art FIG. 5 shows a PLL circuit used in a conventional frequency synthesizer. In this PLL circuit, a phase comparison circuit 1 compares a phase of a reference frequency R (hereinafter, referred to as a signal R) and a phase of an output signal S of a frequency dividing circuit 5 and determines a phase of the two signals R and S according to the context. A signal P for controlling the output of the charge pump circuit 2 is output. For example,
When the phase difference between the two signals R and S is substantially zero, the output of the charge pump circuit 2 is set to a high impedance state (floating state). When the phase of the signal S is ahead of the phase of the signal R, the output of the charge pump circuit 2 is set to "L" level. Conversely, when the phase of the signal S is behind the phase of the signal R, the output of the charge pump circuit 2 is set to the “H” level.

The charge pump circuit 2 includes a phase comparison circuit 1
To generate a voltage level having a DC component corresponding to the output of. A low-pass filter (hereinafter referred to as LPF) 3 converts the output voltage of the charge pump circuit 2 into DC.

A voltage controlled oscillator (hereinafter referred to as VCO)
4, an output voltage (DC voltage) of the LPF 3 is supplied as a control voltage, and the oscillation frequency f is adjusted according to the control voltage level.
v is controlled. The frequency dividing circuit 5 divides the oscillation frequency of the VCO 4 by a certain frequency dividing ratio N.

A phase comparison circuit 1, a charge pump circuit 2,
The LPF 3, VCO 4 and frequency dividing circuit 5 form a PLL circuit.

The operation of the PLL circuit is well known and will not be described in detail. However, the oscillation frequency fv is N times the frequency of an output signal R of a reference frequency generation circuit (not shown). I have.

[0007]

The conventional PL
In the L circuit, a measure is taken to increase the loop gain in order to reduce the lock-up time. That is,
LPF 3 for increasing the output voltage of charge pump circuit 2
, The control voltage sensitivity of the VCO 4 is increased, or the frequency dividing ratio N of the frequency dividing circuit 5 is reduced. However, in these methods PL
The L circuit reacts too sensitively and the VCO
The problem arises that the stability of the oscillation frequency fv becomes worse.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a PLL circuit which can maintain a stable oscillation frequency of a VCO at the time of locking without increasing a loop gain and can shorten a lock-up time. With the goal.

[0009]

According to the present invention, there is provided a phase comparison circuit, a charge pump circuit, and an LP.
In a PLL circuit in which the F, the VCO, and the frequency dividing circuit or the variable frequency dividing circuit are connected in a loop, the output voltage of the LPF can be arbitrarily set to some extent before the operation of the PLL circuit starts up.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The state of the PLL circuit at the time of locking is brought close to the time when the operation of the PLL circuit starts up. The lock state indicates a state in which an arbitrary VCO oscillation frequency is oscillating stably. Since the output voltage of the LPF is also stabilized at an arbitrary value, the output of the charge pump circuit is controlled from the LPF output voltage, and the state at the time of lock is obtained. Close to.

By doing so, the lock-up time can be shortened because the locked state is already close when the operation of the PLL circuit is started. In addition, since there is no need to change the phase comparison circuit, the charge pump circuit, the LPF, the VCO, the frequency divider, or the variable frequency divider forming the PLL circuit, the loop gain is not increased.

Hereinafter, each embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(First Embodiment) FIG. 1 shows a PLL circuit according to a first embodiment of the present invention.

This PLL circuit is different from the conventional PLL circuit described above with reference to FIG. 5 in that a voltage determining circuit 6 for determining the output voltage of the LPF 3 and controlling the output of the charge pump circuit 2 is added. The differences are the same, and the others are the same.

The voltage judgment circuit 6 has a judgment voltage level, and the charge pump circuit 2 is based on the judgment voltage level.
Control the output of For example, if the output voltage of the LPF 3 is higher than the determination voltage level, the output of the charge pump circuit 2 is set to “L”, and the output voltage of the LPF 3 is reduced. LPF
If the output voltage of the LPF 3 is lower than the determination voltage level, the output of the charge pump circuit 2 is set to “H”, and the output voltage of the LPF 3 is raised.

If the above operation is performed and the output voltage of the LPF 3 is brought close to the locked state, and then the operation shifts to the PLL operation,
Lock-up time can be reduced.

(Embodiment 2) FIG. 2 shows a PLL circuit according to Embodiment 2 of the present invention.

This PLL circuit determines the output voltage of the LPF 3 and controls the output of the phase comparison circuit 1 in comparison with the conventional PLL circuit described above with reference to FIG.
Are added, and the others are the same.

The voltage judgment circuit 6 has a judgment voltage level, and controls the output of the phase comparison circuit 1 based on the judgment voltage level. For example, if the output voltage of LPF 3 is higher than the determination voltage level, phase comparison circuit 1 outputs a signal for setting the output of charge pump circuit 2 to “L”, and lowers the output voltage of LPF 3. If the output voltage of the LPF 3 is lower than the determination voltage level, the phase comparison circuit 1
Is set to “H”, and the output voltage of the LPF 3 is increased.

If the above operation is performed and the output voltage of the LPF 3 is brought close to the locked state, and then the operation shifts to the PLL operation,
Lock-up time can be reduced.

(Embodiment 3) FIG. 3 shows a PLL circuit according to Embodiment 3 of the present invention.

In this PLL circuit, as compared with the conventional PLL circuit described above with reference to FIG. 5, the frequency dividing circuit 5 is specified as the variable frequency dividing circuit 7, and the output voltage of the LPF 3 is determined to determine the variable frequency dividing circuit. 7 is different from the first embodiment in that a voltage determination circuit 6 for controlling the frequency division ratio is added, and the other components are the same.

The voltage judgment circuit 6 has a judgment voltage level, and controls the frequency division ratio of the variable frequency dividing circuit 7 based on the judgment voltage level. For example, if the output voltage of the LPF 3 is higher than the determination voltage level, the frequency division ratio of the variable frequency divider 7 is reduced, and the frequency of the output signal S of the variable frequency divider 7 is increased.
Then, the output of the charge pump 2 becomes “L” by the output signal P of the phase comparison circuit 1, and the output voltage of the LPF 3 decreases. If the output voltage of the LPF 3 is lower than the determination voltage level, the frequency division ratio of the variable frequency divider 7 is increased, and the frequency of the output signal S of the variable frequency divider 7 is reduced. Then, the output of the charge pump circuit 2 becomes “H” by the output signal P of the phase comparison circuit 1, and the output voltage of the LPF 3 is increased.

If the above operation is performed and the output voltage of the LPF 3 is brought close to the locked state, and then the operation shifts to the PLL operation,
Lock-up time can be reduced.

(Embodiment 4) FIG. 4 shows a PLL circuit according to Embodiment 4 of the present invention.

The PLL circuit according to the first embodiment (FIG. 1) and the PLL circuit according to the second embodiment (FIG. 2)
The frequency dividing circuit 5 is specified as a variable frequency dividing circuit 7 and includes a frequency dividing setting circuit 8 for setting a frequency dividing ratio of the variable frequency dividing circuit 7, and the voltage judging circuit 6 has a plurality of judging voltage levels. Setting circuit 8
In that the decision voltage level is controlled and the frequency division ratio of the variable frequency divider 7 is controlled.

The PLL circuit can determine the lock frequency of the oscillation frequency fv of the VCO 4 by the frequency division ratio N of the variable frequency divider 7, and the lock frequency is N of the reference frequency R.
Double. Since the output voltage of the locked state of the LPF 3 can be calculated from the frequency division ratio N and the control voltage characteristics of the VCO 4 from the PLL operation, the frequency division setting circuit 8 for setting the frequency division ratio of the variable frequency divider 7 The voltage judgment circuit 6 is controlled to change the judgment voltage level. Voltage determination circuit 6 performs the same control as in the first to third embodiments.

FIG. 4 shows, as a typical example, the P
This is an example in which an LL circuit is applied. The voltage judgment circuit 6 controls the output of the charge pump circuit 2 based on the judgment voltage level. For example, if the output voltage of LPF 3 is higher than the judgment voltage level, the output of charge pump circuit 2 is set to “L”.
And the output voltage of the LPF 3 is lowered. If the output voltage of LPF 3 is lower than the judgment voltage level, charge pump circuit 2
Is set to “H”, and the output voltage of the LPF 3 is increased.

Thereafter, when it is desired to change the lock frequency of the oscillation frequency fv of the VCO 4 and the frequency division ratio N of the variable frequency dividing circuit 7 is changed, the frequency becomes the judgment voltage level calculated from the frequency dividing ratio N of the variable frequency dividing circuit 7. In order to change, the voltage determination circuit 6 is controlled by the frequency division setting circuit 8.

By performing the above operation, the lock-up time can be shortened by shifting the output voltage of the LPF 3 to the locked state and then shifting to the PLL operation.

Also, when locking from the locked state to the oscillation frequency of another VCO, the lock-up time can be reduced.

[0032]

As described above, according to the present invention, the voltage judgment circuit for judging the output voltage of the low-pass filter includes:
The output of a charge pump circuit, a phase comparison circuit, and a fixed or variable frequency dividing circuit that constitutes a phase locked loop is controlled.
Alternatively, the lock-up time of the phase-locked loop circuit is reduced by controlling the determination voltage level of the voltage determination circuit and the output of the variable frequency divider circuit by the frequency division setting circuit, and the stability of the oscillation frequency of the VCO at the time of locking is maintained. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a PLL circuit according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a PLL circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a PLL circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a PLL circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2 Charge pump circuit 3 Low-pass filter (LPF) 4 Voltage control oscillation circuit (VCO) 5 Divider circuit 6 Voltage judgment circuit 7 Variable divider circuit 8 Divider setting circuit

Claims (4)

[Claims] 1. A phase-locked loop in which a phase comparison circuit, a charge pump circuit, a low-pass filter, a voltage-controlled oscillation circuit, and a frequency-dividing circuit are connected in a loop, and a voltage determination circuit that determines an output voltage of the low-pass filter. Have,
An output of said charge pump circuit is controlled by said voltage judgment circuit, wherein a phase locked loop circuit is provided. 2. A phase-locked loop in which a phase comparison circuit, a charge pump circuit, a low-pass filter, a voltage-controlled oscillation circuit, and a frequency-dividing circuit are connected in a loop, and a voltage determination circuit that determines an output voltage of the low-pass filter. Have,
A phase locked loop circuit, wherein an output of the phase comparison circuit is controlled by the voltage determination circuit. 3. A phase locked loop in which a phase comparison circuit, a charge pump circuit, a low-pass filter, a voltage controlled oscillation circuit, and a variable frequency dividing circuit are connected in a loop, and a voltage determination circuit for determining an output voltage of the low-pass filter. Wherein the voltage determining circuit controls the frequency division ratio of the variable frequency dividing circuit. 4. A phase locked loop circuit in which a phase comparison circuit, a charge pump circuit, a low-pass filter, a voltage controlled oscillation circuit, and a variable frequency dividing circuit are connected in a loop, wherein the voltage determination circuit has a plurality of determination voltage levels. A frequency setting circuit that sets a determination voltage level of the voltage determination circuit calculated from a digital value that sets the frequency division of the variable frequency divider, and controls a frequency division ratio of the variable frequency divider. A phase locked loop circuit characterized by the above.