JPH05347558A - High-speed lock-up synthesizer - Google Patents

Abstract

PURPOSE:To provide a circuit system which locks up a voltage control oscillator at a high speed for a high-speed lock-up synthesizer using a phase locked loop. CONSTITUTION:A loop 10 consists of a voltage controlled oscillator 1A which produces an optional output frequency from the constant voltage, a variable divider 4 which variably divide the optional frequency, a phase comparator 5 which compares the phase of the variable division result with that of the fixed frequency, and a loop filter 2 which smoothes the phase comparison result and generates the constant voltage. The division set value is added to the comparator 5 from the outside and an optional output frequency is transmitted. Then the oscillator 1A is provided with a 1st control terminal (C1) to which the 1st control voltage V1 is applied for fine adjustment of the output frequency and a 2nd control terminal (C2) to which the 2nd control voltage V2 is applied for rough setting of the output frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed lockup synthesizer using a phase locked loop.

Increasing the speed of an oscillation circuit using a phase-locked loop (PLL), which generates an arbitrary frequency by an external signal, is becoming an important issue in the field of digital communication.

However, for example, in a digital cordless telephone, when the PLL synthesizer used does not lock up at high speed and it takes a long time to start up, it becomes difficult to use it for time division multiplex communication.

As the digitalization of mobile communication becomes widespread in the future, the time division multiplex system is expected to become the mainstream, and it is expected that the high-speed lockup of the PLL synthesizer will become a major subject.

[0005]

2. Description of the Related Art A lockup synthesizer using a conventional phase locked loop (PLL) will be described below with reference to FIG.

FIG. 2 is a diagram showing the configuration of a conventional example circuit. In FIG. 2, 1 is a voltage controlled oscillator, 2 is a loop filter, and 3 is a buffer amplifier. 4 is a variable frequency divider,
Reference numeral 5 is a phase comparator, 6 is a reference oscillator, and 7 is a fixed frequency divider.

Reference numeral 10 is a voltage controlled oscillator 1 → buffer amplifier 3 → variable frequency divider 4 → phase comparator 5 → loop filter 2
→ It is a loop formed by the voltage controlled oscillator 1. When the loop 10 receives a signal of a frequency division setting value from the outside, the time until the system of the loop 10 settles in a constant steady state is locked up time. Is called.

In FIG. 2, the reference oscillator 6 generates a fundamental frequency of 10.24 MHz and outputs it to the fixed frequency divider 7,
The fixed frequency divider 7 divides the frequency of 10.24 MHZ to a fixed frequency division ratio, for example, 1/1024, so that a fixed frequency f3 =
10 kHz is produced and the fixed frequency f3 = 10 kHz is applied to the phase comparator 5.

Now, it is assumed that the system of the loop 10 is in a steady state and the output frequency f1 of the buffer amplifier 3 is a constant value of 20.48 MHz. In the variable frequency divider 4, the frequency division set value which is an external signal is controlled to specify the frequency division ratio to 1/2048, and the output frequency f1 fed back from the buffer amplifier 3 is 20.48.
MHZ is divided by 1/2048 to create a variable frequency f2 = 10 kHz, and the variable frequency f2 = 10 kHz is applied to the phase comparator 5.

The phase comparator 5 compares and confirms the magnitude of the fixed frequency f3 = 10 kHz from the fixed frequency divider 7 and the variable frequency f2 = 10 kHz from the variable frequency divider 4, and the difference frequency 0
The differential voltage Vc corresponding to the above is applied to the loop filter 2.

The loop filter 2 smoothes the differential voltage Vc to produce a constant voltage V1 which is a direct current voltage. The constant voltage V1
Is applied to the voltage controlled oscillator 1, the output frequency f1 = 20.48
MHZ is generated and this output frequency f1 = 20.48 MHZ is sent as the output of the buffer amplifier 3.

In the above operation, when it is desired to change the output frequency f1, the frequency division setting value of the variable frequency divider 4 is variably controlled. For example, when the frequency division setting value is set to 1/2050, the variable frequency f2 of the variable frequency divider 4 becomes excessively 9.99 kHz.

The phase comparator 5 has a fixed frequency f3 = 10 kHz.
It was confirmed that the difference frequency was 0.01 kHz by comparing z with the excessive variable frequency f2 = 9.99 kHz,
A difference voltage Vc ′ corresponding to this difference frequency of 0.01 kHz is applied to the loop filter 2.

The loop filter 2 smoothes the differential voltage Vc 'to create a constant voltage V1', and applies the constant voltage V1 'to the voltage controlled oscillator 1 to generate an excessive output frequency f1', and the output frequency f1 'is output from the buffer amplifier 3. It should be noted that the excessive output frequency f1'≈20.50 MHZ.

The output frequency f1'≈20.50 MHZ is a loop
The system of 10 is fed back and circulated several times for correction, and the output of the voltage controlled oscillator 1 is finally controlled so as to settle to the steady value of the constant voltage V1. The output frequency from the buffer amplifier 3 becomes a constant value of f1 = 20.50 MHZ and is sent to the outside.

Further, the output frequency f1 is branched and applied to the variable frequency divider 4, and is divided by the variable frequency divider 4 to obtain a variable frequency f2 = 10 kHz. At this point, the difference frequency of the phase comparator 5 is It matches 0 and maintains this steady state thereafter.

As described above, after a certain lock-up time, the output frequency f1 reaches a constant value of 20.50 MHz. In the conventional PLL synthesizer, in order to shorten the lockup time, (1) the sensitivity (Δf1 / ΔVd) of the voltage controlled oscillator 1 is increased. (2) The capacitor C on the low-pass filter side that constitutes the loop filter 2 is reduced, and the cutoff frequency of the loop filter 2 is increased.

Although the speed-up is realized by means such as the above, (a) When the above (1) is realized, the voltage controlled oscillator 1 is easily affected by noise (N), that is, the signal / noise characteristic ( C / N characteristics) deteriorate. (b) When the above (1) is realized, the interval of the output frequency f1 of the voltage controlled oscillator 1 becomes large. In other words, loop filter 2
The attenuation characteristic of is determined by the capacitor C of the low pass filter, and it is necessary to reduce the value of the capacitor C in order to increase the cutoff frequency.

However, when the value of the capacitor C is reduced, the frequency separation becomes difficult, resulting in a contradiction.
There is no choice but to increase the frequency (f2 in the conventional example) interval,
As a result, the frequency distribution becomes coarse.

Therefore, none of the means (1) and (2) works effectively, and the conventional circuit has to wait until the loop 10 is locked up.

[0021]

Therefore, in the conventional phase locked loop, there is a problem in that there is no choice but to wait until the PLL synthesizer locks.

An object of the present invention is to provide a circuit system that locks up a voltage controlled oscillator at high speed.

[0023]

In order to achieve the above object, as shown in FIG. 1, in the first aspect of the present invention, a voltage controlled oscillator 1A which generates an arbitrary output frequency when a constant voltage is applied, and the arbitrary frequency. A variable frequency divider 4 for performing variable frequency division, and a phase comparator 5 for performing a phase comparison between the variable frequency division result and a predetermined fixed frequency.
And a loop 10 is formed from the loop filter 2 that smoothes the phase comparison result to produce the constant voltage, and the phase comparator 5
In which a frequency division setting value is externally applied to send out the arbitrary output frequency, a first control terminal to which a first control voltage V1 for finely adjusting the output frequency is applied to the voltage controlled oscillator 1A. (C1) and a second control terminal (C2) to which a second control voltage V2 for roughly setting the output frequency is applied are provided, and the second control voltage V2 is set in advance by the CPU.
The second control voltage V2 corresponding to the output frequency is read from the CPU 13 and stored in the second CPU 13.
It is configured to be added to the control terminal (C2).

Further, in the second invention, the second control voltage V2 of the voltage controlled oscillator 1A stored in the CPU 13 is corrected by the temperature of the loop 10 system detected by the temperature detecting element 11.

[0025]

As shown in FIG. 1, the present invention relates to a first control terminal (C1) to which a first control voltage V1 for finely adjusting the output frequency is applied to the voltage controlled oscillator 1A and the output frequency. Second control voltage V2 for coarse setting is applied
A control terminal (C2) is provided, and the second control voltage V2 of the voltage controlled oscillator 1 applied to the second control terminal (C2) is stored in the control CPU 13 and is output under the control of the control CPU 13 to output the loop 10. I try to reduce the lockup time.

Further, in the second invention, a temperature detecting element
At the temperature of the loop 10 system detected by 11, the control C
The second control voltage V2 of the voltage controlled oscillator 1A stored in the PU 13 is corrected.

Therefore, according to both the first invention and the second invention, the temperature-corrected and designated second control voltage V2 is applied to the voltage controlled oscillator 1 so that a predetermined output frequency is outputted at a higher speed. The lockup time of the voltage controlled oscillator 1 can be shortened.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lockup synthesizer using a phase locked loop according to the present invention will be described below with reference to FIG. FIG. 1 is a diagram showing the configuration of an embodiment circuit of the present invention.

In FIG. 1, 1A and 11, 12, 13, 14 are circuits of the present invention, 1A is a voltage controlled oscillator, and
11 is a temperature detecting element, 12 is an analog / digital (A /
D) converter, 13 is a control central processing unit (control CPU) having a built-in read-only memory (ROM) 13a, and 14 is a D / A (digital / analog) converter.

2 to 7 are circuits having the same structure and operation as those of the conventional example, and the description thereof will be omitted below. Figure 1
In the circuit shown in Fig. 1, the voltage controlled oscillator 1A has a structure having a first control terminal (C1) for finely adjusting the output frequency and a second control terminal (C2) for roughly setting the output frequency. , The oscillating frequency of the voltage controlled oscillator 1A can be controlled by the DC voltage applied to C2.

Further, in the ROM 13a of the control CPU 13, a voltage such that the first control voltage V1 of the first control terminal (C1) of the voltage controlled oscillator 1A becomes about 1/2 of the power supply voltage Vcc of the voltage controlled oscillator 1A. Second control terminal (C2) of controlled oscillator 1A
The voltage of the second control voltage V2 is digitized.

Then, the digital value is prepared in advance as Vr, and the required value can be instantly selected so that the frequency of the voltage controlled oscillator 1A is set. Similarly, in the ROM 13a of the control CPU 13, the correction value Δ of the second control voltage V2 of the second control terminal (C2) due to the temperature Δ
V is digitized and prepared.

Hereinafter, description will be added in order of the circuit diagram. (1) For example, the analog value indicating the temperature correction value of the voltage controlled oscillator 1A detected by the temperature detection element 11 is an A / D converter.
At 12, the analog signal is converted into a digital signal, which is taken into the control CPU 13.

(2) The control CPU 13 calculates a correction value ΔV from the value of (1) to correct V2, and generates a coarse DC voltage V2 = Vr + ΔV in the D / A converter 14, It is added to the second control terminal (C2) of the controlled oscillator 1A.

(3) Similar to the conventional example of FIG. 2, the reference oscillator 6
Is applied to the fixed frequency divider 7 to generate a fixed frequency f3, and in the phase comparator 5, the fixed frequency f3 and the output from the buffer amplifier 3 are variably frequency-divided by the variable frequency divider 4 to obtain the phase of the variable frequency f2. Make a comparison.

Then, the phase comparison result is smoothed by the loop filter 2 to generate the first control voltage V1 of the first control terminal (C1) for finely adjusting the voltage controlled oscillator 1A. By the above-mentioned operations (1) to (3), the control state of the voltage-controlled oscillator 1A is instantly coarsely set to the desired output frequency with the preset second control voltage V2, and then the first The loop 10 system is finely adjusted by the control voltage V1 to shorten the lockup time to reach a steady state.

[0037]

As is apparent from the above description, according to the present invention, the lockup time of the PLL is significantly improved from 20 milliseconds to several milliseconds, and two or more PLL synthesizers are conventionally used for speeding up. What has been used is that the circuit can be realized with one synthesizer.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional example circuit.

[Explanation of symbols]

 1, 1A is a voltage controlled oscillator 2 is a loop filter 3 is a buffer amplifier 4 is a variable frequency divider 5 is a phase comparator 6 is a reference oscillator 7 is a fixed frequency divider 10 is a loop 11 is a temperature detecting element 12 is an analog / digital conversion Device (A / D converter) 13 is control central processing unit (control CPU) 13a is read only memory (ROM) 14 is digital / analog converter (D / A converter)

Claims (2)

[Claims] 1. A voltage controlled oscillator (1A) that generates an arbitrary output frequency when a constant voltage is applied, a variable frequency divider (4) that performs variable frequency division of the arbitrary frequency, and a variable frequency division result. A phase comparator (5) for performing phase comparison of a predetermined fixed frequency, and a loop filter for smoothing the phase comparison result to create the constant voltage.
A loop (10) is formed from (2), and the phase comparator (5) is applied with a frequency division setting value from the outside to send out the arbitrary output frequency, wherein the voltage-controlled oscillator (1A) is A first control terminal (C1) to which a first control voltage V1 for finely adjusting the output frequency is applied and a second control terminal (C2) to which a second control voltage V2 for roughly setting the output frequency is applied. And the second control voltage V2 is stored in the CPU (13) in advance, the second control voltage V2 corresponding to the output frequency is read from the CPU (13), and the second control terminal (C) is read.
A high-speed lockup synthesizer characterized in that it is added to 2). 2. The second control voltage V2 of the voltage controlled oscillator (1A) stored in the CPU (13) is corrected by the temperature of the loop (10) system detected by a temperature detecting element (11). The high-speed lockup synthesizer according to claim 1, characterized in that