JPH04344713A - Phase synchronizing circuit - Google Patents
Phase synchronizing circuitInfo
- Publication number
- JPH04344713A JPH04344713A JP3116393A JP11639391A JPH04344713A JP H04344713 A JPH04344713 A JP H04344713A JP 3116393 A JP3116393 A JP 3116393A JP 11639391 A JP11639391 A JP 11639391A JP H04344713 A JPH04344713 A JP H04344713A
- Authority
- JP
- Japan
- Prior art keywords
- output
- amplifier
- controlled oscillator
- voltage
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009499 grossing Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 230000008859 change Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は通信機等に使用される位
相同期(PLL)回路に関し、特に入力基準信号N倍(
Nは自然数)の周波数の信号を出力するPLL回路に関
する。[Industrial Application Field] The present invention relates to a phase-locked lock (PLL) circuit used in communication equipment, etc., and in particular to an input reference signal N times
The present invention relates to a PLL circuit that outputs a signal with a frequency (N is a natural number).
【0002】0002
【従来の技術】従来PLL回路は、図2のブロック図の
ように構成されていた。図2において、1は基準クロッ
ク信号の入力端子、2は位相比較器(PC)、3は低域
ろ波器(LPF)、4は増幅器、8は電圧制御発振器(
VCO)、9はPLL回路の出力端子、10はN分周器
(1/N)である。入力端子1に入力された基準クロッ
ク信号と電圧制御発振器8の出力信号がN分周器10で
N分周された信号は、位相比較器2で位相比較される。
即ち、基準クロック信号とPLL回路の出力信号をN分
周した信号との位相差に比例した信号(第1の誤差出力
)が、位相比較器2の出力に得られる。位相比較器2の
誤差出力は、低域ろ波器3で直流を含む低周波信号に変
換され、増幅器4によって増幅される。増幅された信号
は、電圧制御発振器8の制御端子8aへ入力され、電圧
制御発振器8の出力周波数、即ち出力信号の周波数を制
御する。電圧制御発振器8の出力信号は、N分周器10
へ導かれるとともに、出力端子9へ出力される。上に述
べた様な動作により、出力端子9には、入力端子1に入
力された基準クロック信号に位相同期し、かつその周波
数が基準クロック信号のN倍の周波数である出力信号を
得ることが出来る。2. Description of the Related Art A conventional PLL circuit has been constructed as shown in the block diagram of FIG. In FIG. 2, 1 is an input terminal for a reference clock signal, 2 is a phase comparator (PC), 3 is a low pass filter (LPF), 4 is an amplifier, and 8 is a voltage controlled oscillator (
9 is an output terminal of the PLL circuit, and 10 is an N frequency divider (1/N). The reference clock signal input to the input terminal 1 and the output signal of the voltage controlled oscillator 8 are frequency-divided by N by the N frequency divider 10, and the phases of the signals are compared by the phase comparator 2. That is, a signal (first error output) proportional to the phase difference between the reference clock signal and the signal obtained by dividing the output signal of the PLL circuit by N is obtained at the output of the phase comparator 2. The error output of the phase comparator 2 is converted into a low frequency signal containing direct current by a low pass filter 3 and amplified by an amplifier 4. The amplified signal is input to the control terminal 8a of the voltage controlled oscillator 8, and controls the output frequency of the voltage controlled oscillator 8, that is, the frequency of the output signal. The output signal of the voltage controlled oscillator 8 is passed through the N frequency divider 10
At the same time, it is output to the output terminal 9. Through the operation described above, it is possible to obtain an output signal at the output terminal 9 that is phase-synchronized with the reference clock signal input to the input terminal 1 and whose frequency is N times that of the reference clock signal. I can do it.
【0003】0003
【発明が解決しようとする課題】この従来のPLL回路
においては、基準クロック信号と出力信号の位相差(定
常位相誤差)を電圧制御発振器の特性変化にかかわらず
少ならしめる為に増幅器の利得を大きくしていた。一方
、PLL回路の周波数応答特性の観点からは、増幅器の
利得に応じて、すなわち、増幅器の利得に比例して低域
ろ波器の時定数を大きくする必要があった。従来のPL
L回路は、この様に構成されていたので、大きな時定数
を有する低域ろ波器の為に、電源投入時あるいは基準ク
ロック信号の位相が急変した場合などに増幅器の出力信
号の電圧が電源電圧近くまで上昇あるいは下降して(す
なわち、ダイナミックレンジをこえて)しまう。このた
め、従来のPLL回路は、最終的に基準クロック信号に
位相同期した出力信号を得るまでに著しく時間がかかる
という欠点を有していた。[Problems to be Solved by the Invention] In this conventional PLL circuit, the gain of the amplifier is adjusted to reduce the phase difference (steady phase error) between the reference clock signal and the output signal regardless of changes in the characteristics of the voltage controlled oscillator. I was making it big. On the other hand, from the viewpoint of the frequency response characteristics of the PLL circuit, it is necessary to increase the time constant of the low-pass filter in accordance with the gain of the amplifier, that is, in proportion to the gain of the amplifier. Conventional PL
Since the L circuit was configured in this way, because it is a low-pass filter with a large time constant, the voltage of the output signal of the amplifier changes from the power supply when the power is turned on or when the phase of the reference clock signal suddenly changes. It rises or falls close to the voltage (in other words, it exceeds the dynamic range). For this reason, the conventional PLL circuit has the disadvantage that it takes a considerable amount of time to finally obtain an output signal that is phase-synchronized with the reference clock signal.
【0004】0004
【課題を解決するための手段】本発明のPLL回路は、
基準クロック信号と出力信号をN(Nは自然数)分周し
た信号との位相を比較する位相比較器と、前記位相比較
器の出力信号を平滑化する低域ろ波器と、前記低域ろ波
器の出力信号を増幅する増幅器と、第1の制御端子に入
力される前記増幅器の出力信号により出力周波数が制御
される電圧制御発振器とを備え、前記電圧制御発振器の
出力を出力信号とする位相同期回路において、前記増幅
器の出力信号と予め定められた値の基準電圧とを比較増
幅する比較増幅器と、前記比較増幅器の出力信号を平滑
化し前記平滑出力とする平滑回路とが付加されており、
且つ前記電圧制御発振器は前記平滑出力の入力によって
出力周波数を制御する第2の制御端子を備えている。[Means for Solving the Problems] The PLL circuit of the present invention has the following features:
a phase comparator that compares the phase of a reference clock signal and a signal obtained by frequency-dividing the output signal by N (N is a natural number); a low-pass filter that smoothes the output signal of the phase comparator; and a low-pass filter that smoothes the output signal of the phase comparator. a voltage-controlled oscillator whose output frequency is controlled by the output signal of the amplifier input to a first control terminal, and uses the output of the voltage-controlled oscillator as an output signal. The phase-locked circuit includes a comparison amplifier that compares and amplifies the output signal of the amplifier with a reference voltage having a predetermined value, and a smoothing circuit that smoothes the output signal of the comparison amplifier to produce the smoothed output. ,
Further, the voltage controlled oscillator includes a second control terminal that controls the output frequency by inputting the smoothed output.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明する
。図1は本発明の一実施例のブロック図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.
【0006】図1に示された構成要素、即ち、入力端子
1、位相比較器2、主ループの低域ろ波器3,増幅器4
,出力端子9およびN分周器10は、図2に示した従来
例と同じ機能を有する。また、電圧制御発振器8に代え
て、電圧制御発振器8にさらに制御端子8bが加えられ
ている電圧制御発振器8Aが用いられている。制御端子
8bは、電圧制御発振器8Aの出力周波数を零調整する
ための制御端子である。制御端子8bは、制御端子8a
と同様に、入力電圧に応じて電圧制御発振器8Aの出力
周波数を制御する。上述した構成要素は、電圧制御発振
器8Aの制御端子8bを除き、従来例と同じ接続がされ
ている。The components shown in FIG. 1, namely the input terminal 1, the phase comparator 2, the main loop low-pass filter 3, and the amplifier 4
, output terminal 9 and N frequency divider 10 have the same functions as the conventional example shown in FIG. Further, instead of the voltage controlled oscillator 8, a voltage controlled oscillator 8A is used, which is the voltage controlled oscillator 8 and further includes a control terminal 8b. The control terminal 8b is a control terminal for adjusting the output frequency of the voltage controlled oscillator 8A to zero. The control terminal 8b is the control terminal 8a.
Similarly, the output frequency of the voltage controlled oscillator 8A is controlled according to the input voltage. The above-mentioned components are connected in the same way as in the conventional example except for the control terminal 8b of the voltage controlled oscillator 8A.
【0007】本実施例においては、従来例に加えて、予
め定められた基準電圧Eを発生する基準電圧源5と、基
準電圧と増幅器4の出力信号とを比較し、これを増幅す
る比較増幅器6と、比較増幅器6から出力された信号(
第2の誤差出力)を平滑する平滑回路である副ループの
低域ろ破棄7とを有している。低域ろ波器7の出力は、
電圧制御発振器8Aの制御端子8bに加えられる。In addition to the conventional example, this embodiment includes a reference voltage source 5 that generates a predetermined reference voltage E, and a comparison amplifier that compares the reference voltage with the output signal of the amplifier 4 and amplifies it. 6 and the signal output from the comparator amplifier 6 (
and a sub-loop low-frequency filter discard 7, which is a smoothing circuit for smoothing the second error output). The output of the low-pass filter 7 is
It is applied to the control terminal 8b of the voltage controlled oscillator 8A.
【0008】以下、本実施例の動作を説明する。The operation of this embodiment will be explained below.
【0009】電圧制御発振器8Aにおいて、制御端子8
aの入力電圧対出力周波数の特性が、環境温度の変化あ
るいは印加する電源電圧の変化などにより変化した場合
を考える。この場合には、出力端子9に基準クロック信
号のN倍の周波数をもった信号を得る様に働くPLL回
路の機能により、増幅器4の出力電圧(第1の誤差出力
)が電圧制御発振器8Aの特性変化を補償する方向に変
化する。同時に、増幅器4の出力電圧の変化は、比較増
幅器6にて基準電圧Eと比較されている。比較増幅器6
の第2の誤差出力の変化分は、低域ろ波器7にて平滑化
されたあと、電圧制御発振器8Aの制御端子8bに入力
され、電圧制御発振器8Aの出力信号の周波数を制御す
る。その結果、増幅器4の出力電圧が基準電圧Eと等し
くなる様に、すなわち前述した増幅器4の出力電圧の変
化分を圧縮する様に動作する。言いかえれば、電圧制御
発振器8Aにおいては、何らかの原因で制御端子8aの
入力電圧対出力周波数特性が変化した場合に、新たに設
けた零調用の制御端子8bの入力電圧を変化させ、電圧
制御発振器8Aを制御端子8aの入力電圧対出力周波数
特性の変化を相殺する様に動作させる。従って、電圧制
御発振器8Aは、制御端子8aの入力電圧対出力周波数
特性が外見上変化しない様に構成されている。In the voltage controlled oscillator 8A, the control terminal 8
Consider a case where the input voltage versus output frequency characteristic of a changes due to a change in the environmental temperature or a change in the applied power supply voltage. In this case, due to the function of the PLL circuit that works to obtain a signal having a frequency N times that of the reference clock signal at the output terminal 9, the output voltage (first error output) of the amplifier 4 is changed to the output voltage of the voltage controlled oscillator 8A. It changes in a direction that compensates for the change in characteristics. At the same time, the change in the output voltage of the amplifier 4 is compared with a reference voltage E in a comparator amplifier 6. Comparison amplifier 6
After being smoothed by the low-pass filter 7, the change in the second error output is input to the control terminal 8b of the voltage controlled oscillator 8A to control the frequency of the output signal of the voltage controlled oscillator 8A. As a result, it operates so that the output voltage of the amplifier 4 becomes equal to the reference voltage E, that is, so as to compress the change in the output voltage of the amplifier 4 described above. In other words, in the voltage controlled oscillator 8A, if the input voltage vs. output frequency characteristic of the control terminal 8a changes for some reason, the input voltage of the newly provided zero adjustment control terminal 8b is changed, and the voltage controlled oscillator 8A changes. 8A is operated so as to cancel out the change in the input voltage versus output frequency characteristic of the control terminal 8a. Therefore, the voltage controlled oscillator 8A is configured so that the input voltage versus output frequency characteristic of the control terminal 8a does not change in appearance.
【0010】ここで低域ろ波器7は、PLL回路の応答
に影響しない程度にその時定数を選ばれる。また、比較
増幅器6のダイナミックレンジは、増幅器4の出力電圧
の範囲がPLL回路の通常の同期状態においても又自定
している状態においても定常的にはある狭い範囲にある
ので、広くとる必要がない。従ってPLL回路の過渡特
性を劣化させる要素が少なくなる。Here, the time constant of the low-pass filter 7 is selected to such an extent that it does not affect the response of the PLL circuit. Furthermore, the dynamic range of the comparator amplifier 6 needs to be wide because the range of the output voltage of the amplifier 4 is normally within a certain narrow range even in the normal synchronized state of the PLL circuit and in the self-stable state. There is no. Therefore, the number of factors that degrade the transient characteristics of the PLL circuit is reduced.
【0011】[0011]
【発明の効果】以上説明したように本発明は、電圧制御
発振器に第1の周波数制御端子に加えて、出力周波数の
誤差を零調整するための第2の制御端子設けこの入力電
圧を制御することにより、第1の周波数制御入力端子の
入力電圧対出力周波数特性の変動を圧縮させる様にして
いる。この結果、PLL回路に要求される定常位相誤差
を満足させる為に必要な増幅器の利得が少なくて済み、
また主ループの低減ろ波器の時定数も小さくて済む。従
って、本発明のPLL回路は、電源投入時あるいは入力
基準クロック信号の位相急変時にも、速かに入力基準ク
ロック信号に位相同期した出力信号を得ることが出来る
という効果がある。[Effects of the Invention] As explained above, the present invention provides a voltage controlled oscillator with a second control terminal in addition to the first frequency control terminal for adjusting the error in the output frequency to zero to control the input voltage. By doing so, fluctuations in the input voltage versus output frequency characteristic of the first frequency control input terminal are compressed. As a result, less amplifier gain is required to satisfy the steady phase error required for PLL circuits.
Furthermore, the time constant of the reduction filter in the main loop can also be small. Therefore, the PLL circuit of the present invention has the advantage of being able to quickly obtain an output signal phase-synchronized with the input reference clock signal even when the power is turned on or when the phase of the input reference clock signal suddenly changes.
【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
【図2】従来のPLL回路のブロック図である。FIG. 2 is a block diagram of a conventional PLL circuit.
1 入力端子
2 位相比較器(PC)
3,7 低域ろ波器(LPF)
4 増幅器
5 基準電圧源
6 比較増幅器
8,8A 電圧制御発振器(VCO)8a,8b
制御端子
9 出力端子
10 N分周器(1/N)1 Input terminal 2 Phase comparator (PC) 3, 7 Low pass filter (LPF) 4 Amplifier 5 Reference voltage source 6 Comparison amplifier 8, 8A Voltage controlled oscillator (VCO) 8a, 8b
Control terminal 9 Output terminal 10 N frequency divider (1/N)
Claims (1)
は自然数)分周した信号との位相を比較する位相比較器
と、前記位相比較器の出力信号を平滑化する低域ろ波器
と、前記低域ろ波器の出力信号を増幅する増幅器と、第
1の制御端子に入力される前記増幅器の出力信号により
出力周波数が制御される電圧制御発振器とを備え、前記
電圧制御発振器の出力を出力信号とする位相同期回路に
おいて、前記増幅器の出力信号と予め定められた値の基
準電圧とを比較増幅する比較増幅器と、前記比較増幅器
の出力信号を平滑化し前記平滑出力とする平滑回路とが
付加されており、且つ前記電圧制御発振器は前記平滑出
力の入力によって出力周波数を制御する第2の制御端子
を備えることを特徴とする位相同期回路。[Claim 1] The reference clock signal and the output signal are set to N (N
is a natural number); a phase comparator that compares the phase with the frequency-divided signal; a low-pass filter that smoothes the output signal of the phase comparator; and an amplifier that amplifies the output signal of the low-pass filter. , and a voltage controlled oscillator whose output frequency is controlled by the output signal of the amplifier input to a first control terminal, the phase locked circuit having an output signal of the voltage controlled oscillator as an output signal, the output signal of the amplifier and a reference voltage of a predetermined value, and a smoothing circuit that smoothes the output signal of the comparison amplifier to produce the smoothed output, and the voltage controlled oscillator is configured to output the smoothed output. A phase synchronized circuit comprising a second control terminal that controls an output frequency according to an input of the phase synchronization circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3116393A JPH04344713A (en) | 1991-05-22 | 1991-05-22 | Phase synchronizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3116393A JPH04344713A (en) | 1991-05-22 | 1991-05-22 | Phase synchronizing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04344713A true JPH04344713A (en) | 1992-12-01 |
Family
ID=14685924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3116393A Pending JPH04344713A (en) | 1991-05-22 | 1991-05-22 | Phase synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04344713A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2385721A (en) * | 2001-12-19 | 2003-08-27 | John David Hopper | System for wiring a building and componebts of the system |
JP2006333323A (en) * | 2005-05-30 | 2006-12-07 | Mitsubishi Electric Corp | Pll circuit |
-
1991
- 1991-05-22 JP JP3116393A patent/JPH04344713A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2385721A (en) * | 2001-12-19 | 2003-08-27 | John David Hopper | System for wiring a building and componebts of the system |
JP2006333323A (en) * | 2005-05-30 | 2006-12-07 | Mitsubishi Electric Corp | Pll circuit |
JP4667963B2 (en) * | 2005-05-30 | 2011-04-13 | 三菱電機株式会社 | PLL circuit |
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