JPH04344713A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease the gain of an amplifier and to reduce the time constant of a low pass filter of a main loop. CONSTITUTION:The phase synchronization circuit composed of a phase comparator 2, the low pass filter of a main loop, an amplifier 4, a voltage controlled oscillator 8A and a 1/N frequency divider circuit 10 converts a reference clock signal inputted from an input terminal 1 into an output signal having the frequency of the multiple of N of the frequency of the reference clock signal and outputs the result to an output terminal 9. The frequency of an output signal of the voltage controlled oscillator 8A is controlled by using an input voltage from a control terminal 8a to the control terminal 8b of the voltage controlled oscillator 8A. A comparator amplifier 6 compares the output of the amplifier 4 with a reference voltage E supplied from a reference voltage source 5 and amplifies the result, a low pass filter 7 amoothes the signal result of comparison and amplification and the smoothed signal is inputted to the control terminal 8b of the voltage controlled oscillator 8A.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a phase-locked lock (PLL) circuit used in communication equipment, etc., and in particular to an input reference signal N times
The present invention relates to a PLL circuit that outputs a signal with a frequency (N is a natural number).

0002

2. Description of the Related Art A conventional PLL circuit has been constructed as shown in the block diagram of FIG. In FIG. 2, 1 is an input terminal for a reference clock signal, 2 is a phase comparator (PC), 3 is a low pass filter (LPF), 4 is an amplifier, and 8 is a voltage controlled oscillator (
9 is an output terminal of the PLL circuit, and 10 is an N frequency divider (1/N). The reference clock signal input to the input terminal 1 and the output signal of the voltage controlled oscillator 8 are frequency-divided by N by the N frequency divider 10, and the phases of the signals are compared by the phase comparator 2. That is, a signal (first error output) proportional to the phase difference between the reference clock signal and the signal obtained by dividing the output signal of the PLL circuit by N is obtained at the output of the phase comparator 2. The error output of the phase comparator 2 is converted into a low frequency signal containing direct current by a low pass filter 3 and amplified by an amplifier 4. The amplified signal is input to the control terminal 8a of the voltage controlled oscillator 8, and controls the output frequency of the voltage controlled oscillator 8, that is, the frequency of the output signal. The output signal of the voltage controlled oscillator 8 is passed through the N frequency divider 10
At the same time, it is output to the output terminal 9. Through the operation described above, it is possible to obtain an output signal at the output terminal 9 that is phase-synchronized with the reference clock signal input to the input terminal 1 and whose frequency is N times that of the reference clock signal. I can do it.

0003

[Problems to be Solved by the Invention] In this conventional PLL circuit, the gain of the amplifier is adjusted to reduce the phase difference (steady phase error) between the reference clock signal and the output signal regardless of changes in the characteristics of the voltage controlled oscillator. I was making it big. On the other hand, from the viewpoint of the frequency response characteristics of the PLL circuit, it is necessary to increase the time constant of the low-pass filter in accordance with the gain of the amplifier, that is, in proportion to the gain of the amplifier. Conventional PL
Since the L circuit was configured in this way, because it is a low-pass filter with a large time constant, the voltage of the output signal of the amplifier changes from the power supply when the power is turned on or when the phase of the reference clock signal suddenly changes. It rises or falls close to the voltage (in other words, it exceeds the dynamic range). For this reason, the conventional PLL circuit has the disadvantage that it takes a considerable amount of time to finally obtain an output signal that is phase-synchronized with the reference clock signal.

0004

[Means for Solving the Problems] The PLL circuit of the present invention has the following features:
a phase comparator that compares the phase of a reference clock signal and a signal obtained by frequency-dividing the output signal by N (N is a natural number); a low-pass filter that smoothes the output signal of the phase comparator; and a low-pass filter that smoothes the output signal of the phase comparator. a voltage-controlled oscillator whose output frequency is controlled by the output signal of the amplifier input to a first control terminal, and uses the output of the voltage-controlled oscillator as an output signal. The phase-locked circuit includes a comparison amplifier that compares and amplifies the output signal of the amplifier with a reference voltage having a predetermined value, and a smoothing circuit that smoothes the output signal of the comparison amplifier to produce the smoothed output. ,
Further, the voltage controlled oscillator includes a second control terminal that controls the output frequency by inputting the smoothed output.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

The components shown in FIG. 1, namely the input terminal 1, the phase comparator 2, the main loop low-pass filter 3, and the amplifier 4
, output terminal 9 and N frequency divider 10 have the same functions as the conventional example shown in FIG. Further, instead of the voltage controlled oscillator 8, a voltage controlled oscillator 8A is used, which is the voltage controlled oscillator 8 and further includes a control terminal 8b. The control terminal 8b is a control terminal for adjusting the output frequency of the voltage controlled oscillator 8A to zero. The control terminal 8b is the control terminal 8a.
Similarly, the output frequency of the voltage controlled oscillator 8A is controlled according to the input voltage. The above-mentioned components are connected in the same way as in the conventional example except for the control terminal 8b of the voltage controlled oscillator 8A.

In addition to the conventional example, this embodiment includes a reference voltage source 5 that generates a predetermined reference voltage E, and a comparison amplifier that compares the reference voltage with the output signal of the amplifier 4 and amplifies it. 6 and the signal output from the comparator amplifier 6 (
and a sub-loop low-frequency filter discard 7, which is a smoothing circuit for smoothing the second error output). The output of the low-pass filter 7 is
It is applied to the control terminal 8b of the voltage controlled oscillator 8A.

The operation of this embodiment will be explained below.

In the voltage controlled oscillator 8A, the control terminal 8
Consider a case where the input voltage versus output frequency characteristic of a changes due to a change in the environmental temperature or a change in the applied power supply voltage. In this case, due to the function of the PLL circuit that works to obtain a signal having a frequency N times that of the reference clock signal at the output terminal 9, the output voltage (first error output) of the amplifier 4 is changed to the output voltage of the voltage controlled oscillator 8A. It changes in a direction that compensates for the change in characteristics. At the same time, the change in the output voltage of the amplifier 4 is compared with a reference voltage E in a comparator amplifier 6. Comparison amplifier 6
After being smoothed by the low-pass filter 7, the change in the second error output is input to the control terminal 8b of the voltage controlled oscillator 8A to control the frequency of the output signal of the voltage controlled oscillator 8A. As a result, it operates so that the output voltage of the amplifier 4 becomes equal to the reference voltage E, that is, so as to compress the change in the output voltage of the amplifier 4 described above. In other words, in the voltage controlled oscillator 8A, if the input voltage vs. output frequency characteristic of the control terminal 8a changes for some reason, the input voltage of the newly provided zero adjustment control terminal 8b is changed, and the voltage controlled oscillator 8A changes. 8A is operated so as to cancel out the change in the input voltage versus output frequency characteristic of the control terminal 8a. Therefore, the voltage controlled oscillator 8A is configured so that the input voltage versus output frequency characteristic of the control terminal 8a does not change in appearance.

Here, the time constant of the low-pass filter 7 is selected to such an extent that it does not affect the response of the PLL circuit. Furthermore, the dynamic range of the comparator amplifier 6 needs to be wide because the range of the output voltage of the amplifier 4 is normally within a certain narrow range even in the normal synchronized state of the PLL circuit and in the self-stable state. There is no. Therefore, the number of factors that degrade the transient characteristics of the PLL circuit is reduced.

[0011]

[Effects of the Invention] As explained above, the present invention provides a voltage controlled oscillator with a second control terminal in addition to the first frequency control terminal for adjusting the error in the output frequency to zero to control the input voltage. By doing so, fluctuations in the input voltage versus output frequency characteristic of the first frequency control input terminal are compressed. As a result, less amplifier gain is required to satisfy the steady phase error required for PLL circuits.
Furthermore, the time constant of the reduction filter in the main loop can also be small. Therefore, the PLL circuit of the present invention has the advantage of being able to quickly obtain an output signal phase-synchronized with the input reference clock signal even when the power is turned on or when the phase of the input reference clock signal suddenly changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

1 Input terminal 2 Phase comparator (PC) 3, 7 Low pass filter (LPF) 4 Amplifier 5 Reference voltage source 6 Comparison amplifier 8, 8A Voltage controlled oscillator (VCO) 8a, 8b
Control terminal 9 Output terminal 10 N frequency divider (1/N)

Claims (1)

[Claims] [Claim 1] The reference clock signal and the output signal are set to N (N
is a natural number); a phase comparator that compares the phase with the frequency-divided signal; a low-pass filter that smoothes the output signal of the phase comparator; and an amplifier that amplifies the output signal of the low-pass filter. , and a voltage controlled oscillator whose output frequency is controlled by the output signal of the amplifier input to a first control terminal, the phase locked circuit having an output signal of the voltage controlled oscillator as an output signal, the output signal of the amplifier and a reference voltage of a predetermined value, and a smoothing circuit that smoothes the output signal of the comparison amplifier to produce the smoothed output, and the voltage controlled oscillator is configured to output the smoothed output. A phase synchronized circuit comprising a second control terminal that controls an output frequency according to an input of the phase synchronization circuit.