JP2006333323A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a PLL circuit which suppresses phase variations of an output clock using a small-scaled control circuit. <P>SOLUTION: A PLL circuit for suppressing phase variations of an output clock comprises: a phase comparing means 2 for detecting a phase difference between an input signal and an output clock of a VCO; an LPF 3 for inputting the output of the phase comparing means and passing only a low frequency component; an ordinary phase error detecting means 5 for inputting the output of the LPF and detecting an ordinary phase error of the PLL circuit; a VCO oscillation frequency offset control means 6 for inputting the output of the ordinary phase error detecting means and generating a VCO oscillation frequency offset control voltage; and a VCO 4 including a VCO oscillation frequency control terminal for inputting the output of the LPF and a VCO oscillation frequency offset control terminal which inputs the output of the VCO oscillation frequency offset control means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit that suppresses phase fluctuations of an output clock.

In an identification circuit in the optical receiver of the optical communication system, the data signal is converted into a binary digital signal of 0 or 1. When converting into such a digital signal, a clock obtained by extracting from the received data signal is required. In recent years, PLL circuits have been applied as clock extraction means in order to realize downsizing and power saving of optical receivers. A ring type VCO is known as one method of a VCO (Voltage Controlled Oscillator) that constitutes a PLL circuit. The oscillation frequency of the ring type VCO is determined by the delay time of a circuit composed of a plurality of differential pairs. Since the delay time of the differential pair depends on the environmental temperature, the oscillation frequency of the ring VCO changes with the environmental temperature. For this reason, the stationary phase error ΔΦ of the PLL circuit expressed by the equation (1) also changes with the environmental temperature.
ΔΦ = Δω / K (1)
Δω is the deviation of the oscillation frequency of the VCO alone due to the environmental temperature change,
K represents the DC gain of the PLL loop.

  In an optical receiver to which a PLL circuit in which a deviation Δω of the oscillation frequency of a single VCO accompanying an environmental temperature change is applied, the phase of the output clock of the PLL circuit changes with the environmental temperature together with the steady phase error ΔΦ. There was a problem that the phase shifted from the optimum phase. In order to solve this problem, the DC gain K of the PLL loop may be increased. However, if K is increased carelessly, the SN ratio in the control signal of the VCO oscillation frequency is degraded, and the VCO output clock waveform is reduced. There was another problem that the included jitter increased. From the above, in order to suppress the phase variation of the output clock of the PLL circuit, it is necessary not only to increase K but also to suppress Δω accompanying the environmental temperature change.

  Therefore, there is a synthesizer device for stabilizing the oscillation frequency deviation Δω of the VCO alone accompanying the environmental temperature change regardless of the environmental temperature variation (see, for example, Patent Document 1). This conventional synthesizer device includes an A / D converter for digitally converting a VCO voltage from a loop filter in a PLL circuit, a digital signal for a stationary phase error from the A / D converter, and a pre-written normal temperature. The VCO oscillation frequency deviation is detected by comparing the digital signal with respect to the stationary phase error at the time, the VCO oscillation frequency in the PLL circuit is controlled, and the frequency control signal from the CPU is DA converted. And a DA converter that outputs to an oscillation frequency control element of the PLL circuit.

JP-A-6-53823 (FIG. 1)

  As described above, the conventional synthesizer device uses an A / D converter, a CPU, and a D / A converter, and thus has a problem that the control circuit becomes large.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a PLL circuit that suppresses a phase variation of an output clock by a small control circuit.

  A PLL circuit according to the present invention is a PLL circuit for suppressing phase fluctuation of an output clock, a phase comparison means for detecting a phase difference between an input signal and an output clock of a VCO, and an output of the phase comparison means as an input. An LPF that passes only the components, a stationary phase error detection means that detects the steady phase error of the PLL circuit using the output of the LPF as input, and a VCO oscillation frequency offset control voltage that receives the output of the stationary phase error detection means as input And a VCO having a VCO oscillation frequency control terminal that receives the output of the LPF and a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means. Features.

  According to the present invention, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit by detecting the steady phase error with a simple analog circuit and offset-controlling the VCO oscillation frequency according to the detection signal.

Embodiments of the present invention will be described below.
Embodiment 1 FIG.
The PLL circuit according to the first embodiment of the present invention detects a steady phase error with a simple analog circuit, and controls the offset of the oscillation frequency of the VCO according to the detected signal, thereby suppressing the phase variation of the output clock of the PLL circuit. To do.

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to Embodiment 1 of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 1 includes a phase comparison unit 2 that detects a phase difference between an input signal and an output clock of the VCO 4, and an LPF (Low Pass Filter) 3 that passes only a low frequency component included in the output of the phase comparison unit 2. A VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, a stationary phase error detection means 5 for detecting a stationary phase error of the PLL circuit by monitoring the output of the LPF 3, and a stationary phase error detection VCO oscillation frequency offset control means 6 for adding / subtracting an offset voltage to / from the output of the means 5 is provided. In FIG. 1, 1 indicates an input signal terminal.

  Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output of the phase comparison means 2. The difference between the positive phase output of LPF3 and the negative phase output of LPF3 is a steady phase error of the PLL circuit. The stationary phase error is input to the stationary phase error detection means 5 and the VCO oscillation frequency control terminal 7.

  The stationary phase error detection means 5 detects a stationary phase error. The VCO oscillation frequency offset control means 6 adds / subtracts DC to the output of the steady phase error detection means 5 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 as inputs, and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

Next, operations of the VCO oscillation frequency deviation detecting means 5 and the VCO oscillation frequency offset control means 6 will be described in detail.
FIG. 2 shows the characteristics of the VCO alone when the ambient temperature and the voltage of the VCO oscillation frequency offset control terminal 8 are constant. The relationship between the steady phase error ΔΦ of the PLL circuit and the VCO oscillation frequency is shown. It rises with the steady phase error ΔΦ of the circuit.

  FIG. 3 shows the relationship between the steady phase error ΔΦ of the PLL circuit and the ambient temperature when there is no control for suppressing the temperature fluctuation of the steady phase error ΔΦ of the PLL circuit. In FIG. 3, the PLL circuit is in a locked state regardless of the presence or absence of the control.

  In the case of no control, 1) the steady phase error ΔΦ of the PLL circuit increases as the ambient temperature increases from FIG. 3 and 2) the increase of the steady phase error ΔΦ of the PLL circuit increases the VCO oscillation frequency from FIG. 3) It can be seen that the oscillation frequency of the single VCO decreases as the environmental temperature increases, and 4) that the PLL circuit increases the steady phase error ΔΦ of the PLL circuit in order to increase the VCO oscillation frequency.

On the other hand, in the case of control, the voltage at the VCO oscillation frequency offset control terminal 8 is controlled so that the steady phase error ΔΦ of the PLL circuit becomes constant regardless of the change in the environmental temperature.
As described above, the phase fluctuation of the output clock of the PLL circuit can be suppressed by detecting the steady phase error ΔΦ of the PLL circuit and controlling the voltage of the VCO oscillation frequency offset control terminal 8.

  FIG. 4 is a block diagram showing the configuration of the stationary phase error detection means 5 and the VCO oscillation frequency offset control means 6. The stationary phase error detection means 5 is a differential amplifier 11 that amplifies the stationary phase error ΔΦ of the PLL circuit by a predetermined gain. The VCO oscillation frequency offset control means 6 adds / subtracts the DC signal from the DC signal source 13 to the output signal of the differential amplifier 11 by the adder 12.

  As described above, the PLL circuit according to the first embodiment of the present invention detects the stationary phase error with a simple analog circuit, and controls the offset of the VCO oscillation frequency according to the detection signal, so that the phase of the output clock of the PLL circuit is Enables fluctuation suppression.

Embodiment 2. FIG.
The PLL circuit according to the second embodiment of the present invention has a stationary phase error, a frequency of a second VCO having only a VCO oscillation frequency control terminal, and a reference clock source whose oscillation frequency is stable against changes in ambient temperature. By detecting the comparison and performing offset control of the VCO oscillation frequency according to the detection signal, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

FIG. 5 is a block diagram showing the configuration of the PLL circuit according to the second embodiment of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 5 includes a phase comparison unit 2 that detects a phase difference between an input signal and a first VCO output clock, an LPF 3 that passes only a low frequency component included in the output of the phase comparison unit 2, and a VCO oscillation. A fixed voltage is applied to the first VCO 4 having the frequency control terminal 7 and the VCO oscillation frequency offset control terminal 8, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and the VCO oscillation frequency control terminal 7 of the second VCO 15. A DC signal source 20 to be applied, a reference clock source 16 whose oscillation frequency is stable against changes in ambient temperature, frequency comparison means 18 for comparing the frequency of the output clock of the VCO 15 and the output clock of the reference clock source 16, and a frequency VCO oscillation frequency offset control means 6 for generating an oscillation frequency offset control voltage according to the output of the comparison means 18; It is provided. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 5, reference numeral 1 denotes an input signal terminal.

  Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means 2. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and the steady phase error ΔΦ of the PLL circuit is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

  On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates the steady phase error ΔΦ of the PLL circuit by comparing the frequency of the VCO 15 and the frequency of the reference clock source 16. The VCO oscillation frequency offset control means 6 adds / subtracts a DC signal to / from the output of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 as inputs, and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

  The frequency comparison means 18 performs frequency comparison, and may be a frequency counter or a frequency comparator, for example.

  As described above, the PLL circuit according to the second embodiment of the present invention has a steady phase error, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and a reference whose oscillation frequency is stable with respect to changes in the ambient temperature. By estimating the frequency with the clock source 16 and performing offset control of the VCO oscillation frequency according to the estimated signal, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit with a small-scale control circuit.

Embodiment 3 FIG.
In the PLL circuit according to the third embodiment of the present invention, the stationary phase error is determined by using the first VCO having the VCO oscillation frequency control terminal and the VCO oscillation frequency offset control terminal, and the second VCO having only the VCO oscillation frequency control terminal. The phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit by performing offset control on the VCO oscillation frequency according to the detection signal.

FIG. 6 is a block diagram showing a configuration of a PLL circuit according to Embodiment 3 of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 6 includes a phase comparison unit 2 that detects the phase difference between the input signal and the output clock of the branching unit 17, an LPF 3 that passes only a low frequency component contained in the output of the phase comparison unit 2, and a VCO oscillation A first VCO 4 having a frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, a branching means 17 for bifurcating the output of the VCO 4, a second VCO 15 having only the VCO oscillation frequency control terminal 7, and a second The DC signal source 20 that applies a fixed voltage to the VCO oscillation frequency control terminal 7 of the VCO 15, the frequency comparison means 18 that compares the oscillation frequency of the output clock of the VCO 15 and the output clock of the branch means 17, and the output of the frequency comparison means 18 VCO oscillation frequency offset control means 6 for generating an oscillation frequency offset control voltage according to the above. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 6, reference numeral 1 denotes an input signal terminal.

  Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The output clock of the VCO 4 is branched into two by the branching unit 17 and then input to the phase comparison unit 2 and the frequency comparison unit 18. The phase comparison unit 2 performs phase comparison between the input signal and the output of the branching unit 17 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

  On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates ΔΦ by comparing the frequency of the VCO 15 with the frequency of the branching means 17. The VCO oscillation frequency offset control means 6 adds / subtracts the DC signal to / from the output of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output signal of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs.

  The frequency comparison means 18 performs frequency comparison, and may be a frequency counter or a frequency comparator, for example.

  As described above, the PLL circuit according to the third embodiment of the present invention has the steady phase error, the first VCO having the VCO oscillation frequency control terminal 7 and the VCO oscillation frequency offset control terminal 8, and the VCO oscillation frequency control terminal 7. Thus, the phase fluctuation of the output clock of the PLL circuit can be suppressed with a small-scale control circuit by estimating the frequency by comparing the frequency with the second VCO 15 having only the frequency and offset-controlling the VCO oscillation frequency according to the estimated signal.

Embodiment 4 FIG.
The PLL circuit according to the fourth embodiment of the present invention estimates the stationary phase error by frequency comparison between the input signal that is the output of the branching means and the second VCO that has only the VCO oscillation frequency control terminal, and detects the detection result. By controlling the offset of the VCO oscillation frequency according to the signal, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

FIG. 7 is a block diagram showing a configuration of a PLL circuit according to Embodiment 4 of the present invention, which is constituted by a differential circuit.
The PLL circuit shown in FIG. 7 includes a branching means 17 for branching an input signal into two, a first VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, an output signal from the branching means 17 and a first signal. A phase comparison unit 2 that detects a phase difference between the VCO output clocks of the VCO, an LPF 3 that passes only a low-frequency component included in the output of the phase comparison unit 2, a second VCO 15 that has only a VCO oscillation frequency control terminal 7, Frequency comparison for estimating a stationary phase error by comparing the frequency of the DC signal source 20 that applies a fixed voltage to the VCO oscillation frequency control terminal 7 of the second VCO 15, the output clock of the VCO 15, and the input signal that is the output of the branching means 17. Means 18 and a VCO oscillation frequency offset control for generating an oscillation frequency offset control voltage according to the output of frequency comparison means 18. And a means 6. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 7, reference numeral 1 denotes an input signal terminal.

  Next, the operation will be described. An input signal from the input signal terminal 1 is branched into two by the branching means 17 and input to the phase comparison means 2 and the frequency comparison means 18. The phase comparison means 2 performs a phase comparison between the VCO 4 and the output of the branching means 17 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

  On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates ΔΦ by frequency comparison between the output clock of the VCO 15 and the input signal that is the output of the branch means 17. The VCO oscillation frequency offset control means 6 adds / subtracts a DC signal to the output signal of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

  The VCO oscillation frequency deviation detecting means 5 performs frequency comparison, and may be, for example, a frequency comparator.

  As described above, the PLL circuit according to the fourth embodiment of the present invention uses the stationary phase error as the frequency of the input signal that is the output of the branching means 17 and the second VCO 15 that has only the VCO oscillation frequency control terminal 7. By estimating the comparison and performing offset control of the VCO oscillation frequency in accordance with the estimated signal, the phase fluctuation of the output clock of the PLL circuit can be suppressed by a small-scale control circuit.

Embodiment 5. FIG.
In the PLL circuit according to the fifth embodiment of the present invention, the steady phase error is estimated by the second VCO having only the VCO oscillation frequency control terminal and the electric spectrum monitoring means, and the VCO oscillation frequency is determined according to the estimated signal. By performing offset control, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

FIG. 8 is a block diagram showing the configuration of the PLL circuit according to the fifth embodiment of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 8 includes a first VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, and phase comparison means 2 for detecting the phase difference between the input signal and the first VCO output clock. A fixed voltage is applied to the LPF 3 that passes only the low frequency component included in the output of the phase comparison means 2, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and the VCO oscillation frequency control terminal 7 of the second VCO 15. DC signal source 20 to be applied, electric spectrum monitor means 19 for estimating the steady phase error by monitoring the output spectrum of the VCO 15, and VCO oscillation frequency offset control for generating an oscillation frequency offset control voltage according to the output of the electric spectrum monitor means 19 Means 6 are provided. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 8, 1 indicates an input signal terminal.

  Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

  On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The electrical spectrum monitoring means 19 estimates ΔΦ by monitoring the output spectrum of the VCO 15. The VCO oscillation frequency offset control means 6 calculates a DC signal from the output signal of the electric spectrum monitor means 19 and outputs it to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

  As described above, the PLL circuit according to the fifth embodiment of the present invention estimates the stationary phase error by the second VCO 15 having only the VCO oscillation frequency control terminal 7 and the electric spectrum monitor means 19, and according to the estimated signal. By performing offset control of the VCO oscillation frequency, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit with a small-scale control circuit.

1 is a block diagram showing a configuration of a PLL circuit according to Embodiment 1 of the present invention. It is a figure which shows the VCO single-piece | unit characteristic (The relationship between a VCO oscillation frequency and the stationary phase error (DELTA) (PHI) of PLL circuit). It is a figure which shows the relationship between stationary phase error (DELTA) (PHI) circuit and environmental temperature. It is a block diagram which shows the structure of a stationary phase error detection means and a VCO oscillation frequency offset control means. It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 5 of this invention.

Explanation of symbols

  1 input signal terminal, 2 phase comparison means, 3 LPF (low pass filter), 4 VCO (Voltage Controlled Oscillator), 5 stationary phase error detection means, 6 VCO oscillation frequency offset control means, 7 VCO oscillation frequency control terminal, 8 VCO Oscillation frequency offset control terminal, 11 differential amplifier, 12 adder, 13 DC signal source, 15 VCO, 16 reference clock source, 17 branching means, 18 frequency comparison means, 19 electrical spectrum monitoring means, 20 DC signal source.

Claims (7)

In the PLL circuit that suppresses the phase variation of the output clock,
Phase comparison means for detecting a phase difference between the input signal and the output clock of the VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
Stationary phase error detection means for detecting the stationary phase error of the PLL circuit using the output of the LPF as an input;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the stationary phase error detection means as an input;
A PLL circuit comprising: a VCO having a VCO oscillation frequency control terminal that receives an output of the LPF and a VCO oscillation frequency offset control terminal that receives an output of the VCO oscillation frequency offset control means. The PLL circuit according to claim 1,
The VCO oscillation frequency deviation detecting means comprises a differential amplifier,
The VCO oscillation frequency offset control means includes an adder and a direct current (DC) signal source. In the PLL circuit that suppresses the phase variation of the output clock,
Phase comparison means for detecting a phase difference between the input signal and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A reference clock source whose oscillation frequency is stable against changes in ambient temperature,
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between an output clock of the reference clock source and an output clock of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means. In the PLL circuit that suppresses the phase variation of the output clock,
Branching means for taking the output clock of the first VCO as an input and bifurcating the clock;
Phase comparison means for detecting a phase difference between the input signal and the output clock of the branch means;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between the output clock of the second VCO and the output clock of the branch means;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means. The PLL circuit according to claim 3 or 4,
The PLL circuit according to claim 1, wherein the frequency comparison means is constituted by a frequency counter or a frequency comparator. In the PLL circuit that suppresses the phase variation of the output clock,
Branching means for branching the input signal into two;
Phase comparison means for detecting a phase difference between the output signal of the branch means and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between the output signal of the branch means and the output clock of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means. In the PLL circuit that suppresses the phase variation of the output clock,
Phase comparison means for detecting a phase difference between the input signal and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Electrical spectrum monitoring means for detecting the oscillation frequency of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the electric spectrum monitor means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means.

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