JP4667963B2

JP4667963B2 - PLL circuit

Info

Publication number: JP4667963B2
Application number: JP2005157133A
Authority: JP
Inventors: 竜也小林; 仁之田上; 克宏清水
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2005-05-30
Filing date: 2005-05-30
Publication date: 2011-04-13
Anticipated expiration: 2025-05-30
Also published as: JP2006333323A

Description

この発明は、出力クロックの位相変動を抑圧するＰＬＬ（Phase Locked Loop）回路に関するものである。 The present invention relates to a PLL (Phase Locked Loop) circuit that suppresses phase fluctuations of an output clock.

光通信システムの光受信機における識別回路において、データ信号は０あるいは１の２値のデジタル信号に変換される。係るデジタル信号への変換の際には、受信したデータ信号から抽出することで得られるクロックが必要である。近年、光受信機の小型化および省電力化を実現するため、クロック抽出手段として、ＰＬＬ回路が適用されている。ＰＬＬ回路を構成するＶＣＯ（Voltage Controlled Oscillator）の一方式として、リング型ＶＣＯが知られている。リング型ＶＣＯの発振周波数は、複数の差動対から構成される回路の遅延時間で決定される。前記差動対の遅延時間は環境温度に依存するため、リング型ＶＣＯの発振周波数は環境温度と共に変化してしまう。このため、式（１）で表されるＰＬＬ回路の定常位相誤差ΔΦも環境温度と共に変化する。
ΔΦ＝Δω／Ｋ・・・・・（１）
なお、Δωは環境温度変化に伴うＶＣＯ単体の発振周波数の偏差、
ＫはＰＬＬループのＤＣ利得を表す。 In an identification circuit in the optical receiver of the optical communication system, the data signal is converted into a binary digital signal of 0 or 1. When converting into such a digital signal, a clock obtained by extracting from the received data signal is required. In recent years, PLL circuits have been applied as clock extraction means in order to realize downsizing and power saving of optical receivers. A ring type VCO is known as one method of a VCO (Voltage Controlled Oscillator) that constitutes a PLL circuit. The oscillation frequency of the ring type VCO is determined by the delay time of a circuit composed of a plurality of differential pairs. Since the delay time of the differential pair depends on the environmental temperature, the oscillation frequency of the ring VCO changes with the environmental temperature. For this reason, the stationary phase error ΔΦ of the PLL circuit expressed by the equation (1) also changes with the environmental temperature.
ΔΦ = Δω / K (1)
Δω is the deviation of the oscillation frequency of the VCO alone due to the environmental temperature change,
K represents the DC gain of the PLL loop.

環境温度変化に伴うＶＣＯ単体の発振周波数の偏差Δωの生じるＰＬＬ回路が適用された光受信機では、定常位相誤差ΔΦと共にＰＬＬ回路の出力クロックの位相が環境温度で変化するため、識別回路における識別位相が最適位相からずれてしまうという問題があった。この問題を解決するためには、ＰＬＬループのＤＣ利得Ｋを大きくすれば良いが、不用意にＫを大きくすると、ＶＣＯ発振周波数の制御信号におけるＳＮ比の劣化などが生じ、ＶＣＯ出力クロック波形に含まれるジッタが増加するという別の問題もあった。以上より、ＰＬＬ回路の出力クロックの位相変動を抑圧するためには、Ｋを大きくするだけではなく、環境温度変化に伴うΔωを抑圧する必要がある。 In an optical receiver to which a PLL circuit in which a deviation Δω of the oscillation frequency of the VCO alone accompanying an environmental temperature change is applied, the phase of the output clock of the PLL circuit changes with the environmental temperature together with the stationary phase error ΔΦ. There was a problem that the phase shifted from the optimum phase. In order to solve this problem, the DC gain K of the PLL loop may be increased. However, if K is increased carelessly, the SN ratio in the control signal of the VCO oscillation frequency is degraded, and the VCO output clock waveform is reduced. There was another problem that the included jitter increased. From the above, in order to suppress the phase variation of the output clock of the PLL circuit, it is necessary not only to increase K but also to suppress Δω accompanying the environmental temperature change.

そこで、環境温度変動に係わらず、環境温度変化に伴うＶＣＯ単体の発振周波数の偏差Δωを安定化させるためのシンセサイザ装置がある（例えば、特許文献１参照）。この従来例のシンセサイザ装置は、ＰＬＬ回路内のループフィルタからのＶＣＯ電圧をデジタル変換するＡ−Ｄ変換器と、このＡ−Ｄ変換器からの定常位相誤差に対するデジタル信号と、予め書き込まれた常温時の定常位相誤差に対するデジタル信号とを比較することによりＶＣＯの発振周波数偏位を検出し、ＰＬＬ回路内のＶＣＯ発振周波数を制御するＣＰＵと、ＣＰＵからの周波数制御信号をＤ−Ａ変換してＰＬＬ回路の発振周波数制御素子に出力するＤ−Ａ変換器とを備えたものである。 Therefore, there is a synthesizer device for stabilizing the oscillation frequency deviation Δω of the VCO alone accompanying the environmental temperature change regardless of the environmental temperature variation (see, for example, Patent Document 1). This conventional synthesizer device includes an A / D converter for digitally converting a VCO voltage from a loop filter in a PLL circuit, a digital signal for a stationary phase error from the A / D converter, and a pre-written normal temperature. The VCO oscillation frequency deviation is detected by comparing the digital signal with respect to the stationary phase error at the time, the VCO oscillation frequency in the PLL circuit is controlled, and the frequency control signal from the CPU is DA converted. And a DA converter that outputs to an oscillation frequency control element of the PLL circuit.

特開平６−５３８２３号公報（図１）JP-A-6-53823 (FIG. 1)

従来のシンセサイザ装置では、上述したように、Ａ−Ｄ変換器、ＣＰＵ、Ｄ−Ａ変換器が用いられるため、制御回路が大規模になるという問題があった。 As described above, the conventional synthesizer device uses an A / D converter, a CPU, and a D / A converter, and thus has a problem that the control circuit becomes large.

この発明は上記の問題点を解消するためになされたもので、小規模な制御回路により、出力クロックの位相変動を抑圧するＰＬＬ回路を得ることを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a PLL circuit that suppresses a phase variation of an output clock by a small control circuit.

この発明に係るＰＬＬ回路は、出力クロックの位相変動を抑圧するＰＬＬ回路において、入力信号と第一のＶＣＯの出力クロックとの位相差を検出する位相比較手段と、前記位相比較手段の出力を入力とし低周波数成分のみを通過させるＬＰＦと、発振周波数が環境温度の変化に対し安定である基準クロック源と、ＤＣ信号源と、前記ＤＣ信号源の出力を入力とするＶＣＯ発振周波数制御端子を有する第二のＶＣＯと、前記基準クロック源の出力クロックと前記第二のＶＣＯの出力クロックとの周波数差を検出する周波数比較手段と、前記周波数比較手段の出力を入力としＶＣＯ発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段と、前記ＬＰＦの出力を入力とするＶＣＯ発振周波数制御端子および前記ＶＣＯ発振周波数オフセット制御手段の出力を入力とするＶＣＯ発振周波数オフセット制御端子を有する第一のＶＣＯとを備えることを特徴とする。
また、この発明に係るＰＬＬ回路は、出力クロックの位相変動を抑圧するＰＬＬ回路において、第一のＶＣＯの出力クロックを入力としクロックを２分岐する分岐手段と、入力信号と前記分岐手段の出力クロックとの位相差を検出する位相比較手段と、前記位相比較手段の出力を入力とし低周波数成分のみを通過させるＬＰＦと、ＤＣ信号源と、前記ＤＣ信号源の出力を入力とするＶＣＯ発振周波数制御端子を有する第二のＶＣＯと、前記第二のＶＣＯの出力クロックと前記分岐手段の出力クロックとの周波数差を検出する周波数比較手段と、前記周波数比較手段の出力を入力としＶＣＯ発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段と、前記ＬＰＦの出力を入力とするＶＣＯ発振周波数制御端子および前記ＶＣＯ発振周波数オフセット制御手段の出力を入力とするＶＣＯ発振周波数オフセット制御端子を有する第一のＶＣＯとを備えることを特徴とする。
また、この発明に係るＰＬＬ回路は、出力クロックの位相変動を抑圧するＰＬＬ回路において、入力信号を２分岐する分岐手段と、前記分岐手段の出力信号と第一のＶＣＯの出力クロックとの位相差を検出する位相比較手段と、前記位相比較手段の出力を入力とし低周波数成分のみを通過させるＬＰＦと、ＤＣ信号源と、前記ＤＣ信号源の出力を入力とするＶＣＯ発振周波数制御端子を有する第二のＶＣＯと、前記分岐手段の出力信号と前記第二のＶＣＯの出力クロックとの周波数差を検出する周波数比較手段と、前記周波数比較手段の出力を入力としＶＣＯ発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段と、前記ＬＰＦの出力を入力とするＶＣＯ発振周波数制御端子および前記ＶＣＯ発振周波数オフセット制御手段の出力を入力とするＶＣＯ発振周波数オフセット制御端子を有する第一のＶＣＯとを備えることを特徴とする。
さらに、この発明に係るＰＬＬ回路は、出力クロックの位相変動を抑圧するＰＬＬ回路において、入力信号と第一のＶＣＯの出力クロックとの位相差を検出する位相比較手段と、前記位相比較手段の出力を入力とし低周波数成分のみを通過させるＬＰＦと、ＤＣ信号源と、前記ＤＣ信号源の出力を入力とするＶＣＯ発振周波数制御端子を有する第二のＶＣＯと、前記第二のＶＣＯの発振周波数を検出する電気スペクトルモニタ手段と、前記電気スペクトルモニタ手段の出力を入力としＶＣＯ発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段と、前記ＬＰＦの出力を入力とするＶＣＯ発振周波数制御端子および前記ＶＣＯ発振周波数オフセット制御手段の出力を入力とするＶＣＯ発振周波数オフセット制御端子を有する第一のＶＣＯとを備えることを特徴とする。

The PLL circuit according to the present invention is a PLL circuit that suppresses the phase variation of the output clock, and the phase comparison means for detecting the phase difference between the input signal and the output clock of the first VCO, and the output of the phase comparison means And an LPF that allows only low frequency components to pass through, a reference clock source whose oscillation frequency is stable against changes in environmental temperature, a DC signal source, and a VCO oscillation frequency control terminal that receives the output of the DC signal source. A frequency comparison means for detecting a frequency difference between the output clock of the second VCO, the output clock of the reference clock source and the output clock of the second VCO; and an output of the frequency comparison means as an input to obtain a VCO oscillation frequency offset control voltage VCO oscillation frequency offset control means to be generated, a VCO oscillation frequency control terminal that receives the output of the LPF, and the VCO oscillation It characterized in that it comprises a first VCO with a VCO oscillation frequency offset control terminal for receiving the output of the frequency offset control means.
According to another aspect of the present invention, there is provided a PLL circuit that suppresses phase fluctuations of an output clock, a branching unit that receives the output clock of the first VCO and branches the clock into two, an input signal, and an output clock of the branching unit Phase comparison means for detecting a phase difference between the output signal, an LPF that receives the output of the phase comparison means as an input, passes only a low frequency component, a DC signal source, and a VCO oscillation frequency control that receives the output of the DC signal source A second VCO having a terminal, a frequency comparison means for detecting a frequency difference between an output clock of the second VCO and an output clock of the branch means, and an output of the frequency comparison means as an input, and VCO oscillation frequency offset control VCO oscillation frequency offset control means for generating a voltage, a VCO oscillation frequency control terminal that receives the output of the LPF, and the It characterized in that it comprises a first VCO with a VCO oscillation frequency offset control terminal for receiving the output of the CO oscillation frequency offset control means.
According to another aspect of the present invention, there is provided a PLL circuit for suppressing phase fluctuations of an output clock, a branching means for branching an input signal into two, and a phase difference between an output signal of the branching means and an output clock of the first VCO. A phase comparison means for detecting the output, an LPF that receives the output of the phase comparison means as input and passes only a low frequency component, a DC signal source, and a VCO oscillation frequency control terminal that receives the output of the DC signal source as input. A frequency comparison means for detecting a frequency difference between the second VCO, an output signal of the branch means and an output clock of the second VCO, and an output of the frequency comparison means as inputs to generate a VCO oscillation frequency offset control voltage VCO oscillation frequency offset control means, a VCO oscillation frequency control terminal that receives the output of the LPF, and the VCO oscillation frequency offset Characterized in that it comprises a first VCO with a VCO oscillation frequency offset control terminal for receiving the output of the control means.
Further, the PLL circuit according to the present invention is a PLL circuit that suppresses a phase fluctuation of an output clock, a phase comparison unit that detects a phase difference between an input signal and an output clock of the first VCO, and an output of the phase comparison unit The LPF that passes only the low frequency component, the DC signal source, the second VCO that has the VCO oscillation frequency control terminal that receives the output of the DC signal source, and the oscillation frequency of the second VCO. Electric spectrum monitor means for detecting; VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage by using an output of the electric spectrum monitor means; a VCO oscillation frequency control terminal for receiving the output of the LPF; A VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means as an input. Characterized in that it comprises a first and a VCO for.

この発明によれば、定常位相誤差を簡単なアナログ回路で検出し、その検出信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を可能とする。 According to the present invention, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit by detecting the steady phase error with a simple analog circuit and offset-controlling the VCO oscillation frequency according to the detection signal.

以下、この発明の実施の形態を説明する。
実施の形態１．
この発明の実施の形態１に係るＰＬＬ回路は、定常位相誤差を簡単なアナログ回路で検出し、その検出信号に従いＶＣＯの発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動を抑圧するものである。 Embodiments of the present invention will be described below.
Embodiment 1 FIG.
The PLL circuit according to the first embodiment of the present invention detects a steady phase error with a simple analog circuit, and controls the offset of the oscillation frequency of the VCO according to the detected signal, thereby suppressing the phase variation of the output clock of the PLL circuit. To do.

図１は、この発明の実施の形態１に係るＰＬＬ回路の構成を示すブロック図であり、差動回路から構成されている。
図１に示すＰＬＬ回路は、入力信号とＶＣＯ４の出力クロックの位相差を検出する位相比較手段２と、位相比較手段２の出力に含まれる低周波数成分のみを通過させるＬＰＦ（Low Pass Filter）３と、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有するＶＣＯ４と、ＬＰＦ３の出力をモニタすることでＰＬＬ回路の定常位相誤差を検出する定常位相誤差検出手段５と、定常位相誤差検出手段５の出力にオフセット電圧を加算・減算するＶＣＯ発振周波数オフセット制御手段６とを備えている。なお、図１において、１は入力信号端子を示す。 FIG. 1 is a block diagram showing a configuration of a PLL circuit according to Embodiment 1 of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 1 includes a phase comparison unit 2 that detects a phase difference between an input signal and an output clock of the VCO 4, and an LPF (Low Pass Filter) 3 that passes only a low frequency component included in the output of the phase comparison unit 2. A VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, a stationary phase error detection means 5 for detecting a stationary phase error of the PLL circuit by monitoring the output of the LPF 3, and a stationary phase error detection VCO oscillation frequency offset control means 6 for adding / subtracting an offset voltage to / from the output of the means 5 is provided. In FIG. 1, 1 indicates an input signal terminal.

次に、動作について説明する。入力信号端子１からの入力信号は位相比較手段２に入力される。位相比較手段２は、入力信号とＶＣＯ４の出力クロックの位相比較を行い、位相の進み或いは遅れに相当する信号をＬＰＦ３に出力する。ＬＰＦ３は、位相比較手段２の出力に含まれる低周波数成分のみ通過させる。ＬＰＦ３の正相出力とＬＰＦ３の逆相出力との差は、ＰＬＬ回路の定常位相誤差である。定常位相誤差は、定常位相誤差検出手段５と、ＶＣＯ発振周波数制御端子７とに入力される。 Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output of the phase comparison means 2. The difference between the positive phase output of LPF3 and the negative phase output of LPF3 is a steady phase error of the PLL circuit. The stationary phase error is input to the stationary phase error detection means 5 and the VCO oscillation frequency control terminal 7.

定常位相誤差検出手段５は定常位相誤差を検出する。ＶＣＯ発振周波数オフセット制御手段６は、定常位相誤差検出手段５の出力にＤＣを加算・減算し、ＶＣＯ４のＶＣＯ発振周波数オフセット制御端子８に出力する。ＶＣＯ４は、ＬＰＦ３の出力およびＶＣＯ発振周波数オフセット制御手段６の出力を入力とし、それらの入力に相当する位相および周波数で発振する。ＶＣＯ４の出力クロックは位相比較手段２に入力される。 The stationary phase error detection means 5 detects a stationary phase error. The VCO oscillation frequency offset control means 6 adds / subtracts DC to the output of the steady phase error detection means 5 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 as inputs, and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

次に、ＶＣＯ発振周波数偏差検出手段５およびＶＣＯ発振周波数オフセット制御手段６の動作について詳細に説明する。
図２は、環境温度およびＶＣＯ発振周波数オフセット制御端子８の電圧が一定時におけるＶＣＯ単体特性を示すものであり、ＰＬＬ回路の定常位相誤差ΔΦとＶＣＯ発振周波数の関係を表し、ＶＣＯ発振周波数はＰＬＬ回路の定常位相誤差ΔΦとともに上昇する。 Next, operations of the VCO oscillation frequency deviation detecting means 5 and the VCO oscillation frequency offset control means 6 will be described in detail.
FIG. 2 shows the characteristics of the VCO alone when the ambient temperature and the voltage of the VCO oscillation frequency offset control terminal 8 are constant. The relationship between the steady phase error ΔΦ of the PLL circuit and the VCO oscillation frequency is shown. It rises with the steady phase error ΔΦ of the circuit.

また、図３は、ＰＬＬ回路の定常位相誤差ΔΦの温度変動を抑圧する制御がない場合と、ある場合とにおけるＰＬＬ回路の定常位相誤差ΔΦと環境温度の関係を表す。図３では、前記制御の有無に係わらず、ＰＬＬ回路はロック状態である。 FIG. 3 shows the relationship between the steady phase error ΔΦ of the PLL circuit and the ambient temperature when there is no control for suppressing the temperature fluctuation of the steady phase error ΔΦ of the PLL circuit. In FIG. 3, the PLL circuit is in a locked state regardless of the presence or absence of the control.

制御なしの場合、１）図３よりＰＬＬ回路の定常位相誤差ΔΦは環境温度の上昇に伴い増加すること、２）図２よりＰＬＬ回路の定常位相誤差ΔΦの増加はＶＣＯ発振周波数を上昇させることより、３）ＶＣＯ単体の発振周波数が環境温度の上昇に伴い低下すること、４）ＰＬＬ回路がＶＣＯ発振周波数を上昇させるためにＰＬＬ回路の定常位相誤差ΔΦを増加させることがわかる。 In the case of no control, 1) the steady phase error ΔΦ of the PLL circuit increases as the environmental temperature increases from FIG. 3, and 2) the increase of the steady phase error ΔΦ of the PLL circuit increases the VCO oscillation frequency from FIG. 3) It can be seen that the oscillation frequency of the single VCO decreases as the environmental temperature increases, and 4) that the PLL circuit increases the steady phase error ΔΦ of the PLL circuit in order to increase the VCO oscillation frequency.

一方、制御ありの場合、ＰＬＬ回路の定常位相誤差ΔΦが環境温度の変化に係わらず一定となるように、ＶＣＯ発振周波数オフセット制御端子８の電圧は制御される。
以上より、ＰＬＬ回路の定常位相誤差ΔΦを検出し、ＶＣＯ発振周波数オフセット制御端子８の電圧を制御することで、ＰＬＬ回路の出力クロックの位相変動は抑圧可能となる。 On the other hand, in the case of control, the voltage at the VCO oscillation frequency offset control terminal 8 is controlled so that the steady phase error ΔΦ of the PLL circuit is constant regardless of the change in the environmental temperature.
As described above, the phase fluctuation of the output clock of the PLL circuit can be suppressed by detecting the steady phase error ΔΦ of the PLL circuit and controlling the voltage of the VCO oscillation frequency offset control terminal 8.

図４は、定常位相誤差検出手段５およびＶＣＯ発振周波数オフセット制御手段６の構成を示すブロック図である。定常位相誤差検出手段５は、ＰＬＬ回路の定常位相誤差ΔΦを所定の利得分だけ増幅する差動増幅器１１である。また、ＶＣＯ発振周波数オフセット制御手段６は加算器１２により、前記差動増幅器１１の出力信号にＤＣ信号源１３からのＤＣ信号を加算・減算する。 FIG. 4 is a block diagram showing the configuration of the stationary phase error detection means 5 and the VCO oscillation frequency offset control means 6. The stationary phase error detection means 5 is a differential amplifier 11 that amplifies the stationary phase error ΔΦ of the PLL circuit by a predetermined gain. The VCO oscillation frequency offset control means 6 adds / subtracts the DC signal from the DC signal source 13 to the output signal of the differential amplifier 11 by the adder 12.

このように、この発明の実施の形態１に係るＰＬＬ回路は、定常位相誤差を簡単なアナログ回路で検出し、その検出信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を可能とする。 As described above, the PLL circuit according to the first embodiment of the present invention detects the stationary phase error with a simple analog circuit, and controls the offset of the VCO oscillation frequency according to the detection signal, so that the phase of the output clock of the PLL circuit is Enables fluctuation suppression.

実施の形態２．
この発明の実施の形態２に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子のみを有する第二のＶＣＯと、発振周波数が周囲温度の変化に対し安定である基準クロック源との周波数比較により検出し、その検出信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で行うものである。 Embodiment 2. FIG.
The PLL circuit according to the second embodiment of the present invention has a stationary phase error, a frequency of a second VCO having only a VCO oscillation frequency control terminal, and a reference clock source whose oscillation frequency is stable against changes in ambient temperature. By detecting the comparison and performing offset control of the VCO oscillation frequency according to the detection signal, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

図５は、この発明の実施の形態２に係るＰＬＬ回路の構成を示すブロック図であり、差動回路から構成されている。
図５に示すＰＬＬ回路は、入力信号と第一のＶＣＯ出力クロックの位相差を検出する位相比較手段２と、位相比較手段２の出力に含まれる低周波数成分のみを通過させるＬＰＦ３と、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有する第一のＶＣＯ４と、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、第二のＶＣＯ１５のＶＣＯ発振周波数制御端子７に固定電圧を与えるＤＣ信号源２０と、発振周波数が周囲温度の変化に対し安定である基準クロック源１６と、ＶＣＯ１５の出力クロックと基準クロック源１６の出力クロックとの周波数比較を行う周波数比較手段１８と、周波数比較手段１８の出力に従い発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段６とを備えている。尚、ＶＣＯ４の回路とＶＣＯ１５の回路との差はＶＣＯ発振周波数オフセット制御端子８の有無のみである。また、図５において、１は入力信号端子を示す。 FIG. 5 is a block diagram showing the configuration of the PLL circuit according to the second embodiment of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 5 includes a phase comparison unit 2 that detects a phase difference between an input signal and a first VCO output clock, an LPF 3 that passes only a low frequency component included in the output of the phase comparison unit 2, and a VCO oscillation. A fixed voltage is applied to the first VCO 4 having the frequency control terminal 7 and the VCO oscillation frequency offset control terminal 8, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and the VCO oscillation frequency control terminal 7 of the second VCO 15. A DC signal source 20 to be applied, a reference clock source 16 whose oscillation frequency is stable against changes in ambient temperature, frequency comparison means 18 for comparing the frequency of the output clock of the VCO 15 and the output clock of the reference clock source 16, and a frequency VCO oscillation frequency offset control means 6 for generating an oscillation frequency offset control voltage according to the output of the comparison means 18; It is provided. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 5, reference numeral 1 denotes an input signal terminal.

次に、動作について説明する。入力信号端子１からの入力信号は位相比較手段２に入力される。位相比較手段２は、入力信号とＶＣＯ４の出力クロックの位相比較を行い、位相の進み或いは遅れに相当する信号をＬＰＦ３に出力する。ＬＰＦ３は、位相比較手段２の出力信号に含まれる低周波数成分のみ通過させる。ＬＰＦ３の出力はＰＬＬ回路の定常位相誤差ΔΦであり、ＰＬＬ回路の定常位相誤差ΔΦは第一のＶＣＯ４のＶＣＯ発振周波数制御端子７に入力される。 Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means 2. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and the steady phase error ΔΦ of the PLL circuit is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

一方、ＶＣＯ１５のＶＣＯ発振周波数制御端子７にはＤＣ信号源２０より固定電圧が与えられるため、ＶＣＯ１５の発振周波数は環境温度に従い変化する。そのため、ＶＣＯ１５は温度計として用いられる。周波数比較手段１８は、ＶＣＯ１５の周波数と、基準クロック源１６の周波数とを比較することにより、ＰＬＬ回路の定常位相誤差ΔΦを推定する。ＶＣＯ発振周波数オフセット制御手段６は、周波数比較手段１８の出力にＤＣ信号を加算・減算し、ＶＣＯ４のＶＣＯ発振周波数オフセット制御端子８に出力する。ＶＣＯ４は、ＬＰＦ３の出力およびＶＣＯ発振周波数オフセット制御手段６の出力を入力とし、それらの入力に相当する位相および周波数で発振する。ＶＣＯ４の出力クロックは位相比較手段２に入力される。 On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates the steady phase error ΔΦ of the PLL circuit by comparing the frequency of the VCO 15 and the frequency of the reference clock source 16. The VCO oscillation frequency offset control means 6 adds / subtracts a DC signal to / from the output of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 as inputs, and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

なお、周波数比較手段１８は周波数比較を行うもので、例えば、周波数カウンター或いは周波数比較器などでも良い。 The frequency comparison means 18 performs frequency comparison, and may be a frequency counter or a frequency comparator, for example.

このように、この発明の実施の形態２に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、発振周波数が周囲温度の変化に対し安定である基準クロック源１６との周波数比較により推定し、前記推定信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で可能とする。 As described above, the PLL circuit according to the second embodiment of the present invention has a steady phase error, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and a reference whose oscillation frequency is stable with respect to changes in the ambient temperature. By estimating the frequency with the clock source 16 and performing offset control of the VCO oscillation frequency according to the estimated signal, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit with a small-scale control circuit.

実施の形態３．
この発明の実施の形態３に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子およびＶＣＯ発振周波数オフセット制御端子を有する第一のＶＣＯと、ＶＣＯ発振周波数制御端子のみを有する第二のＶＣＯとの周波数比較により推定し、前記検出信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で行うものである。 Embodiment 3 FIG.
In the PLL circuit according to the third embodiment of the present invention, the stationary phase error is determined by using the first VCO having the VCO oscillation frequency control terminal and the VCO oscillation frequency offset control terminal, and the second VCO having only the VCO oscillation frequency control terminal. The phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit by offset control of the VCO oscillation frequency according to the detection signal.

図６は、この発明の実施の形態３に係るＰＬＬ回路の構成を示すブロック図であり、差動回路から構成されている。
図６に示すＰＬＬ回路は、入力信号と分岐手段１７の出力クロックの位相差を検出する位相比較手段２と、位相比較手段２の出力に含まれる低周波数成分のみを通過させるＬＰＦ３と、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有する第一のＶＣＯ４と、ＶＣＯ４の出力を２分岐する分岐手段１７と、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、第二のＶＣＯ１５のＶＣＯ発振周波数制御端子７に固定電圧を与えるＤＣ信号源２０と、ＶＣＯ１５の出力クロックと分岐手段１７の出力クロックとの発振周波数の比較を行う周波数比較手段１８と、周波数比較手段１８の出力に従い発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段６とを備えている。尚、ＶＣＯ４の回路とＶＣＯ１５の回路との差はＶＣＯ発振周波数オフセット制御端子８の有無のみである。また、図６において、１は入力信号端子を示す。 FIG. 6 is a block diagram showing a configuration of a PLL circuit according to Embodiment 3 of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 6 includes a phase comparison unit 2 that detects the phase difference between the input signal and the output clock of the branching unit 17, an LPF 3 that passes only a low frequency component contained in the output of the phase comparison unit 2, and a VCO oscillation A first VCO 4 having a frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, a branching means 17 for bifurcating the output of the VCO 4, a second VCO 15 having only the VCO oscillation frequency control terminal 7, and a second The DC signal source 20 that applies a fixed voltage to the VCO oscillation frequency control terminal 7 of the VCO 15, the frequency comparison means 18 that compares the oscillation frequency of the output clock of the VCO 15 and the output clock of the branch means 17, and the output of the frequency comparison means 18 VCO oscillation frequency offset control means 6 for generating an oscillation frequency offset control voltage according to the above. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 6, reference numeral 1 denotes an input signal terminal.

次に、動作について説明する。入力信号端子１からの入力信号は位相比較手段２に入力される。ＶＣＯ４の出力クロックは分岐手段１７で２分岐された後、位相比較手段２と周波数比較手段１８に入力される。位相比較手段２は、入力信号と分岐手段１７の出力との位相比較を行い、位相の進み或いは遅れに相当する信号をＬＰＦ３に出力する。ＬＰＦ３は、位相比較手段の出力に含まれる低周波数成分のみ通過させる。ＬＰＦ３の出力はＰＬＬ回路の定常位相誤差ΔΦであり、ΔΦは第一のＶＣＯ４のＶＣＯ発振周波数制御端子７に入力される。 Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The output clock of the VCO 4 is branched into two by the branching unit 17 and then input to the phase comparison unit 2 and the frequency comparison unit 18. The phase comparison unit 2 performs phase comparison between the input signal and the output of the branching unit 17 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

一方、ＶＣＯ１５のＶＣＯ発振周波数制御端子７にはＤＣ信号源２０より固定電圧が与えられるため、ＶＣＯ１５の発振周波数は環境温度に従い変化する。そのため、ＶＣＯ１５は温度計として用いられる。周波数比較手段１８はＶＣＯ１５の周波数と、分岐手段１７の周波数とを比較することにより、ΔΦを推定する。ＶＣＯ発振周波数オフセット制御手段６は周波数比較手段１８の出力にＤＣ信号を加算・減算し、ＶＣＯ４のＶＣＯ発振周波数オフセット制御端子８に出力する。ＶＣＯ４はＬＰＦ３の出力信号およびＶＣＯ発振周波数オフセット制御手段６の出力を入力とし、それらの入力に相当する位相および周波数で発振する。 On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates ΔΦ by comparing the frequency of the VCO 15 with the frequency of the branching means 17. The VCO oscillation frequency offset control means 6 adds / subtracts the DC signal to / from the output of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output signal of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs.

このように、この発明の実施の形態３に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有する第一のＶＣＯと、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５との周波数比較により推定し、前記推定信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で可能とする。 As described above, the PLL circuit according to the third embodiment of the present invention has the steady phase error, the first VCO having the VCO oscillation frequency control terminal 7 and the VCO oscillation frequency offset control terminal 8, and the VCO oscillation frequency control terminal 7. Thus, the phase fluctuation of the output clock of the PLL circuit can be suppressed with a small-scale control circuit by estimating the frequency by comparing the frequency with the second VCO 15 having only the frequency and offset-controlling the VCO oscillation frequency according to the estimated signal.

実施の形態４．
この発明の実施の形態４に係るＰＬＬ回路は、定常位相誤差を、分岐手段の出力である入力信号と、ＶＣＯ発振周波数制御端子のみを有する第二のＶＣＯとの周波数比較により推定し、前記検出信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で行うものである。 Embodiment 4 FIG.
The PLL circuit according to the fourth embodiment of the present invention estimates the stationary phase error by frequency comparison between the input signal that is the output of the branching means and the second VCO that has only the VCO oscillation frequency control terminal, and detects the detection result. By performing offset control of the VCO oscillation frequency according to the signal, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

図７はこの発明の実施の形態４に係るＰＬＬ回路の構成を示すブロック図であり、差動回路から構成されている。
図７に示すＰＬＬ回路は、入力信号を２分岐する分岐手段１７と、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有する第一のＶＣＯ４と、分岐手段１７の出力信号と第一のＶＣＯ出力クロックの位相差を検出する位相比較手段２と、位相比較手段２の出力に含まれる低周波数成分のみを通過させるＬＰＦ３と、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、第二のＶＣＯ１５のＶＣＯ発振周波数制御端子７に固定電圧を与えるＤＣ信号源２０と、ＶＣＯ１５の出力クロックと、分岐手段１７の出力である入力信号との周波数比較により定常位相誤差を推定する周波数比較手段１８と、周波数比較手段１８の出力に従い発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段６とを備えている。尚、ＶＣＯ４の回路とＶＣＯ１５の回路との差はＶＣＯ発振周波数オフセット制御端子８の有無のみである。また、図７において、１は入力信号端子を示す。 FIG. 7 is a block diagram showing a configuration of a PLL circuit according to Embodiment 4 of the present invention, which is constituted by a differential circuit.
The PLL circuit shown in FIG. 7 includes a branching means 17 for branching an input signal into two, a first VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, an output signal from the branching means 17 and a first signal. A phase comparison unit 2 that detects a phase difference between the VCO output clocks of the VCO, an LPF 3 that passes only a low-frequency component included in the output of the phase comparison unit 2, a second VCO 15 that has only a VCO oscillation frequency control terminal 7, Frequency comparison for estimating a stationary phase error by comparing the frequency of the DC signal source 20 that applies a fixed voltage to the VCO oscillation frequency control terminal 7 of the second VCO 15, the output clock of the VCO 15, and the input signal that is the output of the branching means 17. Means 18 and a VCO oscillation frequency offset control for generating an oscillation frequency offset control voltage according to the output of frequency comparison means 18. And a means 6. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 7, reference numeral 1 denotes an input signal terminal.

次に、動作について説明する。入力信号端子１からの入力信号は分岐手段１７で２分岐され、位相比較手段２と周波数比較手段１８に入力される。位相比較手段２はＶＣＯ４と分岐手段１７の出力との位相比較を行い、位相の進み或いは遅れに相当する信号をＬＰＦ３に出力する。ＬＰＦ３は位相比較手段の出力信号に含まれる低周波数成分のみ通過させる。ＬＰＦ３の出力はＰＬＬ回路の定常位相誤差ΔΦであり、ΔΦは第一のＶＣＯ４のＶＣＯ発振周波数制御端子７に入力される。 Next, the operation will be described. An input signal from the input signal terminal 1 is branched into two by the branching means 17 and input to the phase comparison means 2 and the frequency comparison means 18. The phase comparison means 2 performs a phase comparison between the VCO 4 and the output of the branching means 17 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

一方、ＶＣＯ１５のＶＣＯ発振周波数制御端子７にはＤＣ信号源２０より固定電圧が与えられるため、ＶＣＯ１５の発振周波数は環境温度に従い変化する。そのため、ＶＣＯ１５は温度計として用いられる。周波数比較手段１８はＶＣＯ１５の出力クロックと、分岐手段１７の出力である入力信号との周波数比較により、ΔΦを推定する。ＶＣＯ発振周波数オフセット制御手段６は周波数比較手段１８の出力信号にＤＣ信号を加算・減算し、ＶＣＯ４のＶＣＯ発振周波数オフセット制御端子８に出力する。ＶＣＯ４はＬＰＦ３の出力およびＶＣＯ発振周波数オフセット制御手段６の出力を入力とし、それらの入力に相当する位相および周波数で発振する。ＶＣＯ４の出力クロックは位相比較手段２に入力される。 On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The frequency comparison means 18 estimates ΔΦ by frequency comparison between the output clock of the VCO 15 and the input signal that is the output of the branch means 17. The VCO oscillation frequency offset control means 6 adds / subtracts a DC signal to the output signal of the frequency comparison means 18 and outputs the result to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

なお、ＶＣＯ発振周波数偏差検出手段５は周波数比較を行うもので、例えば、周波数比較器などでも良い。 The VCO oscillation frequency deviation detecting means 5 performs frequency comparison, and may be, for example, a frequency comparator.

このように、この発明の実施の形態４に係るＰＬＬ回路は、定常位相誤差を、分岐手段１７の出力である入力信号と、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、を周波数比較により推定し、前記推定信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で可能とする。 As described above, the PLL circuit according to the fourth embodiment of the present invention uses the stationary phase error as the frequency of the input signal that is the output of the branching means 17 and the second VCO 15 that has only the VCO oscillation frequency control terminal 7. By estimating the comparison and performing offset control of the VCO oscillation frequency in accordance with the estimated signal, the phase fluctuation of the output clock of the PLL circuit can be suppressed by a small-scale control circuit.

実施の形態５．
この発明の実施の形態５に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子のみを有する第二のＶＣＯと、電気スペクトルモニタ手段と、により推定し、前記推定信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で行うものである。 Embodiment 5. FIG.
In the PLL circuit according to the fifth embodiment of the present invention, the steady phase error is estimated by the second VCO having only the VCO oscillation frequency control terminal and the electric spectrum monitoring means, and the VCO oscillation frequency is determined according to the estimated signal. By performing offset control, the phase fluctuation of the output clock of the PLL circuit is suppressed by a small-scale control circuit.

図８はこの発明の実施の形態５に係るＰＬＬ回路の構成を示すブロック図であり、差動回路から構成されている。
図８に示すＰＬＬ回路は、ＶＣＯ発振周波数制御端子７およびＶＣＯ発振周波数オフセット制御端子８を有する第一のＶＣＯ４と、入力信号と第一のＶＣＯ出力クロックの位相差を検出する位相比較手段２と、位相比較手段２の出力に含まれる低周波数成分のみを通過させるＬＰＦ３と、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、第二のＶＣＯ１５のＶＣＯ発振周波数制御端子７に固定電圧を与えるＤＣ信号源２０と、ＶＣＯ１５の出力スペクトルをモニタすることで定常位相誤差を推定する電気スペクトルモニタ手段１９と、電気スペクトルモニタ手段１９の出力に従い発振周波数オフセット制御電圧を生成するＶＣＯ発振周波数オフセット制御手段６とを備えている。尚、ＶＣＯ４の回路とＶＣＯ１５の回路との差はＶＣＯ発振周波数オフセット制御端子８の有無のみである。また、図８において、１は入力信号端子を示す。 FIG. 8 is a block diagram showing the configuration of the PLL circuit according to the fifth embodiment of the present invention, which is composed of a differential circuit.
The PLL circuit shown in FIG. 8 includes a first VCO 4 having a VCO oscillation frequency control terminal 7 and a VCO oscillation frequency offset control terminal 8, and phase comparison means 2 for detecting the phase difference between the input signal and the first VCO output clock. A fixed voltage is applied to the LPF 3 that passes only the low frequency component included in the output of the phase comparison means 2, the second VCO 15 having only the VCO oscillation frequency control terminal 7, and the VCO oscillation frequency control terminal 7 of the second VCO 15. DC signal source 20 to be applied, electric spectrum monitor means 19 for estimating the steady phase error by monitoring the output spectrum of the VCO 15, and VCO oscillation frequency offset control for generating an oscillation frequency offset control voltage according to the output of the electric spectrum monitor means 19 Means 6 are provided. The difference between the VCO 4 circuit and the VCO 15 circuit is only the presence or absence of the VCO oscillation frequency offset control terminal 8. In FIG. 8, 1 indicates an input signal terminal.

次に、動作について説明する。入力信号端子１からの入力信号は位相比較手段２に入力される。位相比較手段２は入力信号とＶＣＯ４の出力クロックの位相比較を行い、位相の進み或いは遅れに相当する信号をＬＰＦ３に出力する。ＬＰＦ３は位相比較手段の出力信号に含まれる低周波数成分のみ通過させる。ＬＰＦ３の出力はＰＬＬ回路の定常位相誤差ΔΦであり、ΔΦは第一のＶＣＯ４のＶＣＯ発振周波数制御端子７に入力される。 Next, the operation will be described. An input signal from the input signal terminal 1 is input to the phase comparison means 2. The phase comparison means 2 compares the phase of the input signal and the output clock of the VCO 4 and outputs a signal corresponding to the phase advance or delay to the LPF 3. The LPF 3 passes only low frequency components included in the output signal of the phase comparison means. The output of the LPF 3 is a steady phase error ΔΦ of the PLL circuit, and ΔΦ is input to the VCO oscillation frequency control terminal 7 of the first VCO 4.

一方、ＶＣＯ１５のＶＣＯ発振周波数制御端子７にはＤＣ信号源２０より固定電圧が与えられるため、ＶＣＯ１５の発振周波数は環境温度に従い変化する。そのため、ＶＣＯ１５は温度計として用いられる。電気スペクトルモニタ手段１９はＶＣＯ１５の出力スペクトルをモニタすることにより、ΔΦを推定する。ＶＣＯ発振周波数オフセット制御手段６は電気スペクトルモニタ手段１９の出力信号にＤＣ信号を演算し、ＶＣＯ４のＶＣＯ発振周波数オフセット制御端子８に出力する。ＶＣＯ４はＬＰＦ３の出力およびＶＣＯ発振周波数オフセット制御手段６の出力を入力とし、それらの入力に相当する位相および周波数で発振する。ＶＣＯ４の出力クロックは位相比較手段２に入力される。 On the other hand, since a fixed voltage is applied to the VCO oscillation frequency control terminal 7 of the VCO 15 from the DC signal source 20, the oscillation frequency of the VCO 15 changes according to the environmental temperature. Therefore, the VCO 15 is used as a thermometer. The electrical spectrum monitoring means 19 estimates ΔΦ by monitoring the output spectrum of the VCO 15. The VCO oscillation frequency offset control means 6 calculates a DC signal from the output signal of the electric spectrum monitor means 19 and outputs it to the VCO oscillation frequency offset control terminal 8 of the VCO 4. The VCO 4 receives the output of the LPF 3 and the output of the VCO oscillation frequency offset control means 6 and oscillates at a phase and frequency corresponding to those inputs. The output clock of the VCO 4 is input to the phase comparison means 2.

このように、この発明の実施の形態５に係るＰＬＬ回路は、定常位相誤差を、ＶＣＯ発振周波数制御端子７のみを有する第二のＶＣＯ１５と、電気スペクトルモニタ手段１９により推定し、前記推定信号に従いＶＣＯ発振周波数をオフセット制御することで、ＰＬＬ回路の出力クロックの位相変動抑圧を小規模な制御回路で可能とする。 As described above, the PLL circuit according to the fifth embodiment of the present invention estimates the stationary phase error by the second VCO 15 having only the VCO oscillation frequency control terminal 7 and the electric spectrum monitor means 19, and according to the estimated signal. By performing offset control of the VCO oscillation frequency, it is possible to suppress the phase fluctuation of the output clock of the PLL circuit with a small-scale control circuit.

この発明の実施の形態１に係るＰＬＬ回路の構成を示すブロック図である。1 is a block diagram showing a configuration of a PLL circuit according to Embodiment 1 of the present invention. ＶＣＯ単体特性（ＶＣＯ発振周波数とＰＬＬ回路の定常位相誤差ΔΦ）の関係）を示す図である。It is a figure which shows the VCO single-piece | unit characteristic (The relationship between a VCO oscillation frequency and the stationary phase error (DELTA) (PHI) of a PLL circuit). ＰＬＬ回路の定常位相誤差ΔΦと環境温度の関係を示す図である。It is a figure which shows the relationship between stationary phase error (DELTA) (PHI) circuit, and environmental temperature. 定常位相誤差検出手段およびＶＣＯ発振周波数オフセット制御手段の構成を示すブロック図である。It is a block diagram which shows the structure of a stationary phase error detection means and a VCO oscillation frequency offset control means. この発明の実施の形態２に係るＰＬＬ回路の構成を示すブロック図である。It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係るＰＬＬ回路の構成を示すブロック図である。It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 3 of this invention. この発明の実施の形態４に係るＰＬＬ回路の構成を示すブロック図である。It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 4 of this invention. この発明の実施の形態５に係るＰＬＬ回路の構成を示すブロック図である。It is a block diagram which shows the structure of the PLL circuit which concerns on Embodiment 5 of this invention.

Explanation of symbols

１入力信号端子、２位相比較手段、３ＬＰＦ（low Pass Filter）、４ＶＣＯ（Voltage Controlled Oscillator）、５定常位相誤差検出手段、６ＶＣＯ発振周波数オフセット制御手段、７ＶＣＯ発振周波数制御端子、８ＶＣＯ発振周波数オフセット制御端子、１１差動増幅器、１２加算器、１３ＤＣ信号源、１５ＶＣＯ、１６基準クロック源、１７分岐手段、１８周波数比較手段、１９電気スペクトルモニタ手段、２０ＤＣ信号源。 1 input signal terminal, 2 phase comparison means, 3 LPF (low pass filter), 4 VCO (Voltage Controlled Oscillator), 5 stationary phase error detection means, 6 VCO oscillation frequency offset control means, 7 VCO oscillation frequency control terminal, 8 VCO Oscillation frequency offset control terminal, 11 differential amplifier, 12 adder, 13 DC signal source, 15 VCO, 16 reference clock source, 17 branching means, 18 frequency comparison means, 19 electrical spectrum monitoring means, 20 DC signal source.

Claims

In the PLL circuit that suppresses the phase variation of the output clock,
Phase comparison means for detecting a phase difference between the input signal and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A reference clock source whose oscillation frequency is stable against changes in ambient temperature,
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between the output clock of the reference clock source and the output clock of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means.

In the PLL circuit that suppresses the phase variation of the output clock,
Branching means for taking the output clock of the first VCO as an input and bifurcating the clock;
Phase comparison means for detecting a phase difference between the input signal and the output clock of the branch means;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between the output clock of the second VCO and the output clock of the branch means;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means.

The PLL circuit according to claim 1 or 2 ,
The PLL circuit according to claim 1, wherein the frequency comparison means is constituted by a frequency counter or a frequency comparator.

In the PLL circuit that suppresses the phase variation of the output clock,
Branching means for branching the input signal into two;
Phase comparison means for detecting a phase difference between the output signal of the branch means and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Frequency comparison means for detecting a frequency difference between the output signal of the branch means and the output clock of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the frequency comparison means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means.

In the PLL circuit that suppresses the phase variation of the output clock,
Phase comparison means for detecting a phase difference between the input signal and the output clock of the first VCO;
An LPF that receives only the low-frequency component using the output of the phase comparison means as an input; and
A DC signal source;
A second VCO having a VCO oscillation frequency control terminal that receives the output of the DC signal source;
Electrical spectrum monitoring means for detecting the oscillation frequency of the second VCO;
VCO oscillation frequency offset control means for generating a VCO oscillation frequency offset control voltage using the output of the electric spectrum monitor means as an input;
A PLL circuit comprising: a VCO oscillation frequency control terminal that receives the output of the LPF; and a first VCO that has a VCO oscillation frequency offset control terminal that receives the output of the VCO oscillation frequency offset control means.