JPH05227019A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH05227019A JPH05227019A JP4027037A JP2703792A JPH05227019A JP H05227019 A JPH05227019 A JP H05227019A JP 4027037 A JP4027037 A JP 4027037A JP 2703792 A JP2703792 A JP 2703792A JP H05227019 A JPH05227019 A JP H05227019A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- oscillator
- outputs
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＰＬＬ（フェーズ・ロ
ック・ループ）回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase lock loop) circuit.
【０００２】[0002]
【従来の技術】伝送通信装置などに用いられる従来のＰ
ＬＬ回路の一例を図２に示す。この回路は、制御信号の
電圧に応じた周波数の信号を出力する電圧制御発振器
（ＶＣＯ）１と、２つの信号の位相差を検出するエクス
クルーシブ・オア回路からなる位相検出器３と、位相検
出器３の出力信号の低周波成分を取り出すローパスフィ
ルタ（ＬＰＦ）４と、ローパスフィルタ４の出力信号を
増幅し、電圧制御発振器１に制御信号として出力する増
幅器（ＡＭＰ）５と、入力信号および発振器１の出力信
号をそれぞれ１／Ｎ（ただし、Ｎは整数）に分周し、位
相検出器３に出力する分周器６を備えている。2. Description of the Related Art A conventional P used in a transmission communication device or the like.
An example of the LL circuit is shown in FIG. This circuit includes a voltage controlled oscillator (VCO) 1 that outputs a signal having a frequency corresponding to the voltage of a control signal, a phase detector 3 that includes an exclusive OR circuit that detects a phase difference between two signals, and a phase detector. 3 is a low-pass filter (LPF) 4 for extracting low-frequency components of the output signal, an amplifier (AMP) 5 for amplifying the output signal of the low-pass filter 4 and outputting it as a control signal to the voltage controlled oscillator 1, the input signal and the oscillator 1. Each of the output signals of 1 is divided into 1 / N (where N is an integer), and a frequency divider 6 for outputting to the phase detector 3 is provided.
【０００３】このような構成において、分周器６は、周
波数ｆi の入力信号および発振器１からの周波数ｆ0 の
信号を１／Ｎに分周し、各信号の周波数をそれぞれｆi
／Ｎ，ｆ0 ／Ｎにして位相検出器３に出力する。位相検
出器３はこれら２つの信号の位相差を検出し、検出結果
を表す信号ｆEXを出力する。ローパスフィルタ４はその
信号ｆEXから低周波成分を取り出し、信号ｆLPF を出力
する。増幅器５はローパスフィルタ４の出力信号ｆLPF
を増幅し、発振器１に出力する。発振器１は増幅器５か
らの信号の電圧に応じた周波数の信号を分周器６に出力
する。その結果、発振器１の出力信号は、その位相が入
力信号の位相に一致したものとなる。In such a configuration, the frequency divider 6 divides the input signal of the frequency f i and the signal of the frequency f 0 from the oscillator 1 into 1 / N, and the frequency of each signal is f i.
/ N, f 0 / N and output to the phase detector 3. The phase detector 3 detects the phase difference between these two signals and outputs a signal f EX representing the detection result. The low pass filter 4 extracts low frequency components from the signal f EX and outputs a signal f LPF . The amplifier 5 is the output signal f LPF of the low-pass filter 4.
Is amplified and output to the oscillator 1. The oscillator 1 outputs a signal having a frequency corresponding to the voltage of the signal from the amplifier 5 to the frequency divider 6. As a result, the phase of the output signal of the oscillator 1 matches the phase of the input signal.
【０００４】[0004]
【発明が解決しようとする課題】しかし、このような従
来のＰＬＬ回路では、発振器１の発振周波数対入力制御
電圧の特性（すなわちｆ−Ｖ特性）にバラツキがあった
場合、ＰＬＬ回路のループゲインの補正は、増幅器５の
増幅度を変更するか、またはローパスフィルタ４の定数
を変えてカットオフ周波数を変化させることによってし
か行えず、そのため、個々の電圧制御発振器１のｆ−Ｖ
特性のバラツキに対して、ＰＬＬ回路のループゲインを
それぞれ補正することは困難であった。However, in such a conventional PLL circuit, when there is a variation in the characteristic of the oscillation frequency of the oscillator 1 versus the input control voltage (that is, f-V characteristic), the loop gain of the PLL circuit is increased. Can be corrected only by changing the amplification degree of the amplifier 5 or changing the constant of the low-pass filter 4 to change the cut-off frequency. Therefore, f-V of each voltage-controlled oscillator 1 can be corrected.
It was difficult to correct the loop gain of the PLL circuit for each characteristic variation.
【０００５】本発明の目的は、このような問題を解決
し、ループゲインを容易に補正できるＰＬＬ回路を提供
することにある。An object of the present invention is to solve such a problem and to provide a PLL circuit which can easily correct the loop gain.
【０００６】[0006]
【課題を解決するための手段】本発明は、制御信号の電
圧に応じた周波数の信号を出力する電圧制御発振器と、
第１および第２の信号の位相差を検出する位相検出器
と、この位相検出器の出力信号を入力信号とするローパ
スフィルタと、このローパスフィルタの出力信号を増幅
し、前記電圧制御発振器に前記制御信号として出力する
増幅器とを備えたＰＬＬ回路において、入力信号を任意
の分周比で分周し、前記第１の信号として前記位相検出
器に出力する第１の分周回路と、前記電圧制御発振器の
出力信号を任意の分周比で分周し、前記第２の信号とし
て前記位相検出器に出力する第２の分周回路とを備えた
ことを特徴とする。The present invention provides a voltage controlled oscillator for outputting a signal having a frequency corresponding to the voltage of a control signal,
A phase detector that detects the phase difference between the first and second signals, a low-pass filter that uses the output signal of this phase detector as an input signal, and an output signal of this low-pass filter that is amplified by the voltage-controlled oscillator. In a PLL circuit including an amplifier that outputs as a control signal, a first frequency dividing circuit that divides an input signal with an arbitrary frequency dividing ratio and outputs the first signal to the phase detector as the first signal, and the voltage. A second frequency divider circuit for dividing the output signal of the controlled oscillator by an arbitrary frequency division ratio and outputting it as the second signal to the phase detector is provided.
【０００７】[0007]
【実施例】次に本発明の実施例について図面を参照して
説明する。図１に本発明によるＰＬＬ回路の一例を示
す。この回路は、制御信号の電圧に応じた周波数の信号
を出力する電圧制御発振器（ＶＣＯ）１と、２つの信号
の位相差を検出するエクスクルーシブ・オア回路からな
る位相検出器３と、位相検出器３の出力信号の低周波成
分を取り出すローパスフィルタ（ＬＰＦ）４と、ローパ
スフィルタ４の出力信号を増幅し、電圧制御発振器１に
制御信号として出力する増幅器（ＡＭＰ）５と、入力信
号および発振器１の出力信号をそれぞれ１／Ｎ1 ，１／
Ｎ2 ，１／Ｎ3など任意の分周比で（ただし、Ｎ1 ，Ｎ
2 ，Ｎ3 は整数）分周し、位相検出器３に出力する分周
器２を備えている。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a PLL circuit according to the present invention. This circuit includes a voltage controlled oscillator (VCO) 1 that outputs a signal having a frequency corresponding to the voltage of a control signal, a phase detector 3 that includes an exclusive OR circuit that detects a phase difference between two signals, and a phase detector. 3 is a low-pass filter (LPF) 4 for extracting low-frequency components of the output signal, an amplifier (AMP) 5 for amplifying the output signal of the low-pass filter 4 and outputting it as a control signal to the voltage controlled oscillator 1, the input signal and the oscillator 1. Output signals of 1 / N 1 and 1 /
N 2, 1 / N 3 Any frequency division ratio such (where, N 1, N
2 and N 3 are integers) and are provided with a frequency divider 2 which outputs the frequency to a phase detector 3.
【０００８】次に動作を説明する。分周器２は、周波数
ｆi の入力信号および発振器１からの周波数ｆ0 の信号
を分周比選択制御信号により指定された分周比で分周
し、分周結果をそれぞれ位相検出器３に出力する。位相
検出器３はこれら２つの信号の位相差を検出し、検出結
果を表す信号ｆEXを出力する。ローパスフィルタ４はそ
の信号ｆEXから低周波成分を取り出し、信号ｆLPF を出
力する。増幅器５はローパスフィルタ４の出力信号ｆ
LPF を増幅し、発振器１に出力する。発振器１は増幅器
５からの信号の電圧に応じた周波数の信号を分周器６に
出力する。その結果、発振器１の出力信号は、その位相
が入力信号の位相に一致したものとなる。Next, the operation will be described. The frequency divider 2 frequency-divides the input signal of the frequency f i and the signal of the frequency f 0 from the oscillator 1 by the frequency division ratio designated by the frequency division ratio selection control signal, and outputs the frequency division results to the phase detector 3 respectively. Output to. The phase detector 3 detects the phase difference between these two signals and outputs a signal f EX representing the detection result. The low pass filter 4 extracts low frequency components from the signal f EX and outputs a signal f LPF . The amplifier 5 outputs the output signal f of the low-pass filter 4.
LPF is amplified and output to oscillator 1. The oscillator 1 outputs a signal having a frequency corresponding to the voltage of the signal from the amplifier 5 to the frequency divider 6. As a result, the phase of the output signal of the oscillator 1 matches the phase of the input signal.
【０００９】そして、このＰＬＬ回路では、分周器２の
分周比は、分周選択制御信号によって任意に設定できる
ので、電圧制御発振器１に特性のバラツキがあっても、
発振器１の特性に応じて分周器２の分周比を変えること
により、容易にＰＬＬ回路のループゲインを補正するこ
とができる。In this PLL circuit, the frequency division ratio of the frequency divider 2 can be arbitrarily set by the frequency division selection control signal. Therefore, even if the voltage controlled oscillator 1 has characteristic variations,
By changing the frequency division ratio of the frequency divider 2 according to the characteristics of the oscillator 1, the loop gain of the PLL circuit can be easily corrected.
【００１０】図２に、分周器２の分周比を変えた場合、
ローパスフィルタ４の出力信号ｆLPF の電圧Ｖavg と、
入力信号ｆi および信号ｆ0 の位相差φの関係を示す。
図中、横軸は位相差φを表し、縦軸は電圧Ｖavg を表
す。なお、位相差φは、２つの信号の実際の位相差がπ
／２のとき、φ＝０とした。図から分かるように、分周
比を１／１，１／２，１／４などと切り替えることによ
り、特性の傾きが変化し、位相差φの変化に対する電圧
Ｖavg の変化の度合が変化する。従って、分周比を変え
ることによりループゲインが変り、ループゲインの補正
が可能となる。In FIG. 2, when the frequency division ratio of the frequency divider 2 is changed,
The voltage V avg of the output signal f LPF of the low pass filter 4,
The relationship between the phase difference φ between the input signal f i and the signal f 0 is shown.
In the figure, the horizontal axis represents the phase difference φ and the vertical axis represents the voltage V avg . Note that the phase difference φ is the actual phase difference between the two signals is π
When / 2, φ = 0. As can be seen from the figure, by switching the frequency division ratio to 1/1, 1/2, 1/4, etc., the slope of the characteristic changes and the degree of change of the voltage V avg with respect to the change of the phase difference φ changes. .. Therefore, the loop gain is changed by changing the division ratio, and the loop gain can be corrected.
【００１１】[0011]
【発明の効果】以上説明したように本発明のＰＬＬ回路
は、制御信号の電圧に応じた周波数の信号を出力する電
圧制御発振器と、第１および第２の信号の位相差を検出
する位相検出器と、この位相検出器の出力信号を入力信
号とするローパスフィルタと、このローパスフィルタの
出力信号を増幅し、電圧制御発振器に制御信号として出
力する増幅器とを備えたＰＬＬ回路において、入力信号
を任意の分周比で分周し、第１の信号として位相検出器
に出力する第１の分周回路と、電圧制御発振器の出力信
号を任意の分周比で分周し、第２の信号として位相検出
器に出力する第２の分周回路とを備えたことを特徴とす
る。従って、本発明のＰＬＬ回路では、電圧制御発振器
のｆ−Ｖ特性にバラツキがあっても、第１および第２の
分周器の分周比を変えることにより、ＰＬＬ回路のルー
プゲインを容易に補正することができる。As described above, the PLL circuit of the present invention includes a voltage control oscillator that outputs a signal having a frequency corresponding to the voltage of the control signal and a phase detection that detects the phase difference between the first and second signals. In a PLL circuit that includes a low-pass filter that uses the output signal of the phase detector as an input signal, and an amplifier that amplifies the output signal of the low-pass filter and outputs it to the voltage-controlled oscillator as a control signal. A first frequency divider circuit that divides the signal with an arbitrary frequency division ratio and outputs it as a first signal to the phase detector, and an output signal of the voltage controlled oscillator with an arbitrary frequency division ratio, and outputs the second signal. And a second frequency dividing circuit for outputting to the phase detector. Therefore, in the PLL circuit of the present invention, even if the fV characteristic of the voltage controlled oscillator varies, the loop gain of the PLL circuit can be easily changed by changing the frequency division ratio of the first and second frequency dividers. Can be corrected.
【図１】本発明のＰＬＬ回路の一例を示すブロック図で
ある。FIG. 1 is a block diagram showing an example of a PLL circuit of the present invention.
【図２】図１のＰＬＬ回路を構成するローパスフィルタ
の出力電圧と、入力信号および電圧制御発振器の出力信
号の位相差との関係を示すグラフである。FIG. 2 is a graph showing a relationship between an output voltage of a low pass filter which constitutes the PLL circuit of FIG. 1 and a phase difference between an input signal and an output signal of a voltage controlled oscillator.
【図３】従来のＰＬＬ回路の一例を示すブロック図であ
る。FIG. 3 is a block diagram showing an example of a conventional PLL circuit.
１ 電圧制御発振器（ＶＣＯ） ２ 分周器 ３ 位相検出器 ４ ローパスフィルタ（ＬＰＦ） ５ 増幅器（ＡＭＰ） 1 Voltage controlled oscillator (VCO) 2 Frequency divider 3 Phase detector 4 Low pass filter (LPF) 5 Amplifier (AMP)
Claims (1)
力する電圧制御発振器と、第１および第２の信号の位相
差を検出する位相検出器と、この位相検出器の出力信号
を入力信号とするローパスフィルタと、このローパスフ
ィルタの出力信号を増幅し、前記電圧制御発振器に前記
制御信号として出力する増幅器とを備えたＰＬＬ回路に
おいて、 入力信号を任意の分周比で分周し、前記第１の信号とし
て前記位相検出器に出力する第１の分周回路と、 前記電圧制御発振器の出力信号を任意の分周比で分周
し、前記第２の信号として前記位相検出器に出力する第
２の分周回路とを備えたことを特徴とするＰＬＬ回路。1. A voltage-controlled oscillator that outputs a signal having a frequency corresponding to a voltage of a control signal, a phase detector that detects a phase difference between first and second signals, and an output signal of the phase detector. In a PLL circuit including a low-pass filter as a signal and an amplifier that amplifies an output signal of the low-pass filter and outputs the amplified signal to the voltage controlled oscillator as the control signal, the input signal is frequency-divided by an arbitrary frequency division ratio, A first frequency divider circuit that outputs the first signal to the phase detector, and an output signal of the voltage controlled oscillator that is divided by an arbitrary frequency division ratio to the phase detector as the second signal. A PLL circuit comprising a second frequency dividing circuit for outputting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4027037A JPH05227019A (en) | 1992-02-14 | 1992-02-14 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4027037A JPH05227019A (en) | 1992-02-14 | 1992-02-14 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05227019A true JPH05227019A (en) | 1993-09-03 |
Family
ID=12209875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4027037A Pending JPH05227019A (en) | 1992-02-14 | 1992-02-14 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05227019A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065377A (en) * | 2013-03-21 | 2014-09-24 | 富士通株式会社 | Pll Circuit And Phase Comparison Method In Pll Circuit |
-
1992
- 1992-02-14 JP JP4027037A patent/JPH05227019A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065377A (en) * | 2013-03-21 | 2014-09-24 | 富士通株式会社 | Pll Circuit And Phase Comparison Method In Pll Circuit |
| JP2014187427A (en) * | 2013-03-21 | 2014-10-02 | Fujitsu Ltd | Pll circuit and method for phase comparison in pll circuit |
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