JPS6253081B2 - - Google Patents

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Publication number
JPS6253081B2
JPS6253081B2 JP11205680A JP11205680A JPS6253081B2 JP S6253081 B2 JPS6253081 B2 JP S6253081B2 JP 11205680 A JP11205680 A JP 11205680A JP 11205680 A JP11205680 A JP 11205680A JP S6253081 B2 JPS6253081 B2 JP S6253081B2
Authority
JP
Japan
Prior art keywords
frequency
signal
intermediate frequency
phase
frequency signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11205680A
Other languages
Japanese (ja)
Other versions
JPS5737906A (en
Inventor
Michinori Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KENUTSUDO KK
Original Assignee
KENUTSUDO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KENUTSUDO KK filed Critical KENUTSUDO KK
Priority to JP11205680A priority Critical patent/JPS5737906A/en
Publication of JPS5737906A publication Critical patent/JPS5737906A/en
Publication of JPS6253081B2 publication Critical patent/JPS6253081B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【発明の詳細な説明】 この発明は、フエーズロツクトループ方式によ
つて局部発振周波数を中間周波信号の周波数偏移
に追従させるようになしたFM受信機の改良に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of an FM receiver in which a local oscillation frequency is made to follow the frequency shift of an intermediate frequency signal using a phase lock loop method.

従来、フエーズロツクトループ(以下PLLと略
す)制御系を用いて受信の安定化や再生特性の向
上を図るようにした受信機には種々のものがある
が、第1図はかような方式のFM受信機の一従来
例である。
Conventionally, there are various types of receivers that use phase lock loop (hereinafter abbreviated as PLL) control systems to stabilize reception and improve playback characteristics. This is a conventional example of an FM receiver.

図中、1はアンテナによつて捕捉され高周波増
幅器によつて増幅されたFM高周波信号f1(周
波数はf1)を入力する入力端、2は信号f1と後
記電圧制御局部発振器10より出力される局部発
振周波信号f2(周波数はf2)とを混合して中間
周波信号f(周波数はf=f1−f2)を出力する混
合器、3は中間周波信号の通過帯域幅を定める中
間周波フイルタ、4は中間周波増幅器(リミツタ
付き)、6は中間周波信号fを以下に説明する基
準周波信号はf0との位相のずれを電圧変動分とし
て出力する位相比較器、7は前記中間周波フイル
タの中心周波数を基準周波信号f0(周波数はf0)と
して出力する基準周波数発振器、8はローパスフ
イルタ、9は低周波増幅器、10は前記位相比較
器により復調された復調信号により制御される電
圧制御局部発振器、14は復調信号出力端を夫々
示す。
In the figure, 1 is an input terminal into which an FM high-frequency signal f1 (frequency is f1) captured by an antenna and amplified by a high-frequency amplifier is input, and 2 is a local signal that is output from the signal f1 and a voltage-controlled local oscillator 10 (described later). A mixer that mixes the oscillation frequency signal f2 (frequency is f2) and outputs an intermediate frequency signal f (frequency is f=f1-f2); 3 is an intermediate frequency filter that determines the passband width of the intermediate frequency signal; 4 is an intermediate frequency filter that determines the passband width of the intermediate frequency signal; An intermediate frequency amplifier (with a limiter); 6 is a phase comparator that outputs the intermediate frequency signal f as a reference frequency signal, which will be explained below, as a voltage fluctuation amount by the phase shift from f 0 ; 7 is the center frequency of the intermediate frequency filter; 8 is a low-pass filter, 9 is a low-frequency amplifier, and 10 is a voltage-controlled local oscillator that is controlled by the demodulated signal demodulated by the phase comparator. , 14 indicate demodulated signal output ends, respectively.

この一従来例におけるPLLは、混合器2、中間
周波フイルタ3、中間周波増幅器4、位相比較器
6、ローパスフイルタ8、低周波増幅器9、電圧
制御局部発振器10によつて構成され、FM高周
波信号f1が搬送波のみのときを考えると、中間
周波信号fの周波数と基準周波信号F0の周波数
が同一周波数となるように電圧制御局部発振器1
0を制御するようになつている。また、FM高周
波信号f1の瞬時位相の変化に対する出力端子1
4からの出力電圧の応答を考えると、出力電圧は
FM高周波信号f1の瞬時位相を微分した値、つ
まりFM検波出力の値と、その復調出力の周波数
特性の値の積になつていることがわかる。
The PLL in this one conventional example is composed of a mixer 2, an intermediate frequency filter 3, an intermediate frequency amplifier 4, a phase comparator 6, a low-pass filter 8, a low-frequency amplifier 9, and a voltage-controlled local oscillator 10, and is configured to generate an FM high-frequency signal. Considering the case where f1 is only a carrier wave, the voltage controlled local oscillator 1 is set so that the frequency of the intermediate frequency signal f and the frequency of the reference frequency signal F0 are the same frequency.
It is designed to control 0. In addition, the output terminal 1 responds to changes in the instantaneous phase of the FM high frequency signal f1.
Considering the output voltage response from 4, the output voltage is
It can be seen that this is the product of the value obtained by differentiating the instantaneous phase of the FM high-frequency signal f1, that is, the value of the FM detection output, and the value of the frequency characteristic of its demodulated output.

かような構成においては、FM高周波信号f1
の変調信号周波数が高い程ループ応答速度を速く
し、周波数偏移が大きい程ループ利得を大きくす
る必要があることが知られている。このループ応
答速度は主に中間周波フイルタ3とローパスフイ
ルタ8とによつて決定され、レープ利得は、位相
比較器6、低周波増幅器9及び電圧制御局部発振
器10によつて決定される。(なお、ループ応答
速度はループ利得の大小によつても変化する。) ところで、一般にFM受信機は、大きな選択度
を得るために中間周波フイルタ3に減衰特性の鋭
いものを使用しているから、この中間周波フイル
タ3において中間周波信号fは相当大きな位相回
転を受け、従つてPLLがそれだけ不安定となつて
発振し易くなる。そこでこの発振を防止するため
に、従来はローパスフイルタ8の時定数を大きく
して位相補償を行なつたり、低周波増幅器9の利
得を減少させてループ利得を低下させたりしてい
る。
In such a configuration, the FM high frequency signal f1
It is known that the higher the modulation signal frequency, the faster the loop response speed, and the larger the frequency deviation, the larger the loop gain. The loop response speed is mainly determined by the intermediate frequency filter 3 and the low pass filter 8, and the rape gain is determined by the phase comparator 6, the low frequency amplifier 9, and the voltage controlled local oscillator 10. (Note that the loop response speed also changes depending on the magnitude of the loop gain.) By the way, FM receivers generally use intermediate frequency filters 3 with sharp attenuation characteristics in order to obtain high selectivity. In this intermediate frequency filter 3, the intermediate frequency signal f undergoes a considerably large phase rotation, so that the PLL becomes unstable and becomes more likely to oscillate. In order to prevent this oscillation, conventionally, the time constant of the low-pass filter 8 is increased to perform phase compensation, or the gain of the low-frequency amplifier 9 is decreased to lower the loop gain.

しかしながら、この位相補償をPLL中で行なう
とループ応答速度が著しく低下するため、FM高
周波信号の変調信号周波数の上限が制限を受けて
低下していまい、一方ループ利得が低下させると
FM高周波信号の周波数偏移の幅が制限を受けて
小さくなつてしまう。すなわち、上述の如き従来
構成では、受信選択度の向上という条件と、FM
高周波信号の変調信号周波数の上限拡張及びその
周波数偏移の幅拡大という条件とは互いに矛盾を
生じてしまうのであり、両条件を兼ね備えたFM
受信機を得ることは非常に困難であつた。
However, if this phase compensation is performed in the PLL, the loop response speed will drop significantly, so the upper limit of the modulation signal frequency of the FM high-frequency signal will be limited and will decrease, while the loop gain will decrease.
The width of the frequency deviation of the FM high-frequency signal is limited and becomes small. In other words, in the conventional configuration as described above, the condition of improving reception selectivity and the FM
The conditions of expanding the upper limit of the modulation signal frequency of high-frequency signals and expanding the width of its frequency deviation are contradictory to each other.
Receivers were extremely difficult to obtain.

この発明の目的は、上述の如き従来欠点を解消
したFM受信機を提供することにある。
An object of the present invention is to provide an FM receiver that eliminates the conventional drawbacks as described above.

以下、本発明の第1の実施例につき第2図に基
づいて説明する。
Hereinafter, a first embodiment of the present invention will be explained based on FIG. 2.

図中、第1図と同一の符号を付した処は同一の
構成要素を示し、その説明は省略する。
In the figure, the same reference numerals as in FIG. 1 indicate the same components, and the explanation thereof will be omitted.

5は中間周波増幅器4から出力される増幅され
た中間周波信号f(周波数はf=f1−f2)を1/
nに分周して1/n周波信号Fとする1/n分周
器を示す。なお、基準周波数発振器7は、この回
路では基準周波信号F0(周波数はF0=f0/n)を
出力するようになつていて、位相比較器6は信号
Fと信号F0との位相を比較する構成としてあ
る。
5 is the amplified intermediate frequency signal f (frequency is f=f1-f2) output from the intermediate frequency amplifier 4 by 1/
A 1/n frequency divider that divides the frequency by n to produce a 1/n frequency signal F is shown. In this circuit, the reference frequency oscillator 7 is configured to output a reference frequency signal F 0 (frequency is F 0 = f 0 /n), and the phase comparator 6 is configured to output a reference frequency signal F 0 (frequency is F 0 =f 0 /n), and the phase comparator 6 is configured to output a reference frequency signal F 0 (frequency is F 0 =f 0 /n), and the phase comparator 6 is configured to output a reference frequency signal F 0 (frequency is F 0 =f 0 /n). This is a configuration for comparing.

上述の構成において、中間周波信号fを、 f=cosωt ……(1) とすると、中間周波フイルタ3を通過した信号
f′は、 f′=cos(ωt−θ) ……(2) θ…フイルタ3によつて決まる位相回転分 のように、位相回転を受けた信号となる。更にこ
の信号f′は中間周波増幅器4を通過後1/n分周
器5に入力されて分周され、1/n周波信号Fと
なる。
In the above configuration, if the intermediate frequency signal f is f=cosωt...(1), then the signal passed through the intermediate frequency filter 3
f' becomes a signal that has undergone phase rotation, such as f'=cos(ωt-θ) (2) θ...the phase rotation determined by the filter 3. Further, this signal f' passes through an intermediate frequency amplifier 4 and is input to a 1/n frequency divider 5 where it is frequency-divided to become a 1/n frequency signal F.

F=cos(ωt/n−θ/n) ……(3) すなわち、中間周波信号fは、その周波数が
1/nとなると同時に位相回転分も1/nとなる
のである。従つてPLLの位相余裕が増大し、安定
度も増すこととなる。
F=cos(ωt/n−θ/n) (3) In other words, the frequency of the intermediate frequency signal f becomes 1/n, and at the same time, the phase rotation also becomes 1/n. Therefore, the phase margin of the PLL increases and the stability also increases.

ここに、位相余裕とは開ループ特性のループ利
得がゼロとなる周波数において位相回転分が−π
(rad)に対してどれだけの余裕があるかを示すも
ので、これが−π(rad)以上回転していて、か
つ開ループ利得が1以上あるとその閉ループは発
振してしまう。このを発振を抑えるためには、位
相回転分あるいは開ループ利得もしくはその両者
をできるだけ小さくする。(すなわち位相余裕を
大きくするということである。)これを実際の回
路で行なうには、ローパスフイルタ8の時定数を
なるべく大きくし、低周波増幅器9等の利得を減
少すればよいのであるが、こうすると、ループ応
答速度が著しく遅くなつていまい不都合であるこ
とは前記従来例において説明した通りである。
Here, the phase margin is the phase rotation of −π at the frequency where the loop gain of the open-loop characteristic is zero.
(rad), and if this rotates by more than -π (rad) and the open loop gain is more than 1, the closed loop will oscillate. In order to suppress this oscillation, the phase rotation, the open loop gain, or both should be made as small as possible. (That is, increasing the phase margin.) To do this in an actual circuit, the time constant of the low-pass filter 8 should be made as large as possible and the gain of the low-frequency amplifier 9 etc. should be reduced. If this is done, the loop response speed becomes extremely slow, which is disadvantageous, as explained in the prior art example.

本発明回路の場合、(3)式からその位相余裕を計
算すると−θ/nの−πに対する余裕、すなわち
−θ/n−(−π)=π−θ/nとなる。一方、第
1図に示す従来回路(位相補償を施してない回路
とする。)の場合の位相余裕は、中間周波フイル
タ3を通過して位相回転を受けた信号f′について
考えればよいこから(2)式から−θ−(−π)=π−
θとなる。ここで、π−θ/n>π−θが云える
から、本発明回路の位相余裕は従来回路のそれに
比して増大していることが判る。すなわち、とく
に位相補償を行なわなくとも位相余裕を十分に得
ることができる訳である。従つてループ応答速度
の低下は全くなく、またループ利得は1/n分周
器5において少許低下するだけであるから低周波
増幅器9等でその低下分だけ補つてやればよい。
In the case of the circuit of the present invention, the phase margin calculated from equation (3) is the margin of -θ/n with respect to -π, that is, -θ/n-(-π)=π-θ/n. On the other hand, the phase margin in the case of the conventional circuit shown in FIG. 1 (a circuit without phase compensation) can be determined by considering the signal f' that has passed through the intermediate frequency filter 3 and undergone phase rotation ( 2) From formula, −θ−(−π)=π−
becomes θ. Here, since π-θ/n>π-θ can be said, it can be seen that the phase margin of the circuit of the present invention is increased compared to that of the conventional circuit. In other words, a sufficient phase margin can be obtained without performing any particular phase compensation. Therefore, the loop response speed does not decrease at all, and the loop gain only decreases to a small extent in the 1/n frequency divider 5, so it is sufficient to compensate for the decrease using the low frequency amplifier 9 or the like.

しかして、受信選択度を向上させるべく減衰特
性の鋭い中間周波フイルタを用いたとしても、位
相補償なしで十分な位相余裕が得られることにな
り、ループ応答速度及びループ利得が大きく低下
することはなくなるのである。
Therefore, even if an intermediate frequency filter with a sharp attenuation characteristic is used to improve reception selectivity, sufficient phase margin can be obtained without phase compensation, and the loop response speed and loop gain will not decrease significantly. It will disappear.

なお、1/n分周器5の分周比1/nは位相回
転分θが大きい程小さくしてわれば良いが、分周
後の信号Fの周波数がFM高周波信号f1の変調
信号最大周波数より低くならないように決める必
要がある。
Note that the frequency division ratio 1/n of the 1/n frequency divider 5 can be made smaller as the phase rotation θ increases, but the frequency of the signal F after frequency division is the maximum frequency of the modulation signal of the FM high frequency signal f1. It is necessary to decide so that it does not become lower.

第3図は本発明の第2の実施例を示す。 FIG. 3 shows a second embodiment of the invention.

この例では、前記第1の実施例の構成に乗算器
12及びローパスフイルタ13を設け、1/n分
周器5の出力信号Fと基準周波数発振器7の出力
信号F0とを乗算することよつて復調信号を取り
出すようにしてあるが、基本動作は前記第1の実
施例の位相比較器と同じであり、復調動作だけを
位相比較器6と分け、新たに乗算器12で行なつ
た構成である。
In this example, a multiplier 12 and a low-pass filter 13 are provided in the configuration of the first embodiment, and the output signal F of the 1/n frequency divider 5 and the output signal F 0 of the reference frequency oscillator 7 are multiplied. Although the basic operation is the same as that of the phase comparator of the first embodiment, only the demodulation operation is separated from the phase comparator 6 and a new multiplier 12 is used to perform the demodulation signal. It is.

第4図は本発明の第3の実施例を示す。 FIG. 4 shows a third embodiment of the invention.

この例は前記第2の実施例の変形であつて、信
号f′と、基準周波数F0をn逓倍器11でn逓倍し
た信号f0=nF0とを乗算器12によつて乗算した
後、ローパスフイルタ13を通して復調信号とす
るものである。基本動作は前記第1の実施例と全
く同様である。
This example is a modification of the second embodiment, in which the signal f' is multiplied by the signal f 0 = nF 0 obtained by multiplying the reference frequency F 0 by n by the n multiplier 11 by the multiplier 12. , and is used as a demodulated signal through a low-pass filter 13. The basic operation is completely the same as that of the first embodiment.

第5図は本発明の第4の実施例を示す。 FIG. 5 shows a fourth embodiment of the invention.

この例では、第1の実施例における基準周波数
発振器7を用いる代わりに、ロワーヘテロダイン
方式によつて得られる中間周波信号fとアツパー
ヘテロダイン方式によつて得られる中間周波信号
とを夫々1/n分周した、信号Fと信号とを
位相比較器6で相比較するようにしている。ここ
において、10′は局部発振周波信号f3(周波
数はf3)を出力する電圧制御局部発振器、2′は
FM高周波信号f1と信号f3とを混合して中間
周波信号(周波数は=f3−f1)を出力する混
合器、3′は中間周波フイルタ、4′は中間周波増
幅器(リミツタ付き)、5′は信号を1/nに分
周して1/n周波信号とする1/nを分周器を
夫々示している。基本動作は前記第1の実施例と
全く同様である。
In this example, instead of using the reference frequency oscillator 7 in the first embodiment, the intermediate frequency signal f obtained by the lower heterodyne method and the intermediate frequency signal obtained by the upper heterodyne method are each 1/n. The phase comparator 6 compares the phase of the frequency-divided signal F and the signal. Here, 10' is a voltage controlled local oscillator that outputs a local oscillation frequency signal f3 (frequency is f3), and 2' is
A mixer that mixes the FM high frequency signal f1 and signal f3 and outputs an intermediate frequency signal (frequency = f3 - f1), 3' is an intermediate frequency filter, 4' is an intermediate frequency amplifier (with a limiter), and 5' is an intermediate frequency signal. Each figure shows a 1/n frequency divider that divides the signal into a 1/n frequency signal to produce a 1/n frequency signal. The basic operation is completely the same as that of the first embodiment.

以上詳細に述べたように、本発明に係るFM受
信機によれば、減衰特性の鋭い中間周波フイルタ
を用いても、位相補償なしでPLLの位相余裕を十
分に得ることができるから、ループ応答速度及び
ループ利得が大きく低下することはなくなり、従
つてFM高周波信号の変調信号周波数の上限や周
波数偏移の幅が制限を受けをこともなくなる。す
なわち、受信選択度が優れていて、しかも再生音
の周波数特性及びダイナミツクレンジの広い、
PLL方式のFM受信機を実現することが可能とな
るのである。しかもその構成は中間周波増幅器の
後段に分周器を挿入するだけの簡単なものである
から、製作が容易かつコストも安い等、本発明
FM受信機は数多の優れた特長を具有するもので
ある。
As described in detail above, according to the FM receiver according to the present invention, even if an intermediate frequency filter with a sharp attenuation characteristic is used, sufficient phase margin of the PLL can be obtained without phase compensation, so that the loop response The speed and loop gain will not be significantly reduced, and therefore the upper limit of the modulation signal frequency and the frequency deviation width of the FM high-frequency signal will no longer be restricted. In other words, it has excellent reception selectivity, and has a wide frequency response and dynamic range of reproduced sound.
This makes it possible to realize a PLL type FM receiver. Furthermore, since the configuration is as simple as inserting a frequency divider after the intermediate frequency amplifier, the present invention is easy to manufacture and inexpensive.
FM receivers have many excellent features.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はフエーズロツクトループ方式のFM受
信機の−従来例を示す回路ブロツク図である。第
2図乃至第5図は本発明に係るFM受信機の実施
例を示し、第2図は第1の実施例、第3図は第2
の実施例、第4図は第3の実施例、第5図は第4
の実施例の夫々回路ブロツク図である。 5,5′……1/n分周器。
FIG. 1 is a circuit block diagram showing a conventional example of a phase-lock loop type FM receiver. 2 to 5 show embodiments of the FM receiver according to the present invention, FIG. 2 is the first embodiment, and FIG. 3 is the second embodiment.
4 is the third embodiment, and FIG. 5 is the fourth embodiment.
3 is a circuit block diagram of each embodiment; FIG. 5, 5'...1/n frequency divider.

Claims (1)

【特許請求の範囲】[Claims] 1 FM高周波信号と電圧制御局部発振器より出
力される局部発振周波信号とを混合して、中間周
波信号を出力する混合器と、前記中間周波信号の
通過帯域幅を定める中間周波フイルタと、該中間
周波フイルタの出力を増幅する中間周波増幅器
と、中間周波増幅器から出力され中間周波信号と
基準周波数等とを位相比較器において位相比較
し、その出力信号によつて前記電圧制御局部発振
器を制御して局部発振周波数を前記中間周波信号
の周波数偏移に追従させるようになしたフエーズ
ロツクトループ方式のFM受信機において、前記
中間周波増幅器と位相比較器との間に分周器を設
けることにより、分周された中間周波信号と基準
周波数等とを前記位相比較器において位相比較す
るように構成したことを特徴とするFM受信器。
1. A mixer that mixes an FM high frequency signal and a local oscillation frequency signal output from a voltage controlled local oscillator to output an intermediate frequency signal, an intermediate frequency filter that determines the passband width of the intermediate frequency signal, and an intermediate frequency amplifier that amplifies the output of the frequency filter; a phase comparator compares the phases of the intermediate frequency signal outputted from the intermediate frequency amplifier with a reference frequency, etc.; and controls the voltage controlled local oscillator using the output signal thereof; In a phase locked loop FM receiver in which the local oscillation frequency follows the frequency shift of the intermediate frequency signal, by providing a frequency divider between the intermediate frequency amplifier and the phase comparator, 1. An FM receiver characterized in that the frequency-divided intermediate frequency signal and a reference frequency are phase-compared in the phase comparator.
JP11205680A 1980-08-14 1980-08-14 Fm receiver Granted JPS5737906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11205680A JPS5737906A (en) 1980-08-14 1980-08-14 Fm receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11205680A JPS5737906A (en) 1980-08-14 1980-08-14 Fm receiver

Publications (2)

Publication Number Publication Date
JPS5737906A JPS5737906A (en) 1982-03-02
JPS6253081B2 true JPS6253081B2 (en) 1987-11-09

Family

ID=14576924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11205680A Granted JPS5737906A (en) 1980-08-14 1980-08-14 Fm receiver

Country Status (1)

Country Link
JP (1) JPS5737906A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437915A (en) * 1987-08-03 1989-02-08 Fujisawa T Co Ltd Carp streamer and coloration thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630437B2 (en) * 1987-09-18 1994-04-20 日本電気株式会社 Communication device
JP6926813B2 (en) 2017-08-15 2021-08-25 富士フイルムビジネスイノベーション株式会社 Information processing equipment and programs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437915A (en) * 1987-08-03 1989-02-08 Fujisawa T Co Ltd Carp streamer and coloration thereof

Also Published As

Publication number Publication date
JPS5737906A (en) 1982-03-02

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