JPH06326603A - Pll frequency synthesizer circuit - Google Patents

Abstract

PURPOSE:To provide a PLL frequency synthesizer circuit in which the output of a frequency in a wide range which can not be obtained conventionally by a single VCO can be obtained by using a single VCO, and miniaturization can be prompted. CONSTITUTION:In the PLL frequency synthesizer circuit constituted of a phase comparator 11, low pass filter 12, voltage control oscillator 13, and programmable N counter 14, a frequency converter 15 is provided between one voltage control oscillator 13 and the programmable N counter 14. The output in the wide frequency range which can not be obtained conventionally without using the plural VCO can be obtained by using one VCO, so that the sharp miniaturization of the circuit can be attained. Then, the circuit can be integrated into one chip IC while a 2<n> programmable frequency-divider is included, and the further miniaturization can be realized. Also, only one VCO is used so that the number of the factors of fault occurrence can be smaller than the conventional manner using the plural VCO, and the cost can be low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator, a low pass filter and a voltage controlled oscillator (hereinafter referred to as VCO).
And a programmable counter, and relates to a PLL frequency synthesizer circuit for obtaining a wide range multiplied clock signal synchronized with the input reference signal from the input reference signal.

[0002]

2. Description of the Related Art As a conventional PLL frequency synthesizer circuit of this type, for example, the one shown in the block diagram of FIG. 2 is known as a basic circuit. In the circuit of Figure 2, VCO 3 frequencies f the oscillation frequency f _o divided by N of
The phase of the signal of _{v and} the signal of the reference frequency f _r is compared by the phase comparator 1, an error voltage proportional to the phase difference between the two signals is generated, and the error voltage is passed through the low pass filter 2 to extract a high frequency component. Except for this, the error voltage at the output of the low-pass filter 2 is supplied to the VCO 3, and thereby the oscillation frequency f _s of the VCO 3 is controlled so that f _v approaches the reference frequency f _r . Part of the signal of the output frequency f _o is divided by the programmable · N counter 4 is input to the phase comparator 1 as a signal of the frequency f _v. Phase comparator 1, low pass filter 2, VCO 3 and programmable N
The feedback loop is made with the counter 4.

When this loop is completely locked, f _r =
f _o / N ie f _o = N · f _r and turned to the reference frequency f
A multiplied (N times) clock signal synchronized with the _r signal is obtained. Such a PLL frequency synthesizer is applied to various fields such as transceivers, communication devices, radios, TVs, measuring instruments, and electronic musical instruments. In any application field, when trying to obtain a clock signal over a wide range of frequencies, one VCO has a limited oscillating frequency range. The VCOs were switched according to the above.

[0004]

However, in such a conventional PLL frequency synthesizer circuit, the larger the frequency range of the output to be obtained, the larger the number of VCOs required and the smaller the circuit size. There was a problem that it became difficult to make it.

Therefore, the present invention, while using a single VCO, obtains an output in a wide range of frequencies which has not been obtained by the conventional single VCO, and further promotes miniaturization.
It is an object to provide a frequency synthesizer circuit.

[0006]

[Means for Solving the Problems] The main points for achieving such an object are: PLL for obtaining a multiplied clock signal in a wide frequency range synchronized with an input reference frequency signal
A frequency synthesizer circuit, comprising: a phase comparator (11) for comparing the phases of input first and second signals to generate a signal representing the phase difference between the two signals; and a high frequency included in the phase difference signal. Low pass filter excluding components (12)
A voltage controlled oscillator (13) that receives the output of the low pass filter (12) as a control voltage, and a programmable N counter (14) that divides the frequency of the output of the voltage controlled oscillator (13). In a circuit in which the reference frequency signal is the first signal and the output of the programmable N counter (14) is the second signal, the number of the voltage controlled oscillators (13) is one, and the one voltage A PLL frequency synthesizer circuit is characterized in that a frequency converter (15) is provided between the output end of the controlled oscillator (13) and the input end of the programmable N counter (14).

2. 2. The PLL frequency synthesizer circuit according to item 1, wherein the frequency converter (15) is a 2 ⁿ programmable frequency divider.

[0008]

Function: Input signal of reference frequency f _r and programmable N
The phase with the output signal of the oscillation frequency f _v of the VCO (13) divided by N through the counter (14) is the phase comparator (1
1), the error voltage proportional to the difference is passed through the low pass filter (12) and becomes the VCO control voltage, which is the dividing frequency f _v of the output signal frequency f _s of the VCO (13) and the reference frequency f _r. The oscillation frequency of the VCO (13) is controlled so that and become equal, that is, the lock state is achieved. The output signal of VCO (13) is VCO
Since the frequency is converted by the frequency converter (15) provided after (13), a frequency exceeding the oscillation frequency range of one VCO can be obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

As shown in FIG. 1, the present embodiment compares the phases of the input signal of the reference frequency f _r and the output signal (frequency f _v ) of the programmable N counter 14 and outputs an error voltage representing a phase error. Phase comparator 11 and the VCO which excludes high frequency components included in the error voltage from the phase comparator 11.
A low-pass filter 12 that changes to a control voltage, a VCO 13 that changes an oscillation frequency f _s according to a control voltage, a frequency converter 15 that converts a frequency, and a programmable frequency-dividing part of the output from the frequency converter 15 by N. N counter 1
It consists of 4 and.

The frequency converter 15 can be either a frequency divider or a frequency multiplier, but when a frequency multiplier is used, a frequency divider is further provided in front of the programmable N counter 14.

Next, the operation will be described. In FIG. 1, an input frequency of 2 ⁿ is shown in FIG.
A case where a 2 ⁿ programmable frequency divider that divides (n is a positive integer) is used will be described.

The oscillation frequency f _{s of the} VCO 13 is divided by the programmable N counter 14 by N to obtain a frequency f _v (hereinafter, the frequency f _v will be referred to as "the dividing frequency of the N division counter (f _v )"). together with the input signal of the frequency f _r is input to the phase comparator 11.

The phase comparator 11 generates an error voltage proportional to the phase difference between the reference frequency f _r and the frequency division frequency f _v of the N frequency division counter.

The error voltage output from the phase comparator 11 becomes an average DC voltage with high frequency components cut by the low pass filter 12, that is, a control voltage of the VCO 13. This control voltage is the oscillation frequency f of the VCO 13.
It is supplied in the direction to reduce the difference between the frequency f _v and the reference frequency f _r which was dividing _s.

The VCO 13, which is a free-running oscillator, oscillates at a predetermined frequency, a so-called free-running frequency, because the error voltage is equal to 0 when the input signal of the reference frequency f _r is not supplied to the PLL frequency synthesizer circuit. When an input signal is supplied, the control voltage generated by the above process causes V
CO13 is controlling the oscillation frequency in the direction to reduce the difference between the reference frequency f _r of the divided frequency f _v and the input signal of the divide-by-N counter which is proportional to the oscillation frequency f _s.

The oscillation frequency f _s from the VCO 13 is 2 ⁿ
The output frequency fo is _divided into 1/2 ⁿ by the programmable frequency divider 15, a part of which is input to the programmable N counter 14 and divided by N to obtain the divided frequency f.
_v . This divided frequency f _v is input to the phase comparator 11.

The above process is repeated until the divided frequency f _v and the reference frequency f _r completely match.

When the frequency division frequency f _v and the reference frequency f _r match in this way and synchronization is established, the VCO 13 always maintains the phase so that the phase difference between the frequency division frequency f _v and the reference frequency f _r is minimized. to follow the change of the reference frequency f _r while changing.

In the 2 ⁿ programmable frequency divider 15, n
= 0, the oscillation frequency f _s from the VCO 13
Is not divided by the 2 ⁿ programmable divider 15, the relationship between the reference frequency f _r and the division frequency f _v when the synchronization is established is the same as that of the basic PLL of the prior art shown in FIG. Similarly to the case, f _r = f _v = f _o / N ∴f _o = Nf _r , and the output frequency f _o becomes the N-multiplied clock signal of the reference frequency f _r . Now, the frequency change ratio of the VCO13 is 2, the output frequency f _o equal to the oscillation frequency f _s of the VCO13 is programmable N counter N
By changing the value of (N in the above equation), VCO1
3 from the maximum oscillation frequency f _max to the minimum oscillation frequency f _max /
It is possible to change up to 2.

Next, when n = 1 is set in the 2 ⁿ programmable frequency divider 15, the oscillation frequency f _s from the VCO 13 is divided by 2, so that f _o = f _s / 2,
By changing the value of the programmable N counter N, f _max / 4 from f _max / 2 as an output frequency f _o
Can be output.

In the 2 ⁿ programmable frequency divider 15, n
= 2 is set, the oscillation frequency f _s from the VCO 13 is divided by 4, so that f _o = f _s / 4, and by changing the value of N of the programmable N counter,
The output frequency f _o can be output from f _max / 4 to f _max / 8.

Similarly, by changing the value of n of the 2 ⁿ programmable frequency divider 15 and the value of N of the programmable N counter, a wide range of output frequencies f _o can be obtained by using only one VCO.

Although the frequency converter 15 using the 2 ⁿ programmable frequency divider has been described above, a frequency multiplier 15 may be used instead. In this case, a frequency divider is provided before the programmable N counter 14 so that the input frequency from the multiplier does not exceed the upper limit frequency that can be processed by the programmable N counter.

[0026]

According to the PLL frequency synthesizer circuit of the present invention, the output of a wide frequency range, which has hitherto been obtained only by using a plurality of VCOs, can be obtained by one V.
Since it can be obtained using CO, the circuit can be remarkably miniaturized. And it can be integrated into a single-chip IC, including a frequency converter such as a 2 ⁿ programmable frequency divider.
Further downsizing can be realized.

Further, since only one VCO is used, the cause of failure is less than that when a plurality of VCOs are used.
The cost is also low.

[Brief description of drawings]

FIG. 1 is a block diagram showing a PLL frequency synthesizer circuit according to an embodiment of the present invention.

FIG. 2 is a basic block diagram showing a PLL frequency synthesizer circuit.

[Explanation of Codes] 11 Phase Comparator 12 Low Pass Filter (LPF) 13 Voltage Controlled Oscillator (VCO) 14 Programmable N Counter 15 Frequency Converter f _r Reference Frequency f _s VCO 13 Oscillation Frequency f _o Output Frequency f _v N Frequency Division Frequency division frequency of counter

Claims (2)

[Claims] 1. A PLL frequency synthesizer circuit for obtaining a multiplied clock signal in a wide frequency range synchronized with an input reference frequency signal, wherein the phases of first and second input signals are compared. Then, a phase comparator that generates a signal representing the phase difference between the two signals, a low-pass filter that removes high-frequency components included in the phase-difference signal, a voltage-controlled oscillator that receives the output of the low-pass filter as a control voltage, and And a programmable N counter for dividing the frequency of the output of the voltage controlled oscillator, wherein the reference frequency signal is the first signal and the output of the programmable N counter is the second signal. There is only one controlled oscillator, and a frequency is provided between the output terminal of the one voltage controlled oscillator and the input terminal of the programmable N counter. A PLL frequency synthesizer circuit comprising a number converter. 2. The PLL frequency synthesizer circuit according to claim 1, wherein the frequency converter is a 2 ⁿ programmable frequency divider.