JPH04111532A - Pll circuit - Google Patents

Abstract

PURPOSE:To allow the frequency and the phase of an output signal to follow up those of a reference clock signal by temporarily adding a voltage, which reduces the phase difference, to a voltage controlled oscillator in the case of the quick change of the phase of the reference clock signal due to some cause. CONSTITUTION:A first switch 2 which connects or disconnects a reference clock input terminal and the other input terminal of a phase comparator and an adder 6 which adds the output signal of an amplifier 5 and a prescribed control voltage and outputs the result to a voltage controlled oscillator 7 are provided. If the phase of the reference clock signal is deviated from that of the output signal of a frequency divider 9 by a prescribed value or larger, the switch 2 is opened. When the phase of the reference clock signal leads that of the output signal of the frequency divider 9 by a prescribed value or larger, the voltage to raise the oscillation frequency of the voltage controlled oscillator 7 is outputted to the adder 6 as the control voltage; but when the phase of the reference clock signal is delayed behind that of the output signal of the frequency divider 9, the voltage to reduce the oscillation frequency us outputted to the adder 6 as the control voltage. Thus, the frequency and the phase of the output signal follow up those of the reference clock signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a PLL circuit that is used in communication equipment and generates a signal that is phase-locked to a given reference clock signal and has a frequency that is an integral multiple of the reference clock signal. It is related to.

[Conventional technology]

An example of a conventional PLL circuit of this type will be shown in the second article. 3 is a phase comparator (PC) that compares the reference clock signal input to the reference clock input terminal 1 with the voltage controlled oscillator (VCO) 7.
A voltage proportional to the phase difference between the output signal and the signal obtained by frequency-dividing the output signal by frequency divider 9 to 1/N (N is an integer) is output. The output signal of the phase comparator 3 is sufficiently smoothed by removing high frequency components by a low-pass filter 4, and then amplified by an amplifier 5 and applied to the VCO 7 as a frequency control voltage. Phase comparator 3, low-pass filter 4, amplifier 5, VC
The loop constituted by O7 and the frequency divider 9 is configured to perform negative feedback, and the output terminal 8 outputs the reference clock signal having a frequency N times that of the reference clock signal input to the input terminal 1. A signal that is phase-synchronized with the signal is output.

[Problem to be solved by the invention]

In such a PLL circuit, the cutoff frequency of the low-pass filter 4 is usually set to a low value in order to suppress jitter in the reference clock signal and improve stability against noise generated inside the PLL circuit. (so the time constant is set to a large value).

If the phase of the reference clock signal changes greatly and rapidly for some reason, or if the PLL circuit is free-running and a reference clock signal with a phase that is significantly different from that is input, The error output of the phase comparator 3 becomes large, and as a result, the output of the amplifier 5 rises or falls to near its power supply voltage, and the PLL circuit operates beyond its dynamic range, so that the negative feedback effect no longer works. When the negative feedback effect disappears, the followability of the output of the low-pass filter 4 to the input is determined by the time constant of the filter 4, and its value is set to the negligible value as described above. Therefore, it takes an extremely long time for the PLL circuit to finally operate within the dynamic range and reach a phase-locked state.

In addition, until the PLL circuit becomes phase-locked, VCO7
is controlled by the amplifier 5 whose output voltage rises or falls near the power supply voltage, so the VCO 7 oscillates at a frequency that is significantly different from the expected center frequency for a long period of time, resulting in poor stability of the free-running frequency. This also becomes a big problem in applications that require the following.

The purpose of the present invention is to solve such problems, and to solve the problem when the phase of the reference clock signal changes greatly and suddenly for some reason, or when the phase of the PLL circuit changes significantly from the phase when the PLL circuit is free-running. To provide a PLL circuit which can sufficiently smoothly and quickly make the frequency and phase of an output signal follow the frequency and phase of a reference clock signal even when a phase reference clock signal is input.

[Means to solve the problem]

The present invention includes a reference clock input terminal for inputting a reference clock signal, a first phase comparator that outputs a voltage signal proportional to the phase difference between two signals applied to the two input terminals, and a first phase comparator that outputs a voltage signal proportional to the phase difference between two signals applied to the two input terminals. A low-pass filter that removes high-frequency components from the output signal of the comparator and outputs the result, an amplifier that amplifies and outputs the output signal of the low-pass filter, a voltage-controlled oscillator, and the oscillator. a frequency divider that divides an output signal of the phase comparator and outputs the frequency divided signal to one of the input terminals of the phase comparator, the reference clock input terminal and the other input terminal of the phase comparator, a first switch that connects or disconnects the amplifier based on a predetermined control signal; an adder that adds the output signal of the amplifier and a predetermined control voltage and outputs the result to the voltage controlled oscillator; and the reference clock input terminal. When the reference clock signal is input to the frequency divider and the phase of the reference clock signal deviates from the phase of the output signal of the frequency divider by a predetermined value or more, the predetermined control signal is output to shut off the switch. When the phase of the reference clock signal is ahead of the phase of the output signal of the frequency divider by a predetermined value or more, the voltage for increasing the oscillation frequency of the voltage controlled oscillator is, conversely, delayed. and control means for outputting a voltage for lowering the oscillation frequency to the adder as the predetermined control voltage when the oscillation frequency is lowered.

Further, according to the PLL circuit of the present invention, the control means includes: a first fixed voltage generator that generates a voltage for increasing the oscillation frequency of the voltage controlled oscillator; and a first fixed voltage generator that lowers the oscillation frequency of the voltage controlled oscillator. a second fixed voltage generator that generates a voltage for the second fixed voltage generator; and a second fixed voltage generator that selects and outputs a voltage generated by the first fixed voltage generator when the phase lead detection signal is input, and a voltage that is generated by the first fixed voltage generator when the phase lead detection signal is input; a selection circuit that selects and outputs the voltage generated by the second fixed voltage generator when a signal detector that detects whether or not the reference clock signal is input to the reference clock input terminal; and a signal detector that detects whether or not the reference clock signal is input to the reference clock input terminal; a second phase comparator that outputs a voltage; and based on the output voltage of this phase comparator, the phase advance when the phase of the reference clock signal is ahead of the phase of the output signal of the frequency divider by a predetermined value or more. Based on the output voltages of a first phase detector that outputs a detection signal and the second phase comparator, the phase of the reference clock signal lags the phase of the output signal of the frequency divider by a predetermined value or more. When the second phase detector outputs the phase delay detection signal, the signal detector detects that the reference clock signal is input, and the first or second phase detector outputs the detection signal. and a logic circuit that outputs the predetermined control signal to turn off the first switch and turn on the second switch when outputting the predetermined control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a PLL circuit according to the present invention. This PLL circuit includes a reference clock input terminal l for inputting a reference clock signal, and a phase comparator (PC) 3 that outputs a voltage signal proportional to the phase difference between two signals applied to the two input terminals. , a low-pass filter 4 that removes the high-frequency bottom from the output signal of this phase comparator 3 and outputs it, and an amplifier (AMP) that amplifies and outputs the output signal of this low-pass filter. ) 5, a voltage controlled oscillator (VCO) 7, and the output signal of this oscillator 7 by 1/N.
A frequency divider 9 that divides the frequency into 1 and outputs it to one input terminal of the phase comparator 3, and a reference clock input terminal 1 and the other input terminal of the phase comparator 3 are connected based on a predetermined control signal. Alternatively, it includes a switch (SW) 2 that shuts off, and an adder 6 that adds the output signal of the amplifier 5 and a predetermined control voltage and outputs the result to the VCO 7.

This PLL circuit further includes V as a component of the control means.
A fixed voltage generator 11 generates a voltage to raise the oscillation frequency of the CO7, a fixed voltage generator 16 generates a voltage to lower the oscillation frequency of the VCO7, and a fixed voltage generator 16 generates a voltage to lower the oscillation frequency of the VCO7. a selection circuit (SEL) 18 that selects and outputs the voltage generated by the voltage generator 11 and selects and outputs the voltage generated by the fixed voltage generator 16 when the phase lag detection signal is input; A switch (SW) 10 that connects or disconnects the output of the selection circuit 18 and the input of the adder 6 according to a control signal, and a signal detector that detects whether or not a reference clock signal is input to the reference clock input terminal 1. Based on the output voltage of the phase comparator 14, A phase detector (DET) outputs a phase lead detection signal when the phase of the reference clock signal is ahead of the phase of the output signal of the frequency divider 9 by a predetermined value or more.
) 15, and a phase detector (DET) that outputs a phase lag detection signal when the phase of the reference clock signal lags the phase of the output signal of the frequency divider 9 by a predetermined value or more based on the output voltage of the phase comparator 14. ) 17, when the signal detector 12 detects that the reference clock signal is input and the phase detector 15 or phase detector 17 outputs the detection signal, a predetermined control signal is output and the switch is activated. A combinational logic circuit in which switch 2 is cut off and switch 1o is connected
LGC) 13.

Next, the operation will be explained. First, if the reference clock signal is not input, or even if the reference clock signal is input, if the phase difference between the reference clock signal and the output signal of the frequency divider 9 is less than a predetermined value, the logic circuit 13 outputs a predetermined control signal, the switch 2 is brought into the connected state, and the switch 1o is brought into the cut-off state. Therefore, in this case, the circuit becomes equivalent to the conventional PLL circuit shown in FIG. 2 and operates as before.

Next, an explanation will be given of the operation when the phase of the reference clock signal changes drastically (by 180 degrees or less) in a direction leading from the phase of the output signal of the frequency divider 9. In this case, since the reference clock signal is input to the input terminal 1, the detector 12 detects the reference clock signal and outputs a signal indicating this to the logic circuit 13, and also the phase comparator 1
4 outputs a voltage representing the phase difference between the two signals, and the detector 15 uses the voltage to detect that the phase of the reference clock signal deviates by more than a predetermined value in a direction that advances the phase of the output signal of the frequency divider 9. It detects this and outputs a phase lead detection signal.

As a result, the logic circuit engineer 3 outputs a control signal to turn the switch 2 into a cutoff state and the switch 10 into a connection state. on the other hand,
The selection circuit 18 selects and outputs the voltage of the fixed voltage generator 11 based on the phase lead detection signal from the detector 15, and the selected voltage is input to the adder 6 through the switch 10. Since the reference clock signal is cut off by the switch 2, the VCO 7 is in a free-running state, and in this state, the voltage from the fixed voltage generator 11 is added by the adder 6, and the VCO
7, the oscillation frequency of the VCO 7 is shifted to a higher side than its center frequency (N times the frequency of the reference clock signal).

As a result, the phase of the output signal of the frequency divider 9 quickly approaches the phase of the reference clock signal, and when the phase difference between these two signals becomes less than a predetermined value, the detection signal is output from the detector 15.17. Since no longer is output, the logic circuit 13 outputs a control signal to bring the switch 2 into the connected state and the switch 10 into the cut off state. As a result, the PLL circuit shifts to normal operation and synchronizes the output signal of the VCO 7 with the reference clock signal.

The output voltages of the fixed voltage generators 11 and 16 are set so that the change in the oscillation frequency of the VCO 7 from the center frequency due to the output voltages is within the range allowed by the circuits subsequent to the 20 PLL circuit. Furthermore, if the output voltage of the phase comparator 14 is clear, the phase difference between the reference clock signal and the output signal of the frequency divider 9 is small, and the PLL circuit detects the dynamic in the microwave,
and Vc.

The value is set so that the phase can be followed within the range where the change in the oscillation frequency of No. 7 is permissible.

The operation is basically the same when the phase of the reference clock signal lags behind the phase of the output signal of the frequency divider 9 and changes rapidly. In this case, the detector 17 detects a large phase delay in the reference clock signal, and as a result, the selection circuit 18 selects and outputs the voltage from the fixed voltage generator 16, and the switch 2 is cut off. , the switch 10 becomes connected.

As a result, a voltage is applied to the free-running VCO 7 to lower its oscillation frequency, and the phase of the output signal of the frequency divider 9 quickly approaches the phase of the reference clock signal. Thereafter, the switches 2 and 10 return to their original states, and the PLL circuit operates normally.

Therefore, in the PLL circuit of the present invention, when the phase of the reference clock signal changes greatly and rapidly for some reason, or when the PLL circuit is free-running, the reference clock signal with a phase significantly different from the phase of the reference clock signal changes. When input, a voltage is temporarily applied to the VCO to reduce the phase difference, and once the phase difference has been reduced, it returns to normal operation, so the frequency of the output signal can be adjusted sufficiently smoothly and quickly. The phase can be made to follow the frequency and phase of the reference clock signal.

〔Effect of the invention〕

As explained above, the present invention provides a reference clock input terminal for inputting a reference clock signal, and a first phase comparison device that outputs a voltage signal proportional to the phase difference between two signals applied to the two input terminals. a low-pass filter that removes high-frequency components from the output signal of this phase comparator and outputs it; an amplifier that amplifies and outputs the output signal of this low-pass filter; and a voltage control circuit. In a PLL circuit comprising an oscillator and a frequency divider that divides the frequency of an output signal of the oscillator and outputs the divided signal to one input terminal of a phase comparator, a reference clock input terminal and the other input terminal of the phase comparator are provided. a first switch that connects or disconnects the terminal based on a predetermined control signal, an adder that adds the output signal of the amplifier and a predetermined control voltage and outputs the result to the voltage controlled oscillator, and a reference clock input terminal. When a reference clock signal is input and the phase of the reference clock signal deviates from the phase of the output signal of the frequency divider by more than a predetermined value, a predetermined control signal is output to turn off the switch, and the reference clock signal is output. When the phase of the output signal of the frequency divider is ahead of the phase of the output signal of the frequency divider by more than a predetermined value, the voltage is applied to increase the oscillation frequency of the voltage controlled oscillator, and conversely, when it is behind the phase of the output signal of the frequency divider, the voltage is applied to lower the oscillation frequency. and control means for outputting the voltage to the adder as a predetermined control voltage.

Therefore, in the PLL circuit of the present invention, when the phase of the reference clock signal changes suddenly for some reason, or when the PLL circuit is free-running, the reference clock signal with a phase significantly different from that of the reference clock signal can be used. When a signal is input, a voltage is temporarily applied to the voltage controlled oscillator to reduce the phase difference, and once the phase difference has been reduced, it returns to normal operation, so the output is sufficiently smooth and prompt. The frequency and phase of the signal can be made to follow the frequency and phase of the reference clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional PLL circuit. 1...Input terminal 2.10...Switch (SW) 3.14...Phase comparator (PC) 4...Low pass filter 5... Amplifier (AMP) 6... Adder 7... Voltage controlled oscillator (VCO) 8... Output terminal 9... Frequency divider 11, 16... Fixed voltage Generator 12, 15.17/Detector CDET) 13...Combinational logic circuit (LGC) 18...
...Selection Circuit (SEL) Agent Patent Attorney Yoshiyuki Iwasa

Claims (2)

[Claims] (1) A reference clock input terminal for inputting a reference clock signal, a first phase comparator that outputs a voltage signal proportional to the phase difference between two signals applied to the two input terminals, and this phase comparison. a low-pass filter that removes high-frequency components from the output signal of the oscillator, an amplifier that amplifies and outputs the output signal of the low-pass filter, a voltage-controlled oscillator, and a voltage-controlled oscillator; a frequency divider that divides the output signal and outputs it to one of the input terminals of the phase comparator.
In the LL circuit, a first switch connects or disconnects the reference clock input terminal and the other input terminal of the phase comparator based on a predetermined control signal; and a first switch connects or disconnects the reference clock input terminal and the other input terminal of the phase comparator based on a predetermined control signal; The reference clock signal is input to the adder that adds the voltage and outputs the resultant voltage to the voltage controlled oscillator, and the reference clock input terminal, and the phase of the reference clock signal is a predetermined phase higher than the phase of the output signal of the frequency divider. When the deviation exceeds a value, the predetermined control signal is output to turn off the switch, and when the phase of the reference clock signal leads the phase of the output signal of the frequency divider by a predetermined value or more, and control means for outputting a voltage for increasing the oscillation frequency of the voltage controlled oscillator to the adder as the predetermined control voltage, and conversely, outputting a voltage for decreasing the oscillation frequency when the oscillation frequency is delayed as the predetermined control voltage. A PLL circuit characterized by: (2) The control means includes a first fixed voltage generator that generates a voltage for increasing the oscillation frequency of the voltage controlled oscillator, and a first fixed voltage generator that generates a voltage for decreasing the oscillation frequency of the voltage controlled oscillator. the first fixed voltage generator selects and outputs the voltage generated when the phase lead detection signal is input, and the second fixed voltage generator selects and outputs the voltage generated when the phase lead detection signal is input; a selection circuit that selects and outputs the voltage generated by the voltage generator; a second switch that connects or disconnects the output of the selection circuit and the input of the adder according to the predetermined control signal; and the reference. a signal detector that detects whether or not the reference clock signal is input to a clock input terminal; and a second signal detector that outputs a voltage proportional to the phase difference between the reference clock signal and the signal output from the frequency divider. a first phase comparator, which outputs the phase advance detection signal when the phase of the reference clock signal is ahead of the phase of the output signal of the frequency divider by a predetermined value or more based on the output voltage of the phase comparator; and detecting the phase lag detection signal when the phase of the reference clock signal lags the phase of the output signal of the frequency divider by a predetermined value or more based on the output voltage of the phase detector and the second phase comparator. a second phase detector that outputs, and when the signal detector detects that the reference clock signal is input and the first or second phase detector outputs the detection signal, the predetermined 2. The PLL circuit according to claim 1, further comprising a logic circuit that outputs a control signal to turn off the first switch and turn on the second switch.