WO2007062577A1

WO2007062577A1 - A phase-locked loop and method of improving clock precision

Info

Publication number: WO2007062577A1
Application number: PCT/CN2006/003059
Authority: WO
Inventors: Qing Zhang
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2005-12-01
Filing date: 2006-11-14
Publication date: 2007-06-07
Also published as: CN100477527C; CN1859004A

Abstract

A phase-locked loop and method of improving clock precision are provided. Control processor , temperature sensor and memory are added to the phase-locked loop. Adjustment value of a digital synthesizer is suitably selected by the control processor, and is written into the digital synthesizer, so that eliminating original frequency deviation, improving free clock standard of device; also, when the system is normally tracking, drift characteristic and aging rate of the oscillator in the system are obtained by calculating, when the system is holding, it makes real-time forecast and correction according to the obtained drift characteristic and aging rate of the oscillator ,so that improving stability and accuracy of output clock when hoding. The present invention improves clock precision and makes sufficient meaning for network synchronization by improving design of the phase-locked loop.

Description

The invention relates to a Chinese patent filed on December 1, 2005, the Chinese Patent Office, the application number is 200510102081.7, and the invention name is "a phase-locked loop and a method for improving clock accuracy". Priority of the application, the entire contents of which are incorporated herein by reference.

Technical field

The present invention relates to the field of electrical communication technologies, and in particular, to a phase locked loop and a method for improving clock accuracy.

Background technique

For communication devices, the clock is generally required to provide the operating frequency. Clock performance is an important aspect that affects the performance of the device. When devices and systems form a network, the performance of the clock affects the performance of the entire network. Each communication organization, country, and operator must rigorously test the clock performance of the device before it enters the network. The indicators of the clock mainly include free time accuracy, drift generation during tracking, and maintaining performance. At present, the phase-locked loop technology is mainly used to keep the clock from the reference clock or the upper-level clock, so that the entire network clock works at the same frequency. The clock circuit is usually implemented by a dedicated phase-locked loop device or a separate device. With the same input clock source, the accuracy of the clock depends on the design of the phase-locked loop and the performance of the oscillator. The drift during tracking depends primarily on the design of the phase-locked loop. Free accuracy and hold performance depend primarily on the performance of the oscillator. In the Digital Synchronous Network Equipment (BITS), the secondary clock is configured with a cesium atomic clock, a three-stage clock configuration oscillator or a voltage controlled crystal oscillator. With the development of communication services, the requirements for the end devices to be synchronized are highlighted. The end device is characterized by a lack of concentration of the device and a large number. For this reason, reducing costs and increasing the accuracy of the clock have become new topics in the field of clocks.

In the prior art, a schematic diagram of the structure of the phase locked loop is shown in FIG.

The phase-locked loop is usually composed of three basic components: a digital phase detector (PD) 110, a loop filter (LF) 120, and a voltage controlled oscillator (VCXO) 130. The digital phase detector 110 is a phase comparison device for detecting a phase difference Θ e(t) between the phase Vi(t) of the input signal and the feedback signal phase Vo(t), and the output error signal Ud(t) is The phase difference signal Θ e(t); the loop filter 120 has a low-pass characteristic; the VCXO 130 is a voltage-to-frequency conversion device that acts as a controlled oscillator in the loop.

The working principle is as follows: The digital phase detector uses the input signal as a standard, and its frequency and The phase is compared to the signal sent from the output. If any phase (frequency) difference is detected within its operating range, an error signal ud(i is generated, the AC component in the error signal is filtered by the loop filter, and the signal Uc(t) is generated to control the VCXO, forcing The VCXO changes its frequency in the direction of decreasing the phase/frequency error, causing any frequency or phase difference between the input reference signal and the VCXO output signal to gradually decrease until it is 0, at which point the loop is locked. If VCXO The output frequency is lower than the frequency of the input reference signal, and the output amplitude of the phase comparator is positive. After filtering, it controls vcxo to increase its frequency until the frequency and phase of the two signals are accurately synchronized. Conversely, if the VCXO output frequency Above the input reference signal, the output of the phase comparator drops, causing the VCXO to lock at the frequency of the input reference signal.

In the case of normal locking, the phase-locked loop is a closed-loop system. The output voltage of the loop filter is a stable voltage. At this time, the frequency of the VCXO output is also stable and locked.

The disadvantage of this type of phase-locked loop is that when the reference source is lost, the phase-locked loop will be in an unlocked state, and the output of the loop filter will change from a stable voltage to an indeterminate voltage. This voltage causes the VCXO to output a comparison. The biased frequency causes the output frequency to be unusable and the accuracy of the output clock to be low. When the phase-locked loop is in normal lock, if the reference source is disturbed, the output will be affected and the hold function will not be easily realized.

In the prior art, a schematic diagram of the configuration of the phase locked loop is shown in FIG. 2, and generally consists of five basic components: a frequency divider 210, a phase detector 220, a filter 230, a digital synthesizer 240, and an oscillator 250. The frequency divider 210 divides the input reference signal ref and the output feedback signal out, and divides the input signal and the output feedback signal to the same frequency; the phase detector 220 is a phase comparison device for detecting the input. The phase difference between the phase of the signal and the phase of the feedback signal. Filter 230 can function as a low pass filter. The digital synthesizer 240 is a digital synthesizing device which can stabilize the phase of the output clock out of the digital synthesizer and the phase opposite to the input clock ref by adjusting the frequency register of the digital synthesizer. Oscillator 250 is the local oscillator portion of the system and provides an oscillator source for digital synthesizer 240.

The working process is as follows: The frequency divider divides the input reference signal ref and the output feedback signal out, and the phase detector takes the input signal as a standard, and its frequency and phase are connected to the output terminal. The sent signals are compared. The phase detector sends the signal generated by the phase comparison to the filter for low-pass filtering. 4. The digital synthesizer is adjusted according to the filter processing deviation value, so that the digital synthesizer output feedback signal out and the reference signal ref are relatively stable, so that the system is in a locked state.

Regardless of the phase-locked loop, when the phase-locked loop is in a free state, that is, when it is not locked to the reference clock source, the accuracy of the clock signal output by the system depends on the current frequency of the oscillator. The value of the last filter output is to maintain the frequency value of the phase-locked loop output when the external reference clock signal is lost. The accuracy of the output clock of the system depends on the aging characteristics of the oscillator. As the oscillator ages, the accuracy gradually Deterioration. When it is necessary to improve the freedom and retention performance of the phase-locked loop, a high-performance oscillator is required, which inevitably increases the cost of the device.

Because of the same input clock source, the accuracy of the clock depends on the design of the phase-locked loop and the performance of the oscillator. The accuracy of the oscillator mainly depends on the factors such as the initial frequency deviation, the aging rate and the ambient temperature. Therefore, both the prior art 1 and the prior art 2 have the problems of the initial frequency deviation of the oscillator and the aging rate, and their existence greatly affects. The performance of the phase-locked loop affects the accuracy of the clock. At the same time, when the reference source is lost, the impact on the prior art oscillator is large, the accuracy of the output clock is relatively low, and the ability to resist external interference is also poor.

Summary of the invention

In view of the above problems in the prior art, the present invention proposes a phase locked loop and a method for improving the accuracy of the clock to improve the accuracy of the clock.

In order to achieve the above object, the present invention is achieved by the following technical solutions:

A phase locked loop includes a frequency divider, a phase detector, a filter, a digital synthesizer and an oscillator; a frequency divider is used to send the frequency-divided signal to the phase detector, and the phase detector processes the received signal. Outputting an error signal to the filter, the phase locked loop further comprising: a control processor, a temperature sensor and a memory;

The temperature sensor is configured to monitor a temperature of the oscillator, and transmit the monitored temperature value to the control processor;

The control processor is configured to, when normal tracking, adjust the digital synthesizer according to the filtered signal processed from the filter, and record the adjustment value; record the temperature sensor Obtaining the current temperature of the oscillator, and the correspondence between the current temperature value and the adjustment value; transferring the recorded information to the memory; the drift characteristic of the self-learning oscillator according to the adjusted value in the recorded preset time period and Aging rate

The memory is configured to store a temperature value of the oscillator, an adjustment value of the digital synthesizer, and a correspondence between the two;

The digital synthesizer is configured to output an output clock signal that is relatively stable with an input clock signal according to an adjustment signal from the control processor and an oscillation source signal from the oscillator.

The control processor is further configured to: when the device is powered on each time, obtain an adjustment value corresponding to the current temperature value from the memory according to the current temperature value and transmit the adjustment value to the digital synthesizer.

The control processor is further configured to predict and correct the adjustment value currently output to the digital synthesizer in real time according to the drift characteristics of the learned oscillator and the aging rate in the hold state.

The frequency divider and phase detector are implemented by an erasable programmable logic device EPLD or a field programmable gate array FPGA.

The filter is a digital filter composed of software;

The temperature sensor is a temperature monitoring chip;

The digital controller is a direct digital synthesis device DDS.

The oscillator is a constant temperature crystal.

The memory is comprised of an electrically erasable programmable read only memory (EEPROM) or flash memory (FLASH) that can be powered down.

A method for improving clock accuracy by using a phase locked loop as described above, comprising: obtaining a current frequency deviation of an oscillator by monitoring a temperature of an oscillator and an adjusted value of a recorded digital synthesizer; in normal tracking, the control processor is based on The adjusted value of the recorded digital synthesizer is the drift characteristic and aging law of the self-learning oscillator.

Further includes: after the device is powered on next time, the adjustment value of the digital synthesizer corresponding to the current temperature is selected and written into the digital synthesizer to eliminate the initial frequency deviation of the oscillator.

The method further includes: when the device is in the hold state, the control processor performs prediction and correction in real time according to the obtained drift characteristics and the aging rule.

It can be seen from the above invention that the control processor, the temperature sensor and the memory are added as compared with the prior art 2. Through the combination of these parts, the design of the phase locked loop is improved. Real-time monitoring of temperature and recording of DDS adjustment values, to obtain the current initial frequency deviation of the oscillator, to achieve high-precision output when free. Furthermore, the drift characteristics and the aging rate of the oscillator in the system are obtained by a self-learning method without increasing the cost, and the stability and accuracy of the holding period are improved, and high-precision maintenance is realized.

By using direct digital synthesis devices and digital filters, the accuracy of phase lock and the robustness of the phase-locked loop are improved. In digital synchronous network devices in the field of communications and other high precision clock devices, it is possible to obtain better results at a lower cost.

DRAWINGS

1 is a schematic structural view of a phase locked loop of the prior art;

2 is a schematic structural view of a phase locked loop of the prior art 2;

3 is a schematic structural view of a phase locked loop according to an embodiment of the invention.

detailed description

The principle of the present invention is shown in FIG. 3. The phase locked loop of the present invention includes a frequency divider 310, a phase detector 320, a filter 330, a digital synthesizer 350, an oscillator 360, a control processor 340, a temperature sensor 370, and a memory. 380; the frequency divider 310 is connected to the phase detector 320, the phase detector 320, the filter 330, the control processor 340, the digital synthesizer 350, and the oscillator 360 are sequentially connected, and the control processor 340 is a central module of the phase locked loop; The temperature sensor 370 is coupled to the control processor 340 and the oscillator 360 to detect the temperature of the oscillator in real time. The memory 380 is coupled to the control processor 340 for storing data corresponding to the temperature of the oscillator 360 and the adjustment value of the digital synthesizer 350.

Specifically, the temperature sensor is used to monitor the temperature of the oscillator, and the monitored temperature value is transmitted to the control processor; the temperature sensor is implemented by a common temperature monitoring chip.

The control processor is configured to adjust the digital synthesizer according to the filtered wave processed signal obtained from the filter during normal tracking, and record the adjustment value; record the current temperature of the oscillator obtained from the temperature sensor, and the current temperature value The correspondence with the adjustment value; the recorded information is transferred to the memory; the drift characteristic and the aging rate of the self-learning oscillator are based on the adjusted values in the recorded preset time period. The control processor can also be configured to transmit, from the memory, an adjustment value corresponding to the current temperature value to the digital synthesizer according to the current temperature value each time the device is powered on. The control processor can also be used to predict and correct the current output to digital synthesis in real time based on the drift characteristics of the learned oscillator and the aging rate. The adjustment value of the device. In addition, for the first start, it can be set by software in the factory, or it can be set. If it is not set, the accuracy may not be accurate enough when the first start, and then it will have no effect as long as it is adjusted to the normal state of the lock. And it has no effect on future operations.

The memory is used to store the temperature value of the oscillator, the adjustment value of the digital synthesizer, and the correspondence between the two; the memory is made of an electrically erasable programmable read only memory (EEPROM) or a flash memory (FLASH). The component composition of the power-down save.

The digital synthesizer is configured to output an output clock signal that is relatively stable with an input clock signal according to an adjustment signal from the control processor and an oscillation source signal from the oscillator, that is, the digital synthesizer output feedback signal out and the reference signal ref are relatively Stable, so the system is locked. The digital controller is a direct digital synthesis device (DDS). The oscillator is a constant temperature crystal.

The frequency divider divides the input reference signal ref and the output feedback signal, and divides the input signal and the output feedback signal to the same frequency. The two signals after frequency division are sent to the phase detector for phase discrimination processing, and the phase detector compares the phase difference between the phase of the input signal and the phase of the feedback signal after the frequency division of the output signal, and then sends the deviation value of the output to In the filter, the filter stores the phase value read by the phase detector into the buffer, filters out the outliers of the data in the buffer, and then takes the average of the data, so that the high frequency components can be effectively filtered out and simultaneously increased. The anti-interference ability (robustness) of the phase-locked loop. The divider and phase detector are implemented by an erasable programmable logic device (EPLD) or a field programmable gate array (FPGA). The filter is a digital filter composed of software.

The method of applying the above phase locked loop to improve the clock accuracy is as follows:

When the device is just powered on and heated, the oscillator has a certain initial frequency deviation, and this deviation determines the accuracy of the device output at this time. The temperature sensor can monitor the temperature of the oscillator in real time, the memory can be used to store the correspondence data of the oscillator temperature and frequency, and the control processor records the ambient temperature of the current oscillator and the current adjustment value of the digital synthesizer. This adjustment value represents the frequency deviation of the oscillator at the corresponding temperature, so the control processor can select an appropriate value to write to the digital synthesizer based on the recorded current temperature to eliminate the initial frequency deviation of the oscillator. Usually the initial frequency offset oscillator ^10-6 ~ ^10-8, by this method, the device can output up to the free 1 (T ⁹ ~ 10- ^1Q. This greatly improves the freedom of device clock indicators while enhancing The validity and practicability of the reference source decision.

When the reference source is present and normal, the device will be in the normal tracking state. The control processor adjusts the value of the digital synthesizer's frequency register in real time according to the data obtained by the filter to ensure the frequency of the output clock and the input clock. The frequency is consistent.

The adjustment value of the digital synthesizer indicates the frequency deviation of the oscillator relative to the reference source in this environment. The value of the frequency register of the digital synthesizer is changed in real time to compensate for the aging of the oscillator, and the curve representation of the adjustment value of the digital synthesizer and the time relationship. The aging process of the oscillator. The control processor records each adjustment value in real time while adjusting the digital synthesizer. Based on these adjustment values, the drift characteristics and aging laws of the oscillator obtained by self-learning can be calculated.

When the reference source is lost, the device is in the hold state, and the control processor obtains the drift characteristic and the aging rate of the oscillator according to the device in the tracking state, and performs real-time prediction and correction on the adjustment value of the digital synthesizer, thereby improving the output of the retention period. Clock stability and accuracy.

The above-mentioned real-time prediction correction process includes: In the tracking situation, the device can obtain the aging characteristics of the oscillator under different temperature conditions through self-learning. When the device enters the hold, the device selects an appropriate aging value from the previous aging characteristics to compensate in real time according to the current temperature condition, thereby realizing real-time prediction and correction.

The above are only preferred embodiments and are not intended to limit the scope of the invention.

Claims

Rights request

1. A phase locked loop comprising a frequency divider, a phase detector, a filter, a digital synthesizer and an oscillator; a frequency divider for transmitting the divided signal to a phase detector, the phase detector processing the received And outputting the error signal to the filter after the signal, wherein the phase locked loop further comprises: a control processor, a temperature sensor and a memory;

The control processor is configured to: in the normal tracking, the filtered wave processed signal obtained from the filter, adjust the digital synthesizer, and record the adjustment value of the digital synthesizer in the memory; record the oscillation obtained from the temperature sensor The current temperature of the device, and the correspondence between the current temperature value and the adjustment value; transferring the recorded information to the memory; according to the adjusted value in the recorded preset time period, the drift characteristic of the self-learning oscillator and the aging rate, And outputting to the digital synthesizer to adjust the signal accordingly;

The digital synthesizer is configured to output an output clock signal that is relatively stable with an input clock signal according to an adjustment signal from the control processor and an oscillation source signal from the oscillator; and the memory is configured to store a temperature value of the oscillator , the adjustment value of the digital synthesizer, and the correspondence between the two.

2. The phase locked loop of claim 1 wherein:

The control processor is further configured to: when the device is powered on, obtain an adjustment value corresponding to the current temperature value from the memory according to the current temperature value and transmit the adjustment value to the digital synthesizer.

3. A phase locked loop according to claim 1 or 2, characterized in that

The control processor is further configured to update the adjustment value currently outputted to the digital synthesizer according to the drift characteristics of the learned oscillator and the aging rate in the hold state.

4. The phase locked loop of claim 3, wherein the updating is performed in real time for prediction and correction.

5. The phase locked loop of claim 1 wherein:

The filter is a digital filter composed of software;

The temperature sensor is a temperature monitoring chip;

The digital controller is a direct digital synthesis device DDS.

6. The phase locked loop of claim 1, wherein the memory is comprised of an electrically erasable device, including an erasable programmable read only memory (EEPROM) or a flash memory (FLASH).

7. A method for improving clock accuracy by using a phase locked loop according to claim 1, wherein the frequency deviation of the oscillator is eliminated by monitoring the temperature of the oscillator and the adjusted value of the recorded digital synthesizer; After power-on, the adjustment value of the digital synthesizer corresponding to the current temperature is selected and written into the digital synthesizer to eliminate the initial frequency deviation of the oscillator.

8. The method according to claim 7, wherein the method further comprises: during normal tracking, the control processor self-learns the drift characteristics of the oscillator according to the adjusted value of the recorded digital synthesizer. Aging law.

The method of claim 8, wherein the method further comprises:

When the device is in the hold state, the control processor performs prediction correction in real time based on the obtained drift characteristics and aging rules.

10. The method of claim 9, wherein the process of performing prediction and correction in real time comprises:

The device selects an appropriate aging value from the aging characteristics for real-time compensation based on the current temperature and the aging characteristics of the oscillator under different temperature conditions obtained by self-learning under tracking conditions.