CN109188889B - Atomic clock 1PPS time synchronization method and system - Google Patents
Atomic clock 1PPS time synchronization method and system Download PDFInfo
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- CN109188889B CN109188889B CN201811241110.1A CN201811241110A CN109188889B CN 109188889 B CN109188889 B CN 109188889B CN 201811241110 A CN201811241110 A CN 201811241110A CN 109188889 B CN109188889 B CN 109188889B
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- G04F5/14—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
Abstract
The embodiment of the application provides a 1PPS time synchronization method of an atomic clock, which comprises the following steps: capturing a 1PPS pulse signal of an atomic clock; if the capture fails, entering a 1PPS failure holding state, and if the capture succeeds, judging whether the 1PPS pulse signal is a pseudo 1PPS pulse signal; if the captured signal is a pseudo-1 PPS pulse signal, the 1PPS pulse signal is captured again, and if the captured pulse signal is not a pseudo-1 PPS pulse signal, 1PPS time synchronization is performed based on a PID algorithm. According to the technical scheme, the captured 1PPS pulse signal is judged and recognized, the interference of the pseudo 1PPS pulse signal to the synchronization process is removed, and meanwhile, the problem of long-term aging drift of the atomic clock is kept overcome through the failure of the 1PPS, so that the frequency stability and the frequency accuracy of the atomic clock are improved.
Description
Technical Field
The application relates to the field of 1PPS signal synchronization and frequency calibration application, in particular to a method and a system for 1PPS time synchronization of an atomic clock, which are suitable for autonomous navigation terminal equipment and high-precision time synchronization and maintenance equipment.
Background
The chip atomic clock is used as a secondary frequency standard and has better long-term frequency stability. However, the frequency accuracy is 1E-10, which is still lower than the application requirement, and the long-term aging drift problem exists. In the prior art, time error data are measured by adopting methods such as a time-amplitude conversion method, a TDC method and the like to calibrate the frequency accuracy of the chip atomic clock, but due to the measurement limitation of the prior art, the requirements of 1PPS synchronization and frequency calibration of the chip atomic clock cannot be met. If the requirements of the 1PPS synchronization and the frequency calibration precision of the chip atomic clock are required to be ensured, a first-level frequency standard is used for calibrating the chip atomic clock, which is not beneficial to practical application.
Disclosure of Invention
In order to solve one of the problems, the application provides a method and a system for synchronizing atomic clock 1PPS time.
According to a first aspect of embodiments of the present application, there is provided an atomic clock 1PPS time synchronization method, including the steps of:
capturing a 1PPS pulse signal of an atomic clock;
if the capture fails, entering a 1PPS failure holding state, and if the capture succeeds, judging whether the 1PPS pulse signal is a pseudo 1PPS pulse signal;
if the captured signal is a pseudo-1 PPS pulse signal, the 1PPS pulse signal is captured again, and if the captured pulse signal is not a pseudo-1 PPS pulse signal, 1PPS time synchronization is performed based on a PID algorithm.
According to a second aspect of embodiments of the present application, there is provided a 1PPS time synchronization system for a chip atomic clock, the system including:
the acquisition module is used for acquiring a 1PPS pulse signal of the atomic clock, entering a 1PPS failure holding state if acquisition fails, and sending the acquired 1PPS pulse signal to the identification module if acquisition succeeds;
the identification module is used for judging whether the 1PPS pulse signal is a pseudo 1PPS pulse signal; if the captured signal is a pseudo-1 PPS pulse signal, the 1PPS pulse signal is captured again, and if the captured pulse signal is not the pseudo-1 PPS pulse signal, the 1PPS pulse signal is sent to a synchronization module;
and the synchronization algorithm module is used for carrying out 1PPS time synchronization based on the PID algorithm.
This application technical scheme can accurately catch 1PPS pulse signal to can eliminate the interference of pseudo-1 PPS pulse, have the fast advantage of 1PPS synchronous process convergence.
According to the technical scheme, the frequency accuracy of the atomic clock can be quickly calibrated, the frequency drift of the atomic clock is eliminated, and the frequency accuracy and the frequency stability of the chip atomic clock are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of the 1PPS time synchronization method according to the scheme;
FIG. 2 is a schematic diagram of the working state detection process of the atomic clock according to the scheme;
FIG. 3 is a schematic diagram of 1PPS pulse capture according to the present scheme;
FIG. 4 shows a timing diagram of the pseudo 1PPS pulse detection according to the present scheme;
fig. 5 shows a timing diagram of the 1PPS time error measurement according to the present scheme.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The core thought of the scheme is that the captured 1PPS pulse signal is judged and identified, the interference of the pseudo 1PPS pulse signal to the synchronization process is removed, and meanwhile, the problem of long-term aging drift of an atomic clock is kept to be solved through the failure of the 1PPS, so that the frequency stability and the frequency accuracy of the atomic clock are improved.
The scheme discloses a 1PPS time synchronization method of an atomic clock, which can be applied to 1PPS time synchronization of a chip atomic clock. The method adopts a 1PPS failure maintenance mode to protect the atomic clock under the condition that the atomic clock is abnormal, so that the reliability of the atomic clock is improved. In the synchronization process, the method can remove the pseudo-1 PPS pulse signal in the acquired atomic clock 1PPS pulse signal, and avoid the interference of the pseudo-signal to the synchronization. As shown in fig. 1, the method comprises the following specific steps:
step 1, detecting whether an atomic clock is in a locking state in real time
As shown in fig. 2, in the present embodiment, the working states of the atomic clock include: an initialization state, a temperature control state, a laser frequency locking state, a microwave frequency locking state and a locking state. In order to accurately detect the working state of the atomic clock, a probe is inserted into each working state, and a probe is also inserted into the output position of the atomic clock, so that when the probe detects that the current working state of the atomic clock is a locking state and the output frequency of the atomic clock is continuously stable, the atomic clock is judged to be in the locking state, and the 1PPS pulse capturing step can be carried out.
Step 2, judging whether the pulse signal is captured successfully or not
First, as shown in fig. 3, a preset capture program is used to capture the 1PPS pulse signal of the atomic clock; if the capture is successful, when the rising edge of the 1PPS pulse signal is captured, a capture signal is output, and the capture signal triggers the 1PPS synchronous output module to output a 1PPS _ out pulse as a synchronous signal of the 1PPS pulse; and outputting a Switch switching signal to control the charging and discharging process of the time error measuring module. If the capture fails, then the 1PPS failure hold state is entered.
Then, as shown in fig. 4, the pulse width and the period are obtained by measuring the captured 1PPS pulse signal with the time comb. The pulse width and the period of the standard 1PPS pulse signal are fixed values. Therefore, the captured 1PPS pulse signal is compared with the standard 1PPS pulse signal, and if the captured 1PPS pulse signal and the standard 1PPS pulse signal are completely identical, the captured 1PPS pulse signal is not a false pulse signal, and if the captured 1PPS pulse signal and the standard 1PPS pulse signal are not completely identical, the captured 1PPS pulse signal can be determined to be the false pulse signal. By the method, the problem that the chip atomic clock is unlocked or fails due to misoperation caused by the interference of the pseudo-1 PPS pulse signal can be solved, so that the reliability of the chip atomic clock is improved.
In this embodiment, the 1PPS failure holding state is realized by a 1PPS failure holding algorithm; specifically, the 1PPS failure holding algorithm comprises an aging model of the chip atomic clock, the aging model is obtained by experimental tests through least square fitting, and the aging model is solidified in the 1PPS failure holding algorithm. When no 1PPS pulse signal exists, the 1PPS failure holding algorithm monitors the frequency feedback process by using a probe and corrects the frequency feedback by using an aging model, so that the frequency drift caused by aging is eliminated.
Step 3, measuring 1PPS synchronous time error data
As shown in fig. 5, the 1PPS _ out pulse signal output by the synchronous output module and the standard 1PPS pulse signal are simultaneously input to the RS flip-flop, the phase error detection of the rising edges of the 1PPS pulse and the 1PPS _ out pulse is realized through setting and resetting, the amplification of the time error can be realized through the charging and discharging process of the output signal of the RS flip-flop, the charging and discharging time sequence is controlled by the Switch signal, and the discharging time is measured by using the clock comb. The interval between the clock combs is 100ns, the maximum measurement time is 1s, and when the measurement range is 0-1 us, the maximum amplification factor can reach 106Resolution can be up toOn the order of 0.1 ps. The frequency calibration range can be +/-1E-6 by the method; 1PPS synchronization precision can be realized within 50ns within 1 second; the synchronization is carried out for 20 minutes, so that the frequency accuracy of 1E-12, 1PPS synchronization and the frequency calibration rate are higher than those of other algorithms; the time error signal is amplified in the charging and discharging process, so that the measurement precision is improved and is higher than that of the traditional time-amplitude measurement method and TDC measurement method.
Step 4, carrying out 1PPS time synchronization based on PID algorithm
In this example, the 1PPS time synchronization uses a PID-like algorithm for time synchronization. The time error is tnThe proportionality coefficient and the differential coefficient are respectively kp、kd. The PID-like algorithm is as follows:
yn＝kp·Sum_P(n)+kd·Sum_D(n) (1)
wherein the proportional term Sum _ p (n) ═ tn+kpSum _ P (n-1) represents the time error term of the 1PPS pulse signal, and includes both the proportional term and the integral term, and the weight of the current measurement value is the largest, and the weight of the measurement value which is farther away is smaller, so that the quick convergence of the time synchronization process is realized, and the steady-state error of the integral term is eliminated.
Differentiation term Sum _ d (n) ═ tn-tn-1)+kdSum _ D (n-1) represents the frequency error of the chip atomic clock and a frequency error integral term, the current frequency accuracy weight is the largest, the frequency output state of the chip atomic clock can be reflected better, and the frequency accuracy can be calibrated quickly by using the term. The algorithm can reflect 1PPS time error and frequency error, and also comprises a time error integral term and an integral term of the frequency error, so that the rapid convergence of the algorithm can be promoted, the oscillation period is reduced, and the rapid convergence of a chip atomic clock can realize the calibration of 1PPS time synchronization and frequency accuracy.
The method of the embodiment can be applied to chip atomic clocks, other types of atomic clocks and time synchronization of voltage-controlled crystal oscillators.
In this embodiment, a system for synchronizing atomic clock 1PPS time is further disclosed, and the system includes: the device comprises a state detection module, a capture module, an identification module, an error detection module and a synchronization module; wherein the content of the first and second substances,
and the state detection module determines whether the atomic clock is in a locking state or not based on the probes preset in each working state and the output position of the atomic clock, and starts to capture the 1PPS pulse signal of the atomic clock if the atomic clock is in the locking state.
The capture module captures a 1PPS pulse signal of the atomic clock based on a preset capture program; if the capture is successful, when the rising edge of the 1PPS pulse signal is captured, a capture signal is output, and the capture signal triggers the 1PPS synchronous output module to output a 1PPS _ out pulse as a synchronous signal of the 1PPS pulse; and outputting a Switch switching signal to control the charging and discharging process of the time error measuring module. If the capture fails, then the 1PPS failure hold state is entered.
The identification module is used for judging whether the 1PPS pulse signal is a pseudo-1 PPS pulse signal or not, namely comparing the captured 1PPS pulse signal with a standard 1PPS pulse signal, if the two pulse signals are completely consistent, the captured 1PPS pulse signal is not a pseudo-pulse signal, and if the two pulse signals are not completely consistent, the captured 1PPS pulse signal can be judged to be a pseudo-pulse signal; and if the captured pulse signal is not the pseudo 1PPS pulse signal, sending the 1PPS pulse signal to the synchronization module.
The error detection module is used for detecting the phase error of the rising edge of the captured 1PPS pulse signal and the 1PPS pulse signal to obtain a time error; and (3) amplifying the time error through the charging and discharging process by taking the time interval of 100ns and the maximum measurement time of 1s as a measurement standard to obtain time error data.
The synchronization module is used for carrying out 1PPS time synchronization based on a PID algorithm; the PID algorithm is as follows:
yn＝kp·Sum_P(n)+kd·Sum_D(n) (1)
wherein the proportional term Sum _ p (n) ═ tn+kpSum _ P (n-1) represents a time error term of the 1PPS pulse signal, and a differential term Sum _ d (n) (t) isn-tn-1)+kdSum _ D (n-1) represents the frequency error of the chip atomic clock and the frequency error integral term.
In conclusion, the method can accurately capture the 1PPS pulse signal, can eliminate the interference of the false 1PPS pulse, and has the advantage of fast convergence of the 1PPS synchronization process. By utilizing the scheme, the frequency accuracy of the chip atomic clock can be quickly calibrated, the frequency drift of the chip atomic clock is eliminated, and the frequency accuracy and the frequency stability of the chip atomic clock are improved. The scheme has the advantages of simple structure, low power consumption, high precision and short synchronization and calibration time, and is suitable for time synchronization of atomic clocks or piezoelectric crystal oscillators of the same type.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.
Claims (8)
1. A1 PPS time synchronization method of an atomic clock is characterized by comprising the following steps:
detecting whether the atomic clock is in a locking state in real time, and if so, starting capturing a 1PPS pulse signal of the atomic clock;
capturing a 1PPS pulse signal of an atomic clock;
if the capture fails, entering a 1PPS failure holding state, wherein the 1PPS failure holding state is realized by a 1PPS failure holding algorithm; if the capture is successful, judging whether the 1PPS pulse signal is a pseudo 1PPS pulse signal;
if the captured signal is a pseudo-1 PPS pulse signal, the 1PPS pulse signal is captured again, and if the captured pulse signal is not the pseudo-1 PPS pulse signal, the 1PPS time synchronization is carried out based on a PID-like algorithm;
the PID-like algorithm is as follows:
yn＝kp·Sum_P(n)+kd·Sum_D(n)
wherein, ynIs the output quantity of the PID algorithm of the n time class, tnTime error, k, of 1PPS signal at time npIs a proportionality coefficient, kdIs a differential coefficient;
the proportional term Sum _ p (n) ═ tn+kpSum _ P (n-1) represents a time error term of the 1PPS pulse signal, and a differential term Sum _ d (n) (t) isn-tn-1)+kdSum _ D (n-1) represents the frequency error of the chip atomic clock and the frequency error integral term.
2. The 1PPS time synchronization method of claim 1, wherein the step of capturing the 1PPS pulse signal of the atomic clock comprises:
capturing the rising edge of the atomic clock 1PPS pulse signal;
the 1PPS _ out pulse signal and the switch signal are synchronously output as the switching signals of the 1PPS pulse for the charging and discharging processes.
3. The method of claim 1PPS time synchronization according to claim 1, wherein the step of determining whether the 1PPS pulse signal is a pseudo 1PPS pulse signal comprises:
measuring the pulse width and period of the captured 1PPS pulse signal and comparing it with the pulse width and period values of a standard 1PPS pulse signal;
if they match, they are not pseudo 1PPS pulse signals, and if they do not match, they are pseudo 1PPS pulse signals.
4. The 1PPS time synchronization method of claim 1, the working state of the atomic clock comprising: the method comprises the following steps of initialization state, temperature control state, laser frequency locking state, microwave frequency locking state and locking state, and is characterized in that the step of detecting whether the atomic clock is locked in real time comprises the following steps:
inserting a probe in each working state of the atomic clock and the output position of the atomic clock;
and if the working state of the current atomic clock is detected to be the locking state and the output frequency of the atomic clock is stable, determining that the atomic clock is in the locking state.
5. The method of claim 1PPS time synchronization according to claim 1, wherein said step of entering a 1PPS synchronization state if the captured pulse signal is not a pseudo 1PPS pulse signal further comprises:
time error data of 1PPS synchronization is measured.
6. The 1PPS time synchronization method of claim 5, said step of measuring 1PPS synchronized time error data comprising:
detecting the phase error of the rising edge of the captured 1PPS pulse signal and the 1PPS pulse signal to obtain a time error;
and (3) amplifying the time error through the charging and discharging process by taking the time interval of 100ns and the maximum measurement time of 1s as a measurement standard to obtain time error data.
7. An atomic clock 1PPS time synchronization system, comprising:
the state detection module is used for detecting whether the atomic clock is in a locking state or not in real time, and if so, the capture module starts to capture a 1PPS pulse signal of the atomic clock;
the capture module captures a 1PPS pulse signal of the atomic clock, and if the capture fails, the capture module enters a 1PPS failure holding state, wherein the 1PPS failure holding state is realized through a 1PPS failure holding algorithm; if the capturing is successful, sending the captured 1PPS pulse signal to an identification module;
the identification module is used for judging whether the 1PPS pulse signal is a pseudo 1PPS pulse signal; if the captured signal is a pseudo-1 PPS pulse signal, the 1PPS pulse signal is captured again, and if the captured pulse signal is not the pseudo-1 PPS pulse signal, the 1PPS pulse signal is sent to a synchronization module;
the synchronization algorithm module carries out 1PPS time synchronization based on a PID-like algorithm, and the PID-like algorithm is as follows:
yn＝kp·Sum_P(n)+kd·Sum_D(n)
wherein, ynIs the output quantity of the PID algorithm of the n time class, tnTime error, k, of 1PPS signal at time npIs a proportionality coefficient, kdIs a differential coefficient;
the proportional term Sum _ p (n) ═ tn+kpSum _ P (n-1) represents a time error term of the 1PPS pulse signal, and a differential term Sum _ d (n) (t) isn-tn-1)+kdSum _ D (n-1) represents the frequency error of the chip atomic clock and the frequency error integral term.
8. The 1PPS time synchronization system of claim 7 further comprising: the error detection module is used for detecting the phase error of the rising edge of the captured 1PPS pulse signal and the 1PPS pulse signal to obtain a time error; and (3) amplifying the time error through the charging and discharging process by taking the time interval of 100ns and the maximum measurement time of 1s as a measurement standard to obtain time error data.
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