CN109188889A - A kind of atomic clock 1PPS method for synchronizing time and system - Google Patents
A kind of atomic clock 1PPS method for synchronizing time and system Download PDFInfo
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- CN109188889A CN109188889A CN201811241110.1A CN201811241110A CN109188889A CN 109188889 A CN109188889 A CN 109188889A CN 201811241110 A CN201811241110 A CN 201811241110A CN 109188889 A CN109188889 A CN 109188889A
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- 1pps
- pulse signal
- atomic clock
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
- G04F5/14—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
Abstract
Provide a kind of atomic clock 1PPS method for synchronizing time in the embodiment of the present application, the step of this method includes: the 1PPS pulse signal for capturing atomic clock；If capture failure, enters 1PPS failure hold mode if acquisition success and judge whether the 1PPS pulse signal is pseudo- 1PPS pulse signal；If the signal of capture is pseudo- 1PPS pulse signal, recapture 1PPS pulse signal carries out 1PPS time synchronization based on pid algorithm if the pulse signal of capture is not pseudo- 1PPS pulse signal.Herein described technical solution is by carrying out judgement identification to the 1PPS pulse signal of capture, remove interference of the puppet 1PPS pulse signal to synchronizing process, simultaneously, it keeps overcoming long-term ageing drifting problem existing for atomic clock by 1PPS failure, so as to improve the frequency stability and frequency accuracy of atomic clock.
Description
Technical field
This application involves the synchronization of 1PPS signal and frequency calibration application fields, in particular to a kind of to be suitable for independent navigation end
End equipment, precise synchronization and atomic clock 1PPS method for synchronizing time and system in holding equipment.
Background technique
Chip atomic clock has preferable long-term frequency stability as Second Level Frequency standard.But frequency accuracy
For 1E-10, it is still below application demand, and there are long-term ageing drifting problems.In the prior art, m- amplitude transformation approach when use
Time error information is measured with the methods of TDC method, to the frequency accuracy of calibration chip atomic clock, still, by
In the limitation of existing method measurement, lead to not meet chip atomic clock 1PPS synchronization and frequency calibration requirement.To guarantee
The synchronous requirement with the calibration accuracy of frequency of chip atomic clock 1PPS, need to use primary frequency standard to calibrate it, be unfavorable for reality
Border application.
Summary of the invention
One of in order to solve the above problem, this application provides a kind of atomic clock 1PPS method for synchronizing time and systems.
According to the first aspect of the embodiment of the present application, a kind of atomic clock 1PPS method for synchronizing time, this method are provided
The step of include:
Capture the 1PPS pulse signal of atomic clock；
If capture failure, enters 1PPS failure hold mode if acquisition success and whether judge the 1PPS pulse signal
For pseudo- 1PPS pulse signal；
If the signal of capture is pseudo- 1PPS pulse signal, recapture 1PPS pulse signal, if the pulse signal of capture
It is not pseudo- 1PPS pulse signal, then 1PPS time synchronization is carried out based on pid algorithm.
According to the second aspect of the embodiment of the present application, a kind of 1PPS time synchronization system for chip atomic clock is provided
System, the system include:
Trapping module captures the 1PPS pulse signal of atomic clock, if capture failure, enters 1PPS failure hold mode,
If acquisition success, the 1PPS pulse signal that will be captured is sent to identification module；
Identification module judges whether the 1PPS pulse signal is pseudo- 1PPS pulse signal；If the signal of capture is pseudo- 1PPS
Pulse signal, then recapture 1PPS pulse signal, if the pulse signal of capture is not pseudo- 1PPS pulse signal, by 1PPS arteries and veins
It rushes signal and is sent to synchronization module；
Synchronized algorithm module carries out 1PPS time synchronization based on pid algorithm.
Herein described technical solution can accurately capture 1PPS pulse signal, and can eliminate the interference of pseudo- 1PPS pulse,
It is fast to have the advantages that 1PPS synchronizing process restrains.
Herein described technical solution can realize the frequency accuracy of quickly calibrated atomic clock, eliminate the frequency drift of atomic clock
It moves, improves the frequency accuracy and frequency stability of chip atomic clock.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, this Shen
Illustrative embodiments and their description please are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the flow chart of 1PPS method for synchronizing time described in this programme；
Fig. 2 shows the schematic diagrames of the working condition detection process of atomic clock described in this programme；
Fig. 3 shows the schematic diagram of 1PPS pulse capture described in this programme；
Fig. 4 shows the timing diagram of puppet 1PPS pulse detection described in this programme；
Fig. 5 shows the timing diagram of the measurement of 1PPS time error described in this programme.
Specific embodiment
In order to which technical solution in the embodiment of the present application and advantage is more clearly understood, below in conjunction with attached drawing to the application
Exemplary embodiment be described in more detail, it is clear that described embodiment be only the application a part implement
Example, rather than the exhaustion of all embodiments.It should be noted that in the absence of conflict, embodiment and reality in the application
The feature applied in example can be combined with each other.
The core ideas of this programme is to remove puppet 1PPS pulse by carrying out judgement identification to the 1PPS pulse signal of capture
Interference of the signal to synchronizing process, meanwhile, it keeps overcoming long-term ageing drifting problem existing for atomic clock by 1PPS failure, from
And improve the frequency stability and frequency accuracy of atomic clock.
This programme discloses a kind of atomic clock 1PPS method for synchronizing time, and this method can be applied to the 1PPS of chip atomic clock
Time synchronization.This method protects atomic clock in the case where atomic clock exception in such a way that 1PPS failure is kept, from
And improve the reliability of atomic clock.This method can remove the atomic clock 1PPS pulse signal that capture obtains in synchronizing process
In pseudo- 1PPS pulse signal, avoid false signal interference caused by synchronization.As shown in Figure 1, specific step is as follows for this method:
Whether step 1, real-time detection atomic clock are in the lock state
As shown in Fig. 2, in the present solution, the working condition of atomic clock includes: init state, temperature control status, laser
Frequency-locked state, microwave frequency-locked state and lock state.In order to accurately detect the working condition that atomic clock is in, in each work
Make to be inserted into probe in state, meanwhile, it is similarly inserted into probe in the output position of atomic clock, as a result, when probe detects atom
The current working status of clock be lock state, and atomic clock output frequency it is continual and steady when, then determine atomic clock for lock shape
State can enter 1PPS pulse capture step.
Step 2, judge pulse signal capture whether acquisition success
Firstly, as shown in figure 3, being captured using capture program is preset to the 1PPS pulse signal of atomic clock；If
Acquisition success, when capturing 1PPS pulse signal rising edge, output capture signal, capture signal triggers 1PPS synchronous output module
Export synchronization signal of the 1PPS_out pulse as 1PPS pulse；It exports Switch switching signal and controls time error measurement module
Charge and discharge process.If capture failure, enter 1PPS failure hold mode.
Then, as shown in figure 4, being measured using time comb to the obtained 1PPS pulse signal of capture, obtain pulsewidth and
Period.The pulse width of standard 1PPS pulse signal and period are all fixed values.Therefore, 1PPS pulse signal capture obtained
It is compared with standard 1PPS pulse signal, if the two is completely the same, the 1PPS pulse signal captured is not false pulse
Signal, if the two be not it is completely the same, may determine that 1PPS pulse signal that capture obtains is false pulse signal.By upper
The mode of stating can eliminate chip atomic clock losing lock or failure caused by maloperation caused by pseudo- 1PPS pulse signal interference, to mention
The reliability of high chip atomic clock.
In the present embodiment, 1PPS failure hold mode is to fail that algorithm is kept to realize by 1PPS；Specifically, 1PPS loses
Effect keeps the Ageing Model in algorithm comprising chip atomic clock, which is obtained by experiment test by least square method fitting
, and be solidificated in 1PPS failure and keep in algorithm.When no 1PPS pulse signal, 1PPS failure keeps algorithm to monitor using probe
Frequency feedback process, and fed back using Ageing Model frequency of amendment, to eliminate frequency drift caused by aging.
Step 3, measurement 1PPS synchronous time error data
As shown in figure 5, simultaneously by the 1PPS_out pulse signal of synchronous output module output and standard 1PPS pulse signal
Rest-set flip-flop is inputted, the phase error detection of 1PPS pulse and 1PPS_out rising edge of a pulse, RS touching are realized by set-reset
Hair device output signal can realize the amplification of time error by charge and discharge process, and charge and discharge timing is by Switch switching signal control
System combs measurement discharge time using clock.Clock comb interval 100ns, maximum measuring time 1s, in 0~1us of measurement range,
Amplification factor maximum can reach 106, resolution ratio can reach 0.1ps magnitude.Can realize through the above way frequency calibration range ±
1E-6；1PPS synchronization accuracy 50ns can be realized within 1 second；Synchronous 20 minutes, it can be achieved that frequency accuracy 1E-12,1PPS it is synchronous and
Frequency calibration rate is higher than other algorithms；The amplification of time error signal is realized using charge and discharge process, to improve measurement essence
Degree, and measurement accuracy is higher than Conventional temporal-amplitude measurement method, TDC measurement method.
Step 4 carries out 1PPS time synchronization based on pid algorithm
In this example, 1PPS time synchronization carries out time synchronization using class pid algorithm.Time error is tn, proportionality coefficient,
Differential coefficient is respectively kp、kd.Class pid algorithm are as follows:
yn=kp·Sum_P(n)+kd·Sum_D(n) (1)
Wherein, proportional Sum_P (n)=tn+kpSum_P (n-1) indicates the time error item of 1PPS pulse signal, both
Proportional is contained and has contained integral term again, and the weight of current measurement value is maximum, the weight of measured value more remote is smaller, real
The fast convergence of existing time synchronization process, and eliminate the steady-state error of integral term.
Differential term Sum_D (n)=(tn-tn-1)+kdThe frequency error and frequency of Sum_D (n-1) expression chip atomic clock
Rate error value product subitem, current frequency accuracy weight is maximum, can more reflect the rate-adaptive pacemaker state of chip atomic clock, utilize this
Item can be with quickly calibrated frequency accuracy.The algorithm can reflect 1PPS time error and frequency error and time error
The integral term of integral term and frequency error can promote the fast convergence of algorithm, reduces cycle of oscillation, receives chip atomic clock quickly
Hold back the calibration for realizing 1PPS time synchronization and frequency accuracy.
The present embodiment the method can also be applied to other kinds of original other than it can be applied to chip atomic clock
In secondary clock, the time synchronization of voltage controlled crystal oscillator also can be applied to.
In the present embodiment, a kind of atomic clock 1PPS clock synchronization system is further disclosed, which includes: state-detection
Module, trapping module, identification module, error sensing module and synchronization module；Wherein,
State detection module is based on being preset in the probe of each working condition and atomic clock output position, determines atom
Whether clock is lock state, if so, starting the 1PPS pulse signal of capture atomic clock.
Trapping module is based on preset capture program, captures to the 1PPS pulse signal of atomic clock；If capture
Success, when capturing 1PPS pulse signal rising edge, output capture signal, capture signal triggering 1PPS synchronous output module output
Synchronization signal of the 1PPS_out pulse as 1PPS pulse；Output Switch switching signal control time error measurement module fills
Discharge process.If capture failure, enter 1PPS failure hold mode.
Identification module judges whether the 1PPS pulse signal is pseudo- 1PPS pulse signal, i.e., the 1PPS arteries and veins obtained capture
It rushes signal to compare with standard 1PPS pulse signal, if the two is completely the same, the 1PPS pulse signal captured is not
False pulse signal, if the two be not it is completely the same, may determine that 1PPS pulse signal that capture obtains is false pulse signal；
If the pulse signal of capture is not pseudo- 1PPS pulse signal, 1PPS pulse signal is sent to synchronization module.
Error sensing module, for carrying out rising edge phase mistake to the 1PPS pulse signal and 1PPS pulse signal that capture
Difference is detected, and time error is obtained；With time interval 100ns, maximum measuring time 1s is measurement standard, passes through charge and discharge
Journey amplifies processing to time error, obtains time error data.
Synchronization module carries out 1PPS time synchronization based on pid algorithm；The pid algorithm are as follows:
yn=kp·Sum_P(n)+kd·Sum_D(n) (1)
Wherein, proportional Sum_P (n)=tn+kpSum_P (n-1) indicates the time error item of 1PPS pulse signal, micro-
Itemize Sum_D (n)=(tn-tn-1)+kdSum_D (n-1) indicates the frequency error and frequency error integral of chip atomic clock
?.
In conclusion this method can accurately capture 1PPS pulse signal, and can eliminate the interference of pseudo- 1PPS pulse, have
1PPS synchronizing process restrains fast advantage.The frequency accuracy of quickly calibrated chip atomic clock can be realized using this programme, eliminated
The frequency drift of chip atomic clock improves the frequency accuracy and frequency stability of chip atomic clock.Program structure is simple, function
It consumes that low, precision is high, synchronous and prover time is short, is suitble to the time synchronization of same type atomic clock or piezoelectricity crystal oscillator.
The application is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The above is only the embodiment of the present invention, are not intended to restrict the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent substitution, improvement and etc. done, be all contained in apply pending scope of the presently claimed invention it
It is interior.
Claims (10)
1. a kind of atomic clock 1PPS method for synchronizing time, which is characterized in that the step of this method includes:
Capture the 1PPS pulse signal of atomic clock；
If capture failure, enter 1PPS failure hold mode, if acquisition success, judges whether the 1PPS pulse signal is pseudo-
1PPS pulse signal；
If the signal of capture is pseudo- 1PPS pulse signal, recapture 1PPS pulse signal, if the pulse signal of capture is not
Pseudo- 1PPS pulse signal then carries out 1PPS time synchronization based on pid algorithm.
2. 1PPS method for synchronizing time according to claim 1, which is characterized in that the 1PPS of the capture chip atomic clock
The step of pulse signal includes:
Capture the rising edge of atomic clock 1PPS pulse signal；
Synchronism output 1PPS_out pulse signal and switch signal are as the synchronization signal of 1PPS pulse and for charge and discharge
The switching signal of journey.
3. 1PPS method for synchronizing time according to claim 1, which is characterized in that described judgement 1PPS pulse signal is
It is no to include: for the step of puppet 1PPS pulse signal
Pulse width and the period of the 1PPS pulse signal captured are measured, and it is wide with the pulse of standard 1PSS pulse signal
Degree and periodic quantity are compared；
It is not pseudo- 1PPS pulse signal if completely the same, if not quite identical, for pseudo- 1PPS pulse signal.
4. 1PPS method for synchronizing time according to claim 1, which is characterized in that the 1PPS pulse of the capture atomic clock
Before the step of signal further include:
Whether real-time detection atomic clock is lock state, if so, starting the 1PPS pulse signal of capture atomic clock.
5. 1PPS method for synchronizing time according to claim 4, the working condition of the atomic clock includes: initialization shape
State, temperature control status, laser frequency-locked state, microwave frequency-locked state and lock state, which is characterized in that the real-time detection is former
The step of whether secondary clock locks include:
In each working condition of atomic clock and probe is inserted into the output position of atomic clock；
If detecting, the working condition of current atomic clock is lock state, and when the output frequency stabilization of atomic clock, it is determined that former
Secondary clock is lock state.
6. 1PPS method for synchronizing time according to claim 1, which is characterized in that if the pulse signal of the capture is not
Pseudo- 1PPS pulse signal, then enter 1PPS synchronous regime the step of after further include:
Measure the synchronous time error data of 1PPS.
7. 1PPS method for synchronizing time according to claim 1, the step of the measurement 1PPS synchronous time error data
Suddenly include:
Rising edge phase error is carried out with 1PPS pulse signal to the 1PPS pulse signal captured to detect, and obtains time mistake
Difference；
With time interval 100ns, maximum measuring time 1s is measurement standard, is amplified by charge and discharge process to time error
Processing obtains time error data.
8. a kind of atomic clock 1PPS clock synchronization system, which is characterized in that the system includes:
Trapping module captures the 1PPS pulse signal of atomic clock, if capture failure, enters 1PPS failure hold mode, if catching
It succeeds, then the 1PPS pulse signal that will be captured is sent to identification module；
Identification module judges whether the 1PPS pulse signal is pseudo- 1PPS pulse signal；If the signal of capture is pseudo- 1PPS pulse
Signal, then recapture 1PPS pulse signal believes 1PPS pulse if the pulse signal of capture is not pseudo- 1PPS pulse signal
Number it is sent to synchronization module；
Synchronized algorithm module carries out 1PPS time synchronization based on pid algorithm.
9. 1PPS clock synchronization system according to claim 8, which is characterized in that the system further include: state-detection mould
Whether block, real-time detection atomic clock are lock state, if so, starting the 1PPS pulse signal of capture atomic clock.
10. 1PPS clock synchronization system according to claim 8, which is characterized in that the system further include: error-detecting mould
Block is detected for carrying out rising edge phase error to the 1PPS pulse signal captured and 1PPS pulse signal, when acquisition
Between error；It is measurement standard with time interval 100ns, maximum measuring time 1s, time error is carried out by charge and discharge process
Enhanced processing obtains time error data.
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| CN201811241110.1A CN109188889B (en) | 2018-10-24 | 2018-10-24 | Atomic clock 1PPS time synchronization method and system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110611544A (en) * | 2019-09-12 | 2019-12-24 | 成都府河电力自动化成套设备有限责任公司 | Method and device for accurately timing by utilizing RS232 serial port |
| CN117111434A (en) * | 2023-08-17 | 2023-11-24 | 湖南时空信安科技有限公司 | Clock performance evaluation method and device and terminal equipment |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5029152A (en) * | 1988-02-22 | 1991-07-02 | Hitachi, Ltd. | Apparatus for detecting delete patterns of optical discs |
| CN1859004A (en) * | 2005-12-01 | 2006-11-08 | 华为技术有限公司 | Phase-locked loop and method for improving clock accuracy |
| CN102780555A (en) * | 2011-05-13 | 2012-11-14 | 中兴通讯股份有限公司 | Clock synchronization method and device in communication system |
| CN103152040A (en) * | 2013-01-31 | 2013-06-12 | 江汉大学 | Method for reducing atomic energy level transition dynamic detection frequency range of atomic clock |
| CN103269262A (en) * | 2013-04-01 | 2013-08-28 | 柳州市达迪通信设备有限公司 | Time-keeping method of time synchronization device |
| JP2014193063A (en) * | 2013-03-28 | 2014-10-06 | Seiko Epson Corp | Protective relay device and power system protective system |
| CN105049040A (en) * | 2015-06-24 | 2015-11-11 | 中国科学院武汉物理与数学研究所 | Method for correcting output frequency of CPT (Coherent Population Trapping) atomic clock through GNSS(Global Navigation Satellite System) |
| CN106712768A (en) * | 2016-12-12 | 2017-05-24 | 深圳市紫光同创电子有限公司 | Deburring frequency locking circuit |
| CN107026702A (en) * | 2017-04-20 | 2017-08-08 | 中国南方电网有限责任公司电网技术研究中心 | The punctual method and apparatus of high accuracy |
| US20180003826A1 (en) * | 2015-06-12 | 2018-01-04 | Alberto Daniel Lacaze | Atomic clock base navigation system for on-the-move radar, obfuscation, sensing, and ad-hoc third party localization |
-
2018
- 2018-10-24 CN CN201811241110.1A patent/CN109188889B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5029152A (en) * | 1988-02-22 | 1991-07-02 | Hitachi, Ltd. | Apparatus for detecting delete patterns of optical discs |
| CN1859004A (en) * | 2005-12-01 | 2006-11-08 | 华为技术有限公司 | Phase-locked loop and method for improving clock accuracy |
| CN102780555A (en) * | 2011-05-13 | 2012-11-14 | 中兴通讯股份有限公司 | Clock synchronization method and device in communication system |
| CN103152040A (en) * | 2013-01-31 | 2013-06-12 | 江汉大学 | Method for reducing atomic energy level transition dynamic detection frequency range of atomic clock |
| JP2014193063A (en) * | 2013-03-28 | 2014-10-06 | Seiko Epson Corp | Protective relay device and power system protective system |
| CN103269262A (en) * | 2013-04-01 | 2013-08-28 | 柳州市达迪通信设备有限公司 | Time-keeping method of time synchronization device |
| US20180003826A1 (en) * | 2015-06-12 | 2018-01-04 | Alberto Daniel Lacaze | Atomic clock base navigation system for on-the-move radar, obfuscation, sensing, and ad-hoc third party localization |
| CN105049040A (en) * | 2015-06-24 | 2015-11-11 | 中国科学院武汉物理与数学研究所 | Method for correcting output frequency of CPT (Coherent Population Trapping) atomic clock through GNSS(Global Navigation Satellite System) |
| CN106712768A (en) * | 2016-12-12 | 2017-05-24 | 深圳市紫光同创电子有限公司 | Deburring frequency locking circuit |
| CN107026702A (en) * | 2017-04-20 | 2017-08-08 | 中国南方电网有限责任公司电网技术研究中心 | The punctual method and apparatus of high accuracy |
Non-Patent Citations (8)
| Title |
|---|
| DONG HOU ET AL.: "Analysis of Long-Term Phase-Locking Technique", 《IEEE JOURNAL OF QUANTUM ELECTRONICS》 * |
| 姚龙鑫: "伪卫星脉冲信号设计及兼容性分析", 《中国优秀硕士学位论文全文数据库（信息科技辑）》 * |
| 徐世许等: "INS/GPS 组合导航系统的数据精确同步方法", 《中国惯性技术学报》 * |
| 易雄书: "基于GPS的DMB-TH单频网时间同步系统研究", 《中国优秀硕士学位论文全文数据库（基础科学辑）》 * |
| 李炎: "惯导模拟系统硬件平台的设计及其测试技术研究", 《中国优秀硕士学位论文全文数据库（信息科技辑）》 * |
| 石金芬编著: "《电子基础技术》", 31 August 2016, 北京：北京理工大学出版社 * |
| 程泽涛等: "基于锁相环技术的智能变电站时钟同步方案", 《通信电源技术》 * |
| 赵建华编著: "《现代安全监测技术》", 31 August 2006, 中国科学技术大学出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110611544A (en) * | 2019-09-12 | 2019-12-24 | 成都府河电力自动化成套设备有限责任公司 | Method and device for accurately timing by utilizing RS232 serial port |
| CN117111434A (en) * | 2023-08-17 | 2023-11-24 | 湖南时空信安科技有限公司 | Clock performance evaluation method and device and terminal equipment |
| CN117111434B (en) * | 2023-08-17 | 2024-03-29 | 湖南时空信安科技有限公司 | Clock performance evaluation method and device and terminal equipment |
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| CN109188889B (en) | 2021-02-12 |
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