CN108063618B - VCO automatic calibration circuit and method - Google Patents
VCO automatic calibration circuit and method Download PDFInfo
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- CN108063618B CN108063618B CN201711387872.8A CN201711387872A CN108063618B CN 108063618 B CN108063618 B CN 108063618B CN 201711387872 A CN201711387872 A CN 201711387872A CN 108063618 B CN108063618 B CN 108063618B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention discloses an automatic VCO (voltage controlled oscillator) calibration circuit which comprises a reference clock counter, a feedback clock counter, a state machine, a voltage controlled oscillator, a frequency divider and a reset module, wherein the reference clock counter, the feedback clock counter, the reset module and the voltage controlled oscillator are all connected with the state machine, and the reset module, the voltage controlled oscillator and the feedback clock counter are all connected with the frequency divider; the state machine resets the reference clock counter and the feedback clock counter in a reset state, enables the reset module to reset the frequency divider, enables the reference clock counter and the feedback clock counter to count simultaneously, records a feedback count value obtained by the feedback counter when the reference clock counter counts to a preset count value, and finds the optimal capacitor array value of the voltage-controlled oscillator through a dichotomy according to a comparison result of the preset count value and the feedback count value. The invention eliminates the problem that the initial phase of the feedback clock is uncertain, thereby reducing the counting accuracy; the time for automatic calibration can be shortened.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a VCO automatic calibration circuit and method.
Background
At present, modern communication technology is changing day by day, and various wireless communication standards are emerging. In the receiving and transmitting of signals, the frequency synthesizer is an important module for generating stable, accurate and low-noise local oscillation signals and realizing frequency mixing with the received (transmitting) signals. To achieve a larger signal bandwidth, the local oscillator signal is required to cover a large range. A Voltage Controlled Oscillator (VCO) for local oscillator generation generally uses a capacitive-inductive resonant structure, which can achieve a noise performance much better than that of a ring oscillator. The control voltage of the oscillator adjusts the frequency of the output by controlling the capacitance value of the varactor. The larger the capacitance, the lower the output frequency, and the smaller the capacitance, the higher the output frequency. The change in frequency with respect to the change in control voltage is referred to as a voltage controlled gain, as shown in fig. 2. A larger voltage controlled gain means that the same control voltage variation can result in a larger output frequency variation.
The frequency variation range of the varactor can be small, and meanwhile, the performance of noise, stray and the like can be deteriorated due to large voltage-controlled gain. Therefore, a switched capacitor array is generally added to the circuit, and when the switches are all closed, the capacitor array is disconnected from the circuit, and the total capacitance of the capacitor array is 0. The more switches that are open, the greater the capacitance value of the capacitor array. The capacitance array can obtain different capacitance values, and a larger output frequency range can be realized by matching the change of the capacitance value of the varactor. The method requires that the output frequency ranges of adjacent capacitor arrays must have certain overlap to ensure the continuity of the coverage frequency band; secondly, when the required frequency changes, the circuit can automatically find out the appropriate value of the capacitor array.
The Automatic Frequency Calibration (AFC) method for finding a proper capacitor array mainly includes an open-loop counting method, a switch simulation method, a closed-loop locking method, and the like. The time required for the closed-loop locking method is very long, the accuracy is affected by the open-loop simulation method due to device mismatch and comparator misadjustment, and the open-loop counting method is more common.
However, the existing solutions have the following drawbacks:
the traditional counting mode needs to read data across clock domains, and the problem of metastable state is easily caused. In counting, because the two clock frequencies and phases are independent, the uncertainty of the initial phase may introduce a counting error, as shown in fig. 1, fref is a reference clock, and a feedback clock fdiv with the same frequency, because the initial phases are different, the counting value may have an error of 1. The fast vco frequency calibration techniques for the pll applications reduce errors caused by phase uncertainty by using a multi-phase clock, and the method increases the complexity of the circuit.
Disclosure of Invention
In order to overcome the disadvantages of the prior art, an object of the present invention is to provide an automatic calibration circuit for VCO, which can avoid phase uncertainty and shorten the time for automatic frequency calibration.
The second objective of the present invention is to provide an automatic calibration method for VCO, which can avoid the phase uncertainty and shorten the time for automatic frequency calibration.
One of the purposes of the invention is realized by adopting the following technical scheme:
a VCO automatic calibration circuit comprises a reference clock counter, a feedback clock counter, a state machine, a voltage-controlled oscillator, a frequency divider and a reset module, wherein the reference clock counter, the feedback clock counter, the reset module and the voltage-controlled oscillator are all connected with the state machine, and the reset module, the voltage-controlled oscillator and the feedback clock counter are all connected with the frequency divider;
the state machine resets the reference clock counter and the feedback clock counter in a reset state, enables the reset module to reset the frequency divider, enables the reference clock counter and the feedback clock counter to count simultaneously in a later counting state, records a feedback count value obtained by the feedback counter when the reference clock counter counts to a preset count value, resets the frequency divider, and finds an optimal capacitor array value of the voltage-controlled oscillator by a bisection method according to a comparison result of the preset count value and the feedback count value so as to adjust the capacitor array of the voltage-controlled oscillator.
The second purpose of the invention is realized by adopting the following technical scheme:
an automatic calibration method of a VCO comprises the following steps:
resetting: the state machine resets the reference clock counter and the feedback clock counter, enables the reset module to reset the frequency divider and outputs an intermediate capacitance value to the voltage-controlled oscillator;
a counting step: the frequency divider divides the output frequency of the voltage-controlled oscillator; the reference clock counter counts an input reference clock from the outside to a preset count value and sends the count value to the state machine; the feedback clock counter which counts simultaneously sends the feedback count value when the reference clock counter finishes counting to the state machine; the feedback count value is obtained by counting the output value from the frequency divider;
resetting the frequency divider: resetting the frequency divider;
a comparison step: the state machine compares the preset count value with the feedback count value, when the feedback count value is smaller than the preset count value, the capacitance value output to the voltage-controlled oscillator is reduced through a dichotomy, and when the feedback count value is larger than the preset count value, the capacitance value output to the voltage-controlled oscillator is increased through the dichotomy;
a judging step: and the state machine judges whether the dichotomy is finished, if so, the calibration is finished, otherwise, the reference clock counter and the feedback clock counter are reset, and then the counting step is returned.
Compared with the prior art, the invention has the beneficial effects that:
the frequency divider is reset when the counting is started, so that the initial phase of the feedback clock is always slightly later than the reference clock, and the problem that the initial phase of the feedback clock is uncertain so as to reduce the counting accuracy is solved; by resetting the frequency divider, the time for automatic calibration can be shortened.
Drawings
FIG. 1 is a graph of the effect of an initial phase on a count value of the prior art;
FIG. 2 is a graph of VCO output frequency versus control voltage versus capacitor array;
FIG. 3 is a block diagram of an automatic calibration circuit for a VCO in accordance with the present invention;
FIG. 4 is a flow chart of an automatic calibration method for VCO in accordance with the present invention;
FIG. 5 is a schematic diagram of a bisection method.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific embodiments, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
As shown in fig. 3, the present invention provides an automatic VCO calibration circuit, which includes a reference clock counter 11, a feedback clock counter 12, a state machine 13, a voltage-controlled oscillator 14, a frequency divider 15, and a reset module 16, where the reference clock counter 11, the feedback clock counter 12, the reset module 16, and the voltage-controlled oscillator 14 are all connected to the state machine 13, and the reset module 16, the voltage-controlled oscillator 14, and the feedback clock counter 12 are all connected to the frequency divider 15.
The reference clock counter 11 counts the input reference clock Fref under control of the state machine 13. I.e. when the state machine 13 is in the counting state. Feedback clock counter 12 counts the output of frequency divider 15 under control of state machine 13. I.e. when the state machine 13 is in the counting state. The frequency divider 15 is controlled by a reset module 16 to divide the output frequency of the vco 14. When the reset module 16 outputs 1, the output of the frequency divider 15 is kept at 0, and the operation is not performed; when the output of the reset module 16 is 0, the frequency divider works. Reset module 16 passes the reset instruction of state machine 13 to frequency divider 15.
Assuming that the number of bits of the capacitor array is n, the unit capacitance is Cu, the total capacitance is (2^ n-1) × Cu. The state machine 13 operates under the drive of the reference clock, and the state machine 13 finds the best capacitor array by the dichotomy in the present invention, as shown in fig. 5.
With reference to fig. 4, the present invention further provides an automatic calibration method for VCO, comprising the following steps:
s1: the state machine resets the reference clock counter and the feedback clock counter, enables the reset module to reset the frequency divider, and outputs the intermediate capacitance value of the capacitor array to the voltage-controlled oscillator;
in this step, the reference clock counter 11 and the feedback clock counter 12 are both reset to 0, the state machine output reset div is reset to 1, and therefore the frequency divider 15 is also reset through the reset module 16, and the state machine 13 output cap sel < n-1:0> takes an intermediate value, that is, cap _ sel < n-1:0> is 2^ (n-1), which is the actual value of the capacitor array of the vco 14. The state machine 13 output afc done is reset to 0, at which time the state machine 13 outputs reset cnt to reset the reference clock counter 11 and the feedback clock counter 12 to 0. It should be noted that this step is an initialization step, which is generally generated by a 3 power supply detection circuit in cooperation with a clock in the conventional technology to initialize the generation and release of the reset signal, and serves almost all circuit blocks on a chip. The initialization reset operation of the register of the normal circuit module is controlled by this signal, but usually will not be generated by this module, and the initialization reset signal is not controlled by this module as seen by the normal circuit module, which is a conventional technical means in this field, so that in practice, S1 completes the functions of initialization reset and reset release, and in practice, after the register obtains the default value through the initial reset, the circuit is released and enters the working state immediately.
S2: the frequency divider divides the output frequency of the voltage-controlled oscillator; the reference clock counter counts an input reference clock from the outside to a preset count value, namely the reference clock counter finishes counting when counting to the preset count value, and sends the preset count value to the state machine; the feedback clock counter counts simultaneously, counts the output value from the frequency divider to obtain a feedback count value when the reference clock counter finishes counting, and sends the feedback count value to the state machine;
the above S2 can be summarized as a counting state in which the counter 11 counts the reference clock Fref by the fixed number of cycles cnt _ ref. The reset module 16 releases the reset of the frequency divider and the resets of the two counters 11 and 12 are also released under the control of the state machine 13. The counter 11 can be reset and can count.
When the counter 11 counts the specified value cnt _ ref, the divider reset state S3 is entered.
S3: resetting the frequency divider; the divider output is reset to 0 and there is no more frequency output. Because the divider is reset at the start of the count, the initial phase of the feedback clock is always slightly later than the reference clock, thus eliminating the problem of uncertainty in the initial phase of the feedback clock reducing the accuracy of the count.
S4: the state machine compares the preset count value with the feedback count value, when the feedback count value is smaller than the preset count value, the capacitance value output to the voltage-controlled oscillator is reduced through a dichotomy, and when the feedback count value is larger than the preset count value, the capacitance value output to the voltage-controlled oscillator is increased through the dichotomy;
s5: and the state machine judges whether the dichotomy is finished, if so, the calibration is finished, otherwise, the reference clock counter and the feedback clock counter are reset, and then the step S3 is returned.
The reset in S1 is an initialization reset of the whole circuit, and resets all registers in preparation for normal operation of the circuit. S4 is to compare the counter of the feedback clock counter with a preset count value to determine whether the output capacitance value should be increased or decreased, and then determine whether the bisection has been completed, if so, enter the end state, otherwise, reset the reference clock counter and the feedback clock counter, without involving resetting of other registers.
The values of the two counters are read and compared by the state machine 13, and if cnt _ div is smaller than cnt _ ref, indicating that the output frequency of the divider 15 is smaller, the value of the capacitance output cap _ sel is decreased; conversely, if cnt _ div is greater than cnt _ ref, the value of the capacitance value output cap _ sel is increased. Because the divider has been reset, feedback clock counter 12 keeps the count state value unchanged, which eliminates the indeterminate state that may exist in conventional methods. In the conventional approach, because the reference clock and the feedback clock are non-homologous clocks, their relative frequencies and phases are uncertain. Thus, reading data generated by another clock threshold under control of one clock does not guarantee setup and hold times, and it is possible to read data while the data is changing and not yet stable. The data read at this time is not a definite high or low but an intermediate state, and the existence of such a metastable state may cause a program failure. Although the use of the method of inserting register synchronization can reduce the probability of failure caused by metastability, it cannot be completely eliminated. The approach presented here solves this problem well.
The end state is entered if the bisection is complete, and the capacitor array cap _ sel < n-1:0> is set to the optimum value. The state machine output afc _ done is set to 1 and calibration is complete.
Otherwise, the counter reset state is entered and the counter of the two counters 11 and 12 is reset to 0. And then entering a counting state to start a new round of counting. Until the bisection is complete.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.
Claims (2)
1. The VCO automatic calibration circuit is characterized by comprising a reference clock counter, a feedback clock counter, a state machine, a voltage-controlled oscillator, a frequency divider and a reset module, wherein the reference clock counter is used for counting an externally input reference clock, the feedback clock counter is used for counting an output numerical value of the frequency divider, the reference clock counter, the feedback clock counter, the reset module and the voltage-controlled oscillator are all connected with the state machine, and the reset module, the voltage-controlled oscillator and the feedback clock counter are all connected with the frequency divider; the state machine resets the reference clock counter and the feedback clock counter in a reset state, enables the reset module to reset the frequency divider, enables the reference clock counter and the feedback clock counter to count simultaneously in a later counting state, records a feedback count value obtained by the feedback counter when the reference clock counter counts to a preset count value, resets the frequency divider, and finds an optimal capacitor array value of the voltage-controlled oscillator through a bisection method according to a comparison result of the preset count value and the feedback count value so as to adjust the capacitor array of the voltage-controlled oscillator.
2. An automatic calibration method for a VCO (voltage controlled oscillator), comprising the steps of:
resetting: the state machine resets the reference clock counter and the feedback clock counter, enables the reset module to reset the frequency divider and outputs an intermediate capacitance value to the voltage-controlled oscillator;
a counting step: the frequency divider divides the output frequency of the voltage-controlled oscillator; the reference clock counter counts an input reference clock from the outside to a preset count value and sends the count value to the state machine; the feedback clock counter which counts simultaneously sends the feedback count value when the reference clock counter finishes counting to the state machine; the feedback count value is obtained by counting the output value from the frequency divider;
resetting the frequency divider: resetting the frequency divider;
a comparison step: the state machine compares the preset count value with the feedback count value, when the feedback count value is smaller than the preset count value, the capacitance value output to the voltage-controlled oscillator is reduced through a dichotomy, and when the feedback count value is larger than the preset count value, the capacitance value output to the voltage-controlled oscillator is increased through the dichotomy;
a judging step: and the state machine judges whether the dichotomy is finished, if so, the calibration is finished, otherwise, the reference clock counter and the feedback clock counter are reset, and then the counting step is returned.
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| TWI692716B (en) * | 2019-01-04 | 2020-05-01 | 瑞鼎科技股份有限公司 | Capacitive touch sensing circuit |
| CN110504959A (en) * | 2019-08-12 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | The calibration method and calibration circuit of a kind of internal clock |
| CN110365335A (en) * | 2019-08-12 | 2019-10-22 | 兆讯恒达微电子技术(北京)有限公司 | A kind of piece internal clock calibration method in technical process and calibration circuit |
| CN110954878B (en) * | 2019-11-21 | 2023-03-10 | 西安电子工程研究所 | Method for open loop detection of metastable state and correction |
| CN111404545B (en) * | 2020-04-20 | 2022-07-29 | 成都华微电子科技股份有限公司 | Oscillator circuit with digital trimming function and clock signal generation method |
| CN116298773A (en) * | 2022-12-27 | 2023-06-23 | 格睿通智能科技（深圳）有限公司 | Chip built-in self-test circuit, method and semiconductor device |
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| US6961403B1 (en) * | 2004-05-28 | 2005-11-01 | International Business Machines Corporation | Programmable frequency divider with symmetrical output |
| US7898344B2 (en) * | 2006-09-12 | 2011-03-01 | Fujitsu Limited | Phase-locked oscillator and multi-radar system using same |
| US8461933B2 (en) * | 2010-10-26 | 2013-06-11 | Mediatek Inc. | Device and method for frequency calibration and phase-locked loop using the same |
| CN104135285B (en) * | 2014-08-07 | 2017-02-15 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN106656173B (en) * | 2016-12-26 | 2020-01-24 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit of oscillator and frequency calibration method thereof |
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