CN104135285B - Frequency calibration circuit and method thereof - Google Patents
Frequency calibration circuit and method thereof Download PDFInfo
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- CN104135285B CN104135285B CN201410384467.0A CN201410384467A CN104135285B CN 104135285 B CN104135285 B CN 104135285B CN 201410384467 A CN201410384467 A CN 201410384467A CN 104135285 B CN104135285 B CN 104135285B
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Abstract
The invention provides a frequency calibration circuit and a method thereof. The frequency calibration circuit comprises a phase lock loop circuit, an M-dividing divider for generating a plurality of phase signals, a sampling circuit for sampling on the rising edges of the phase signals, a first counter for counting reference frequency signals, a second counter counting first phase signals, a logical control circuit for comparing a count value with a target count value to obtain a minimum difference value, and looking up a control bit of a voltage-controlled oscillator through the difference value, and a comparison circuit for judging whether the control voltage of the voltage-controlled oscillator is in a set range or not. The method comprises the following steps: sampling the reference frequency signals to obtain a total count value; comparing the total count value with a target count value; selecting a next resonance line according to a binary lookup flow till binary lookup ends; and outputting a resonance line corresponding to a minimum error in order that the output frequency of the voltage-controlled oscillator reaches a required value. Through adoption of the frequency calibration circuit and the method thereof, the speed and accuracy are increased, and the requirement on the working frequency of a digital circuit is lowered, so that a design method is simplified.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of frequency calibration circuit and its method.
Background technology
In wireless communication field, phase-locked loop frequency integrator (Phase Lock Loop, PLL) is in radio transmitting and receiving chip
A requisite part.Phase-locked loop circuit produces stable, the signal of the certain frequency of low phase noise.In modern channel radio
In letter chip, due to being on the increase it is considered to cost and the market factor of wireless communication protocol, support multiband, multimodal nothing
Line transceiving chip becomes main flow.Therefore, phase-locked loop module needs to support the output of multiband.Because multiple phaselocked loops will certainly carry
Carry out the excessive problem of power consumption, area, broadband single phase-locked loop circuit becomes the main flow in market.
In phase-locked loop circuit, voltage controlled oscillator (Voltage Control Oscillator, VCO) is the core producing frequency
Core module, wideband voltage controlled oscillator is always the study hotspot of RF application.Originally wideband voltage controlled oscillator is by capacitance variations
The larger varactor of scope is realized, but in limited voltage-controlled scope, wideband voltage controlled oscillator means that larger frequency modulation increases
Beneficial (KVCO), the deterioration of loop phase noise can be led to.There is strict wanting in view of radio communication to the phase noise of phaselocked loop
Ask, the wideband voltage controlled oscillator of this single resonance line is replaced by multiple-tuned line voltage controlled oscillator quickly.
Multiple-tuned line voltage controlled oscillator realizes frequency coarse adjustment using capacitor array, varactor realizes frequency fine tuning.Fine tuning
Journey is realized by cycle of phase-locked loop, and extra coarse tuning process is by automatic frequency calibration circuit (Auto Frequency
Calibration, AFC) realize.Therefore with respect to conventional phase locked loops, modern phase-locked loop circuit needs extra frequency calibration
Journey.When needing using fast lock phase-locked loop, the time that extra frequency calibration process is consumed is considerable.
Therefore, broadband phase-looked loop technology needs high-speed, high precision frequency calibration technology to reduce extra locking time, with
Realize the purpose of quick lock in.Earliest closed loop calibration counts needs substantial amounts of closed loop locking time to be eliminated already due to it,
Repeat no more.Frequency calibration technology in recent years is based primarily upon the reference frequency signal cycle, with time-voltage transfer circuit
(Time Voltage Converter, TVC) or it is counted as sampling meanses, the former precision is higher, but be only suitable for integral frequency divisioil,
The logic circuit improving needs more high speed of the latter's velocity accuracy, optimization design is complicated.
The patent of Publication No. CN103312323A, employing to reference frequency signal and oscillator output by loop point
The signal that frequency device frequency dividing obtains is counted, and two input signals of phase frequency detector in loop is counted, due to this
Two signal frequency difference is less and reference frequency signal is relatively low, therefore needs longer time could differentiate.
The patent of Publication No. CN103346790A, directly counts using to reference frequency signal and oscillator output, by
Larger in oscillator frequency, the method relatively goes up a kind of method speed and precision all has a distinct increment, but locks into digital circuit
Operating frequency and design difficulty, high-frequency circuit cannot be applied, and needs first oscillator output to be divided, thus reducing precision
And speed.
Therefore, how quickly the frequency calibration that, must carry out phaselocked loop in high precision is that those skilled in the art urgently solves
Problem certainly.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of frequency calibration circuit and its side
Method, for solving prior art medium frequency collimation technique speed slowly, the low problem of precision.
For achieving the above object and other related purposes, the present invention provides a kind of frequency calibration circuit, described frequency calibration
Circuit at least includes：
Phase frequency detector, wave filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider, ÷ M divider, sampling electricity
Road, the first counter, the second counter, comparison circuit, logic control circuit；
Described phase frequency detector is connected to the reference frequency signal of input and the feedback frequency letter of described ÷ N divider output
Number, for obtaining the phase difference between described reference frequency signal and described feedback frequency signal；
Described wave filter is connected to described phase frequency detector, for filtering to the output signal of described phase frequency detector
Ripple；
Described voltage-setting circuitry is connected to described wave filter, for setting the control voltage of described voltage controlled oscillator；
Described voltage controlled oscillator is connected to described voltage-setting circuitry, and the control ratio being exported by described logic control circuit
The control of special signal, for adjusting frequency of oscillation；
Described ÷ N divider is connected to described voltage controlled oscillator, for carrying out to the output signal of described voltage controlled oscillator
Frequency dividing, and feed back to described phase frequency detector；
Described ÷ M divider is connected to described voltage controlled oscillator, for carrying out to the output signal of described voltage controlled oscillator
Frequency dividing, produces multiple phase signals simultaneously；
Described sample circuit is connected to described ÷ M divider, for exporting to described ÷ M divider except first phase place
Other phase signals outside signal are sampled；
Described first counter is connected to described reference frequency signal, for counting to described reference frequency signal；
Described second counter is connected to first phase signal of described ÷ M divider output, and it is counted；
Described comparison circuit is connected to the input of described voltage controlled oscillator, for judging the control of described voltage controlled oscillator
Whether voltage is in setting range, and exports result of determination；
Described logic control circuit is connected to described sample circuit, described first counter, described second counter and institute
State comparison circuit；According to described sample circuit, described first counter, described second counter output result, draw total
Numerical value, and compare with objective count value and draw difference, and difference is compared with minimal difference, take less difference as next
Take turns the minimal difference comparing, binary lookup rule searching resonance line is utilized according to described difference, and exports its corresponding pressure
The control bit of controlled oscillator；Output result according to described comparison circuit controls described voltage-setting circuitry simultaneously.
Preferably, also include charge pump, described charge pump is connected between described phase frequency detector and described wave filter, use
In raising gain.
Preferably, described voltage-setting circuitry includes first switch and second switch, and one end of described first switch connects
The output end of described wave filter, the other end connects the input of described voltage controlled oscillator；Described second switch one end connects described
The input of voltage controlled oscillator, the other end connects the first setting voltage.
Preferably, described ÷ M divider produces 4 phase signals.
It is highly preferred that described sample circuit includes 3 high speed flip flops, the signal input part of described high speed flip flop connects
Described reference frequency signal, Clock control end connects each phase signal respectively, and output end connects to described logic control circuit.
Preferably, described comparison circuit includes first comparator, the second comparator and OR gate, and described first comparator is just
It is connected with the reverse input end of described second comparator to input, and be connected to the output end of described voltage-setting circuitry, institute
The reverse input end stating first comparator connects the first reference voltage, and the positive input of described second comparator connects the second ginseng
Examine voltage, described OR gate is connected to described first comparator and the output end of described second comparator, described OR gate defeated
Go out end to connect to described logic control circuit.
Preferably, described logic control circuit includes logic comparison module, is connected to the minimum of described logic comparison module
Application condition module and binary lookup module, and it is connected to described minimal error comparison module and described binary lookup mould
The selecting module of block.
For achieving the above object and other related purposes, the present invention provides a kind of transmitting frequency calibration method, described frequency calibration
Method at least comprises the following steps：
Step one：Cycle of phase-locked loop is disconnected based on described voltage-setting circuitry, and the control of described voltage controlled oscillator is set
Voltage is the first setting voltage Vset；
Step 2：Divided based on described ÷ M divider and produce the first quantity P phase signal；Based on described sample circuit
Described reference frequency signal is sampled；Based on described first counter, second is counted up to described reference frequency signal fref
Quantity k；Based on described second counter, first phase signal is counted within the counting cycle of described first counter, note
For NC；The record count cycle start and at the end of sampled value, and obtain corresponding quadrature, be designated as Rb and Rd respectively；Meter
Calculate total count value Ntotal=NC×P+Rd-Rb；
Step 3：Total count value Ntotal and objective count value PkN/M are compared and draw difference, and by difference with
Little difference is compared, and the initial value of described minimal difference is objective count value PkN/M, takes less difference to compare as next round
, for ÷ N divider except rate, M is ÷ M divider except rate for minimal difference, wherein N；Ongoing frequency is drawn according to described difference
Speed, finds out next resonance line using binary lookup rule, and exports the control bit of its corresponding voltage controlled oscillator；
Return to step two, continues to search for resonance line, until binary lookup finishes；
Step 4：The control bit of the voltage controlled oscillator corresponding to optimal tuning line of output minimal difference record, is based on
Described voltage-setting circuitry closes cycle of phase-locked loop, recovers closed loop states, after the first setting time, cycle of phase-locked loop is steady
Fixed, detect the control voltage of described voltage controlled oscillator based on described comparison circuit, if the control voltage of described voltage controlled oscillator surpasses
Go out setting range, then return to step one, recalibrate；If the control voltage of described voltage controlled oscillator is in setting range, complete
Become calibration.
Preferably, in step one, described first setting voltage Vset is the half of supply voltage amplitude.
Preferably, in step 2, described sample circuit enters to described reference frequency signal in the rising edge of each phase signal
Row sampling.
Preferably, in step 3, described binary lookup rule is dichotomy.
Preferably, in step 4, described first setting time is completed by the counting of described second counter.
As described above, the frequency calibration circuit of the present invention and its method, have the advantages that：
The invention provides a kind of frequency that can apply to wideband multi-mode wireless communication transceiver middle width strip phaselocked loop
Collimation technique.The exemplary application of the present invention can realize the frequency calibration of quick high accuracy in the multiple-tuned line phaselocked loop of broadband.
With respect to existing frequency calibration technology, the present invention can reduce digital circuit while realizing improving speed and precision
The requirement of operating frequency, thus simplify method for designing.The present invention adopts open loop sampling, is improved based on the method counting, and increases
Add the sampling mechanism of four phase places, thus in the case of not lifting count frequency, substantially increasing sampling precision, thus being lifted
Frequency resolution, reduces the gate time required for unitary sampling.Meanwhile, the control voltage to voltage controlled oscillator for the present invention
Sampled, automatically recalibrated in the case of losing lock, it is to avoid the losing lock in the course of work.Oscillator in the present invention
The selection algorithm of optimal tuning line employs binary lookup rule, has been simultaneously introduced minimal error comparison mechanism, it is to avoid two
The error of system search rule final step is it is ensured that the centre frequency of selected resonance line is closest to the frequency needing.
Brief description
Fig. 1 is shown as the frequency calibration circuit schematic diagram of the present invention.
Fig. 2 is shown as producing the ÷ 2 divider schematic diagram of four phase signals in the present invention.
Fig. 3 is shown as the logic control circuit schematic diagram of the present invention.
Fig. 4 is shown as the transmitting frequency calibration method schematic flow sheet of the present invention.
Fig. 5 is shown as the detection sampling time sequence figure of the present invention.
Fig. 6 is shown as voltage and the frequency change schematic diagram of the transmitting frequency calibration method of the present invention.
Fig. 7 is shown as the frequency calibration procedure schematic diagram of the transmitting frequency calibration method binary lookup of the present invention.
Component label instructions
1 frequency calibration circuit
11 phase frequency detectors
12 charge pumps
13 wave filters
14 voltage-setting circuitries
141 first switches
142 second switches
15 voltage controlled oscillators
16 ÷ N dividers
17 ÷ M divider
171 first D-latch
172 second D-latch
18 sample circuits
181 first high speed flip flops
182 second high speed flip flops
183 the 3rd high speed flip flops
19 first counters
20 second counters
21 comparison circuits
211 first comparators
212 second comparators
213 OR gates
22 logic control circuits
221 logic comparison modules
222 minimal error comparison modules
223 binary lookup modules
224 selecting modules
S1～S4 step one～step 4
Fref reference frequency signal
Vset first setting voltage
The control voltage of Vtune voltage controlled oscillator
Phase1 first phase signal
Phase2 second phase signal
Phase3 third phase signal
Phase4 the 4th phase signal
Vref1 first reference signal
Vref2 second reference signal
Clk first clock signal
～Clk second clock signal
P first quantity
K second quantity
NC3rd quantity
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
Refer to Fig. 1～Fig. 7.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shows the assembly relevant with the present invention rather than then according to package count during actual enforcement in schema
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
As shown in figure 1, the present invention provides a kind of frequency calibration circuit 1, described frequency calibration circuit 1 at least includes：
Phase frequency detector 11, wave filter 13, voltage-setting circuitry 14, voltage controlled oscillator 15, ÷ N divider 16, ÷ M division
Device 17, sample circuit 18, the first counter 19, the second counter 20, comparison circuit 21, logic control circuit 22；
As shown in figure 1, described phase frequency detector 11 is connected to the reference frequency signal fref of input and described ÷ N divider
The feedback frequency signal of output, for obtaining the phase place between described reference frequency signal fref and described feedback frequency signal
Difference.
As shown in figure 1, described frequency calibration circuit 1 also includes charge pump 12, described charge pump 12 is connected to described frequency discrimination
Between phase discriminator 11 and described wave filter 13, for improving gain.
As shown in figure 1, described wave filter 13 is connected to described phase frequency detector 11, for described phase frequency detector 11 and
The output signal of described charge pump 12 is filtered.
As shown in figure 1, described voltage-setting circuitry 14 is connected to described wave filter 13, for setting described voltage controlled oscillator
Control voltage Vtune.
As shown in figure 1, described voltage-setting circuitry 14 includes first switch 141 and second switch 142, described first switch
141 one end connects the output end of described wave filter 13, and the other end connects the input of described voltage controlled oscillator 15；Described second
Switch the input that 142 one end connect described voltage controlled oscillator 15, the other end connects the first setting voltage Vset.Opened by difference
The switching closed can set to control voltage Vtune of described voltage controlled oscillator.
As shown in figure 1, described voltage controlled oscillator 15 is connected to described voltage-setting circuitry 14, and by described logic control electricity
The control bit signal of road 22 output controls, and for adjusting frequency of oscillation, and then so that described feedback frequency signal is infinitely close to
Described reference frequency signal fref.
As shown in figure 1, described ÷ N divider 16 is connected to described voltage controlled oscillator 15, for described voltage controlled oscillator
15 output signal is divided, and feeds back to described phase frequency detector 11 and adjusted further.
As shown in figure 1, described ÷ M divider 17 is connected to described voltage controlled oscillator 15, for described voltage controlled oscillator
15 output signal is divided, and the output frequency reducing described voltage controlled oscillator 15 will with the work clock meeting logic circuit
Ask, produce multiple phase signals simultaneously.
Described ÷ M divider 17 can produce the first quantity P phase signal, but described ÷ M divider 17 except rate M with
There is not positive connection in the first quantity P, the first quantity P phase signal can be produced by ÷ (P/2) divider, described ÷ M division
Device 17 includes ÷ (P/2) divider and other remove the divider of rate to constitute the divider as M except rate.For example, when except the setting of rate M
For 16, when the first quantity P is set as 2, described ÷ M divider 17 can be made up of ÷ 8 divider and ÷ 2 divider.
In the present embodiment, described first quantity P is set as 4, and described ÷ M divider 17 includes ÷ 2 divider, produces
Raw 4 phase signals.As shown in Fig. 2 described ÷ 2 divider is made up of two D-latch, the forward direction of the first D-latch 171 is defeated
Go out the input terminating described second D-latch 172, and export first phase signal Phase1；Described first D-latch 171
Inverse output terminal output third phase signal Phase3；The positive output end output second phase of described second D-latch 172
Signal Phase2；The positive output of described second D-latch 172 terminates the input of described first D-latch 171, and exports
4th phase signal Phase4；The positive control end of described first D-latch 171 and described second D-latch 172 accesses first
Clock signal Clk, Reverse Turning Control terminates into second clock signal～Clk, when described second clock signal～Clk is described first
The inverted signal of clock signal Clk.
As shown in figure 1, described sample circuit 18 is connected to described ÷ M divider 17, for defeated to described ÷ M divider 17
Other phase signals in addition to first phase signal Phase1 going out are sampled.
As shown in figure 1, in the present embodiment, described sample circuit 18 includes 3 high speed flip flops, described high speed flip flop
Signal input part connect described reference frequency signal fref, the Clock control end of the first high speed flip flop 181 connects described the
Two phase signal Phase2；The Clock control end of the second high speed flip flop 182 connects described third phase signal Phase3；3rd
The Clock control end of high speed flip flop 183 connects described 4th phase signal Phase4.The output end of each high speed flip flop connects
To described logic control circuit 22.
The frequency calibration circuit of the present invention also may extend to 8 phase places even 16 phase places, thus realizing becoming of speed and precision
Improve again.8 phase places can be produced by ÷ 4 divider, and the quantity of high speed flip flop increases to 7；16 phase places can be produced by ÷ 8 divider
Raw, the quantity of high speed flip flop increases to 15.
As shown in figure 1, described first counter 19 is connected to described reference frequency signal fref, for described reference frequency
Rate signal fref is counted.
As shown in figure 1, described second counter 20 is connected to the first phase signal of described ÷ M divider 17 output
Phase1, and it is counted.
As shown in figure 1, described comparison circuit 21 is connected to the input of described voltage controlled oscillator 15, for judging described pressure
Whether control voltage Vtune of controlled oscillator is in setting range, and exports result of determination.
As shown in figure 1, described comparison circuit 21 includes first comparator 211, the second comparator 212 and OR gate 213, described
The positive input of first comparator 211 is connected with the reverse input end of described second comparator 212, and is connected to described voltage
The output end of setting circuit 14, the reverse input end of described first comparator 211 connects the first reference voltage, and described second compares
The positive input of device 212 connects the second reference voltage, and described OR gate 213 is connected to described first comparator 211 and institute
State the output end of the second comparator 212, the output end of described OR gate 213 connects to described logic control circuit 22.Described first
Reference voltage is more than described second reference voltage, if control voltage Vtune of described voltage controlled oscillator (is more than beyond setting range
Described first reference voltage or be less than described second reference voltage), described comparison circuit 21 send signal control described frequency school
Quasi- circuit 1 re-starts calibration；If in setting range, calibration process completes control voltage Vtune of described voltage controlled oscillator.
As shown in figure 1, described logic control circuit 22 is connected to described sample circuit 18, described first counter 19, institute
State the second counter 20 and described comparison circuit 21, according to described sample circuit 18, described first counter 19, described second meter
The output result of number devices 20 and described comparison circuit 21 exports the control signal of described voltage-setting circuitry 14 and described voltage-controlled shakes
Swing the control bit signal of device 15, coarse adjustment is carried out to described voltage controlled oscillator 15.
As shown in figure 3, in the present embodiment, described logic control circuit 22 at least includes logic comparison module 221, minimum
Application condition module 222, binary lookup module 223 and selecting module 224.Described logic comparison module 221 draws comparing
Difference export to described minimal error comparison module 222 and described binary lookup module 223；Described minimal error compares mould
The difference that described logic comparison module 221 exports is compared continuous renewal minimal difference with current minimal difference by block 222；Institute
State the control that binary lookup module 223 searches described voltage controlled oscillator 15 according to the difference that described logic comparison module 221 exports
Bit signal processed.In binary system comparison procedure, described selecting module 224 exports record in described binary lookup module 223
Described voltage controlled oscillator 15 control bit signal.When all binary systems relatively complete, described selecting module 224 exports institute
State the control bit signal of the described voltage controlled oscillator 15 of record in minimal error comparison module 222.
As shown in figure 4, the present invention provides a kind of transmitting frequency calibration method, described transmitting frequency calibration method at least includes following step
Suddenly：
Step one S1：Cycle of phase-locked loop is disconnected based on described voltage-setting circuitry 14, and the control by described voltage controlled oscillator
Voltage Vtune processed is the first setting voltage Vset.
As shown in figure 1, controlling in described voltage-setting circuitry 14 described first to open using described logic control circuit 22
Close 141 disconnections, described second switch 142 closes, control voltage Vtune of described voltage controlled oscillator connects to the described first setting
Voltage Vset, in the present embodiment, described first setting voltage Vset is the half of supply voltage amplitude, voltage-controlled shakes even if described
Control voltage Vtune swinging device is set as VDD/2.
Step 2 S2：Divided based on described ÷ M divider 17 and produce the first quantity P phase signal；Based on described sampling
Circuit 18 is sampled to described reference frequency signal fref；Based on described first counter 19 to described reference frequency signal
Fref counts up to the second quantity k；It is based on described second counter 20 to first within the counting cycle of described first counter 19
Phase signal Phase1 is counted, and is designated as the 3rd quantity NC；The record count cycle start and at the end of sampled value, and
To corresponding quadrature, it is designated as Rb and Rd respectively；Calculate total count value Ntotal=NC×P+Rd-Rb.
For the different requirements of speed and precision, the first quantity P can be done with different settings, the first quantity P is bigger, speed
Faster, precision is higher.As shown in figure 1, in the present embodiment, described first quantity P is set as 4, that is, produce 4 phase signals.
As shown in figure 1, described first phase signal Phase1 connects to described second counter 20, counted by described second
Device 20 counts to it；Described second phase signal Phase2, described third phase signal Phase3 and described 4th phase place
Signal Phase4 connects to described sample circuit 18, be respectively connecting to 3 high speed flip flops in described sample circuit 18 when
Clock control end, the input of 3 high speed flip flops in described sample circuit 18 terminates described reference frequency signal fref, exists respectively
Described second phase signal Phase2, the rising edge of described third phase signal Phase3 and described 4th phase signal Phase4
Described reference frequency signal fref is sampled.
As shown in figure 5, in the present embodiment, single gate time is kTref, and the wherein second quantity k is the described of setting
The count value of the first counter 19, Tref is the cycle of reference frequency signal fref.
As shown in figure 5, in single gate time kTref, described second counter 20 is to described first phase signal
Phase1 starts counting up to N from 1C.
As shown in figure 5, described second phase signal Phase2, described third phase signal Phase3 and described 4th phase place
Signal Phase4 samples to reference frequency signal fref, in single gate time kTref, at the beginning and end of record
Sampled value, and the described first phase signal Phase1 that reference frequency signal fref rising edge is located at the beginning and end of determining
Quadrant, is designated as Rb and Rd respectively, and calculates total count value Ntotal=NC×P+Rd-Rb.As shown in figure 5, in the present embodiment,
Sampled value during beginning is 011, and in quadrant 2. its corresponding rising edge, remembers Rb=2；At the end of sampled value be 000, its correspondence
Rising edge in quadrant 4., remember Rd=4.In single gate time kTref, total counting cycle includes the meter of middle 1 to Nc
The described third phase signal Phase3 of 4 times of count values in one number time and incipient stage and described 4th phase signal
The rising edge of Phase4 counts, i.e. Ntotal=NC× P+Rd-Rb=NC× 4+4-2=NC×4+2.Each sampled value, quadrature are equal
For concrete measuring value；Equally, described first quantity P requires to be set also dependent on side circuit, is not limited in this enforcement
Cited data in example.
In the present embodiment, do not increase high-speed counter, only increase by 3 triggers, just counting rate is improve 4
Times；Can also show that precision is Δ f=M/4k × fref, and the precision of conventional traditional counting structure be Δ f=M/k ×
Fref, the precision of the present invention improves 4 times.In the case that high speed flip flop allows and phase-lock-ring output frequency is higher,
The present invention can produce 8 phase signals using ÷ 4 divider, or even ÷ 8 divider produces 16 phase signals, you can realizes 8 times,
16 times of precision and speed.
Step 3 S3：Based on described logic control circuit 22, total count value Ntotal is carried out with objective count value PkN/M
Relatively draw difference, and difference be compared with minimal difference, the initial value of described minimal difference is objective count value PkN/M,
Take the minimal difference that less difference compares as next round, for ÷ N divider except rate, M is ÷ M divider except rate to wherein N；
Draw the speed of ongoing frequency according to described difference, find out next resonance line using binary lookup rule, and export it
The control bit of corresponding voltage controlled oscillator；Return to step two, continues to search for resonance line, until binary lookup finishes.
Described resonance line has the control bit of corresponding voltage controlled oscillator, can be to electric capacity battle array in described voltage controlled oscillator 15
Row are controlled to realize the coarse adjustment of the output frequency to described voltage controlled oscillator 15.By corresponding for described resonance line VCO
The control bit of device is pressed binary sized order and is arranged, if described total count value Ntotal is less than objective count value PkN/M, explanation
Ongoing frequency is excessively slow, then press binary lookup rule (i.e. dichotomy), seeking scope is contracted to the first half of control bit,
Otherwise seeking scope is contracted to the latter half of control bit, and the control bit finding is exported.Return to step two S2, enters
The lookup of next group resonance line of row, according to binary lookup rule, constantly reduces seeking scope, until finding last tuning
Line, now the resonance line of minimal difference record is optimal tuning line, by its corresponding control bit output.
Step 4 S4：The control bit of the voltage controlled oscillator corresponding to optimal tuning line of output minimal difference record, base
Close cycle of phase-locked loop in described voltage-setting circuitry 14, recover closed loop states, after the first setting time, cycle of phase-locked loop
Stable, detect control voltage Vtune of described voltage controlled oscillator based on described comparison circuit 21, if the control of described voltage controlled oscillator
Voltage Vtune processed exceeds setting range, then return to step one, recalibrates；If control voltage Vtune of described voltage controlled oscillator
In setting range, then complete to calibrate.
As shown in figure 1, controlling in described voltage-setting circuitry 14 described first to open using described logic control circuit 22
Close 141 closures, described second switch 142 disconnects, make described cycle of phase-locked loop closure, enter working condition, cycle of phase-locked loop enters
Line phase is adjusted.After the first setting time, cycle of phase-locked loop is stable, PGC demodulation, and described first setting time is by described
Second counter 20 counts to be realized, and can be set according to the corresponding time of physical circuit.When described second counter 20 counts
To described first setting time, described comparison circuit 21 detects to control voltage Vtune of described voltage controlled oscillator, if
Control voltage Vtune of described voltage controlled oscillator exceeds setting range, in the present embodiment, the control electricity of described voltage controlled oscillator
Pressure Vtune is more than described first reference voltage Vref 1 or is less than described second reference voltage Vref 2, then return to step one S1, weight
New calibration.If control voltage Vtune of described voltage controlled oscillator is in setting range, in the present embodiment, described VCO
Control voltage Vtune of device is more than described second reference voltage Vref 2 and is less than described first reference voltage Vref 1, then complete
Calibration.
Fig. 6 is the voltage of transmitting frequency calibration method and the frequency change of the present invention, and Fig. 7 is the frequency calibration of binary lookup
Journey.The present invention, using 65nm process modeling, carries out simulating, verifying using Candence AMS emulation tool, using Verilog
A model is modeled to phaselocked loop part, and the voltage-controlled inductance and capacitance type oscillator building 9.75GHz～11.5GHz is as described
Voltage controlled oscillator 15, the capacitor array controlling with 6 bits, reference frequency 25MHz.Described voltage controlled oscillator first to high frequency
Signal carries out 16 frequency dividings (M=16), produces 4 phase signals.Single gate time kTref is 12 times of reference frequency cycle (k=
12), sets target frequency is 10.6GHz.As shown in fig. 6, control voltage Vtune of described voltage controlled oscillator just starts to be set in
650mV (half of supply voltage), described frequency calibration circuit is according to binary lookup method to described voltage controlled oscillator 15
Resonance line makes a look up, as shown in fig. 7,6 bit-binary are searched needing to carry out 6 times, the control bit finding first is
100000, now the output frequency of voltage controlled oscillator 15 is 10.67GHz；The control bit finding for the second time is 010000, defeated
Going out frequency is 9.931GHz；The control bit that third time finds is 011000, and output frequency is 10.3GHz；4th lookup
The control bit arriving is 011100, and output frequency is 10.49GHz；The control bit that 5th time finds is 011110, output frequency
Rate is 10.58GHz；The control bit finding for the last time is 011111, and output frequency is 10.63GHz；Due to minimal error
The presence of comparison algorithm, loop non-selected last binary lookup obtain 011111, but it is less to have selected error
011110, said frequencies search procedure used time 3.4 μ s.Then phaselocked loop enters working condition, after phase lock loop locks, described pressure
Control voltage Vtune of controlled oscillator is stablized in 822.8mV；The output frequency of described voltage controlled oscillator 15 is stablized in 10.6GHz,
Consistent with target frequency.By the demonstration of the invention described above, can obtain frequency accuracy be Δ f=M/4k × fref=16/48 ×
25MHz≈8.3MHz.It follows that utilizing frequency calibration circuit and the method for the present invention, for above-mentioned high frequency phase-locked ring model,
Achieve high-precision high-speed frequency calibration.
The frequency calibration circuit of the present invention utilizes the control voltage of sampling circuit samples voltage controlled oscillator, to judge whether to lose
Lock；÷ N divider divides to voltage controlled oscillator output signal, and the frequency reducing voltage controlled oscillator is to meet logic circuit
Work clock requires, and produces four phase signals simultaneously；Counter counts to the signal after frequency dividing, and reference frequency is believed
Number counted；Logic control circuit is compared according to the value of counter, to determine frequency speed；The knot being compared according to logic
Fruit carries out binary system hunting；Minimal error comparator is compared to the result of binary lookup, selects frequency error minimum
Resonance line.
The present invention, first with sample circuit, with rear three signals in four phase signals as clock, believes to reference frequency
Number sampled；Meanwhile, reference frequency signal and first phase signal are counted, when reference frequency signal count value reaches
During to the second quantity k, read the value of another counter and the value of three phase samples, enter row operation according to these values, obtain
To final total count value, then compare with the corresponding count value of frequency needing, thus drawing the speed of ongoing frequency, then root
According to the flow process of binary lookup, select next resonance line, repeat process above, until binary lookup terminates.Meanwhile, exist
Every time at the end of binary lookup, all can compare and draw the corresponding frequency of minimal error, the corresponding tune of final output minimal error
Humorous line.
The invention provides a kind of frequency that can apply to wideband multi-mode wireless communication transceiver middle width strip phaselocked loop
Collimation technique.The exemplary application of the present invention can realize the frequency calibration of quick high accuracy in the multiple-tuned line phaselocked loop of broadband.
With respect to existing frequency calibration technology, the present invention can reduce digital circuit while realizing improving speed and precision
The requirement of operating frequency, thus simplify method for designing.The present invention adopts open loop sampling, is improved based on the method counting, and increases
Add the sampling mechanism of four phase places, thus in the case of not lifting count frequency, substantially increasing sampling precision, thus being lifted
Frequency resolution, reduces the gate time required for unitary sampling.Meanwhile, the control voltage to voltage controlled oscillator for the present invention
Sampled, automatically recalibrated in the case of losing lock, it is to avoid the losing lock in the course of work.Oscillator in the present invention
The selection algorithm of optimal tuning line employs binary lookup rule, has been simultaneously introduced minimal error comparison mechanism, it is to avoid two
The error of system search rule final step is it is ensured that the centre frequency of selected resonance line is closest to the frequency needing.
The present invention than the patent for CN103346790A for the China Patent Publication No. in the application of identical phaselocked loop, Ke Yiti
4 times in high precision, in the case of keeping precision identical, then speed can improve 4 times, breach original technology and lock into circuit work
The restriction of working frequency, realizes the breakthrough in speed and precision using simple 3 high speed flip flops.Meanwhile, with integrated circuit
Constantly the reducing of technique, trigger speed improves constantly, and the present invention also can very easily extend to 8 phase places even 16 phase places,
Thus realizing significantly improving of speed and progress, the number from only increasing trigger unlike 4 phase places, algorithm is changed
Dynamic less.Simultaneously in the present invention, except ÷ N divider, trigger needs outside optimization manually, and remaining module operating frequency is not high,
It is Verilog code to write, portability is higher.
In sum, the frequency calibration circuit of the present invention includes phase frequency detector, wave filter, voltage-setting circuitry, voltage-controlled
Oscillator, ÷ N divider, ÷ M divider, sample circuit, the first counter, the second counter, comparison circuit, logic control electricity
Road.Described phase frequency detector, wave filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider constitute cycle of phase-locked loop.Described
÷ M divider divides to the output signal of described voltage controlled oscillator, and produces multiple phase signals.Described sample circuit pair
Other phase signals in addition to first phase signal of described ÷ M divider output are sampled.Described first counter pair
The rising edge of described reference frequency signal is counted.The first phase that described second counter exports to described ÷ M divider
Signal rising edge is counted.Described logic control circuit is according to described sample circuit, described first counter, described second meter
The output result of number devices and described comparison circuit exports the control signal of described voltage-setting circuitry and described voltage controlled oscillator
Control bit signal, carries out coarse adjustment to described voltage controlled oscillator.Described comparison circuit is used for judging the control of described voltage controlled oscillator
Whether voltage processed is in setting range, and exports result of determination.The present invention first with sample circuit, with four phase signals
Three signals are clock afterwards, and reference frequency signal is sampled；Meanwhile, reference frequency signal and first phase signal are carried out
Count, when reference frequency signal count value reaches the second quantity k, read the value of another counter and three phase samples
Value, enter row operation according to these values, obtain final total count value, then with need the corresponding count value of frequency compare, from
And draw the speed of ongoing frequency, then according to the flow process of binary lookup, select next resonance line, repeat mistake above
Journey, until binary lookup terminates.Meanwhile, at the end of each binary lookup, all can compare and show that minimal error is corresponding
Frequency, the corresponding resonance line of final output minimal error.The invention provides one kind can apply to wideband multi-mode channel radio
The frequency calibration technology of letter transceiver middle width strip phaselocked loop.The exemplary application of the present invention is permissible in the multiple-tuned line phaselocked loop of broadband
Realize the frequency calibration of quick high accuracy.With respect to existing frequency calibration technology, the present invention can realize improving speed and
While precision, reduce the requirement of the operating frequency of digital circuit, thus simplifying method for designing.The present invention adopts open loop sampling,
Improved based on the method counting, increased the sampling mechanism of four phase places, thus in the case of not lifting count frequency, greatly
Improve sampling precision greatly, thus improving frequency resolution, reducing the gate time required for unitary sampling.Meanwhile, originally
Invention is sampled to the control voltage of voltage controlled oscillator, automatically recalibrate in the case of losing lock, it is to avoid worked
Losing lock in journey.The selection algorithm of the oscillator optimal tuning line in the present invention employs binary lookup rule, is simultaneously introduced
Minimal error comparison mechanism, it is to avoid the error of binary lookup rule final step is it is ensured that in selected resonance line
Frequency of heart is closest to the frequency needing.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial
Value.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (12)
1. a kind of frequency calibration circuit is it is characterised in that described frequency calibration circuit at least includes：
Phase frequency detector, wave filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider, ÷ M divider, sample circuit,
One counter, the second counter, comparison circuit, logic control circuit；
Described phase frequency detector is connected to the reference frequency signal of input and the feedback frequency signal of described ÷ N divider output,
For obtaining the phase difference between described reference frequency signal and described feedback frequency signal；
Described wave filter is connected to described phase frequency detector, for being filtered to the output signal of described phase frequency detector；
Described voltage-setting circuitry is connected to described wave filter, for setting the control voltage of described voltage controlled oscillator；
Described voltage controlled oscillator is connected to described voltage-setting circuitry, and the control bit being exported by described logic control circuit is believed
Number control, for adjusting frequency of oscillation；
Described ÷ N divider is connected to described voltage controlled oscillator, for dividing to the output signal of described voltage controlled oscillator,
And feed back to described phase frequency detector；
Described ÷ M divider is connected to described voltage controlled oscillator, for dividing to the output signal of described voltage controlled oscillator,
Produce multiple phase signals simultaneously；
Described sample circuit is connected to described ÷ M divider, for exporting to described ÷ M divider except first phase signal
Other outer phase signals are sampled；
Described first counter is connected to described reference frequency signal, for counting to described reference frequency signal；
Described second counter is connected to first phase signal of described ÷ M divider output, and it is counted；
Described comparison circuit is connected to the input of described voltage controlled oscillator, for judging the control voltage of described voltage controlled oscillator
Whether in setting range, and export result of determination；
Described logic control circuit is connected to described sample circuit, described first counter, described second counter and described ratio
Compared with circuit；According to described sample circuit, described first counter, described second counter output result, draw total count value,
And compare with objective count value and draw difference, and difference is compared with minimal difference, take less difference as next round ratio
Minimal difference relatively, utilizes binary lookup rule searching resonance line according to described difference, and exports it and corresponding voltage-controlled shake
Swing the control bit of device；Output result according to described comparison circuit controls described voltage-setting circuitry simultaneously.
2. frequency calibration circuit according to claim 1 it is characterised in that：Also include charge pump, described charge pump connects
Between described phase frequency detector and described wave filter, for improving gain.
3. frequency calibration circuit according to claim 1 it is characterised in that：Described voltage-setting circuitry includes first switch
And second switch, one end of described first switch connects the output end of described wave filter, the other end described voltage controlled oscillator of connection
Input；Described second switch one end connects the input of described voltage controlled oscillator, and the other end connects the first setting voltage.
4. frequency calibration circuit according to claim 1 it is characterised in that：Described ÷ M divider produces 4 phase place letters
Number.
5. frequency calibration circuit according to claim 4 it is characterised in that：Described sample circuit includes 3 to be triggered at a high speed
Device, the signal input part of described high speed flip flop connects described reference frequency signal, and Clock control end connects each phase place letter respectively
Number, output end connects to described logic control circuit.
6. frequency calibration circuit according to claim 1 it is characterised in that：Described comparison circuit include first comparator,
Second comparator and OR gate, the positive input of described first comparator is connected with the reverse input end of described second comparator,
And it is connected to the output end of described voltage-setting circuitry, the reverse input end of described first comparator connects the first reference voltage,
The positive input of described second comparator connects the second reference voltage, described OR gate be connected to described first comparator and
The output end of described second comparator, the output end of described OR gate connects to described logic control circuit.
7. frequency calibration circuit according to claim 1 it is characterised in that：Described logic control circuit includes logic and compares
Module, is connected to minimal error comparison module and the binary lookup module of described logic comparison module, and is connected to described
Minimal error comparison module and the selecting module of described binary lookup module.
8. the frequency calibration circuit as described in a kind of any one as claim 1～7 transmitting frequency calibration method it is characterised in that
Described transmitting frequency calibration method comprises the following steps：
Step one：Cycle of phase-locked loop is disconnected based on described voltage-setting circuitry, and the control voltage of described voltage controlled oscillator is set
For the first setting voltage Vset；
Step 2：Divided based on described ÷ M divider and produce the first quantity P phase signal；Based on described sample circuit to institute
State reference frequency signal to be sampled；Second quantity k is counted up to described reference frequency signal based on described first counter；?
Based on described second counter, first phase signal is counted in the counting cycle of described first counter, be designated as NC；Note
The record counting cycle start and at the end of sampled value, and obtain corresponding quadrature, be designated as Rb and Rd respectively；Calculate tale
Value Ntotal=NC×P+Rd-Rb；
Step 3：Total count value Ntotal and objective count value PkN/M are compared and draw difference, and by difference and lowest difference
Value is compared, and the initial value of described minimal difference is objective count value PkN/M, takes the minimum that less difference compares as next round
, for ÷ N divider except rate, M is ÷ M divider except rate for difference, wherein N；The fast of ongoing frequency is drawn according to described difference
Slowly, find out next resonance line using binary lookup rule, and export the control bit of its corresponding voltage controlled oscillator；Return
Return step 2, continue to search for resonance line, until binary lookup finishes；
Step 4：The control bit of the voltage controlled oscillator corresponding to optimal tuning line of output minimal difference record, based on described
Voltage-setting circuitry closes cycle of phase-locked loop, recovers closed loop states, after the first setting time, cycle of phase-locked loop is stable, base
Detect the control voltage of described voltage controlled oscillator in described comparison circuit, if the control voltage of described voltage controlled oscillator exceeds setting
Scope, then return to step one, recalibrates；If the control voltage of described voltage controlled oscillator is in setting range, complete to calibrate.
9. transmitting frequency calibration method according to claim 8 it is characterised in that：In step one, described first setting voltage
Vset is the half of supply voltage amplitude.
10. transmitting frequency calibration method according to claim 8 it is characterised in that：In step 2, described sample circuit is in each phase
The rising edge of position signal is sampled to described reference frequency signal.
11. transmitting frequency calibration method according to claim 8 it is characterised in that：In step 3, described binary lookup rule
For dichotomy.
12. transmitting frequency calibration method according to claim 8 it is characterised in that：In step 4, described first setting time is led to
The counting crossing described second counter completes.
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| KR102375949B1 (en) * | 2015-01-02 | 2022-03-17 | 삼성전자주식회사 | Apparatus and method for controlling output of frequency synthesizer |
| CN105991130B (en) * | 2015-03-02 | 2019-02-05 | 原相科技股份有限公司 | The four phase clock pulse generators with self detection of timing |
| CN106301355B (en) * | 2015-06-08 | 2019-03-08 | 京微雅格（北京）科技有限公司 | A kind of device of multiphase clock output |
| US10402166B2 (en) * | 2016-02-05 | 2019-09-03 | Sony Corporation | System and method for processing data in an adder based circuit |
| CN106788404B (en) * | 2016-11-15 | 2020-04-28 | 中国电子科技集团公司第四十一研究所 | Automatic calibration circuit and method for phase-locked loop frequency synthesizer |
| CN107820681B (en) * | 2017-02-08 | 2021-03-02 | 香港应用科技研究院有限公司 | Fast coarse and fine tuning calibration of multi-curve calibrated synthesizer within target window |
| CN106936428A (en) * | 2017-02-24 | 2017-07-07 | 苏州威发半导体有限公司 | The implementation method of automatic frequency control in phase-locked loop circuit |
| US10250266B2 (en) * | 2017-07-24 | 2019-04-02 | Nxp B.V. | Oscillator calibration system |
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| CN108063618B (en) * | 2017-12-20 | 2021-09-28 | 广州润芯信息技术有限公司 | VCO automatic calibration circuit and method |
| CN108259036B (en) * | 2018-01-09 | 2021-09-28 | 上海顺久电子科技有限公司 | VCO, frequency calibration method thereof, electronic device, and computer storage medium |
| CN108988853B (en) * | 2018-07-04 | 2020-11-10 | 西安电子科技大学 | Digital auxiliary locking circuit |
| CN109257043B (en) * | 2018-10-25 | 2021-03-30 | 电子科技大学 | High-speed broadband division chain applied to phase-locked loop frequency synthesizer |
| CN109743059B (en) * | 2019-02-20 | 2023-03-24 | 上海磐启微电子有限公司 | Digital RC oscillator and automatic calibration method |
| CN113098508B (en) * | 2021-05-13 | 2023-12-15 | 江苏集萃智能集成电路设计技术研究所有限公司 | Phase locked loop |
| CN113452365B (en) * | 2021-07-05 | 2022-08-09 | 广东工业大学 | Automatic frequency correction circuit and correction method suitable for under-sampling phase-locked loop |
| CN117278026B (en) * | 2023-10-09 | 2024-05-10 | 湖南迈克森伟电子科技有限公司 | Radio frequency self-calibration method |
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