CN109743059B - Digital RC oscillator and automatic calibration method - Google Patents
Digital RC oscillator and automatic calibration method Download PDFInfo
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- CN109743059B CN109743059B CN201910125435.1A CN201910125435A CN109743059B CN 109743059 B CN109743059 B CN 109743059B CN 201910125435 A CN201910125435 A CN 201910125435A CN 109743059 B CN109743059 B CN 109743059B
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Abstract
The invention discloses a digital RC oscillator, which comprises a comparator circuit, a capacitor charging and discharging circuit, a reference voltage generation module, a clock calibration module and a digital signal processing module, wherein the comparator circuit is connected with the capacitor charging and discharging circuit; the clock calibration module includes a zero crossing counter. The invention has the following advantages: 1. the digital processing module is utilized to reduce the power consumption of the circuit and reduce the change of the output frequency along with the process angle; 2. a digital calibration algorithm is provided, which can realize internal automatic calibration; 3. the use of automatic calibration improves the accuracy of the generated clock.
Description
Technical Field
The invention relates to the field of clock sources of integrated circuits, in particular to a digital RC oscillator and an automatic calibration method.
Background
For an on-chip RC (resistor-capacitor) oscillator, because a process error exists in a CMOS (Complementary Metal-Oxide-Semiconductor) process, errors may occur in a manufactured capacitor and resistor and in a MOS (Metal, oxide, semiconductor) transistor size and a design value. The CMOS technology can control the precision of the capacitance of the gate oxide within +/-20%, some technologies can keep within +/-10%, and the error of the resistance is within +/-20%. Due to the influence of process errors, the accuracy of the on-chip integrated oscillator is low. In addition, variations in supply voltage and temperature also result in less accurate on-chip oscillators.
The traditional digital RC oscillator adopts a controllable current source array or a capacitor array to realize digital calibration. The circuit mainly comprises the following components: the device comprises a comparator reference voltage generation module, a capacitor charging calibratable current generation module, a comparator circuit, an RS shaping circuit and a charging and discharging capacitor circuit. The comparator reference voltage generation module and the capacitance charging calibratable current generation module are composed of a current source, a current mirror circuit and a frequency calibration circuit. Basic working principle of digital RC oscillator: the capacitor is charged through the current source, the obtained charging voltage is compared with the reference voltage, and the output of the comparator is used for controlling the charging and discharging of the capacitor so as to generate the oscillation clock. According to the traditional digital RC oscillator, digital calibration needs to be controlled by an external MCU (microprogrammed control Unit), automatic calibration cannot be realized, and a differential structure is adopted, so that the power consumption of a circuit is increased.
Therefore, those skilled in the art have been devoted to developing a digital RC oscillator and an automatic calibration method thereof in which a digital processing module replaces an external MCU (micro controller Unit).
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the technical problem to be solved by the present invention is how to improve the clock accuracy of the digital RC oscillator and achieve automatic calibration.
In order to achieve the above purpose, the inventor has found through research that automatic calibration can be achieved by using a digital processing module in a digital RC oscillator, and power consumption of a circuit can be reduced. Thus, in one embodiment of the present invention, a digital RC oscillator is provided, comprising a comparator circuit, a capacitor charging and discharging circuit, a reference voltage generating module, a clock calibration module and a digital signal processing module; the clock calibration module comprises a zero-crossing counter, a clock signal CLK _ OUT and a reference clock signal CLK _ REF are used as the input of the clock calibration module, output signals RC _ calibration and RC _ success of the clock calibration module are respectively used as the input of a reference voltage generation module and a digital processing signal processing module, reference voltage Vref generated by the reference voltage generation module and voltage Vc generated by charging of a capacitor charging and discharging circuit are used as the input voltages at two ends of a comparison operational amplifier of a comparator circuit, the RC _ success signal and the output signal of a comparator OP circuit are used as the input of the digital processing signal module, the digital processing signal module outputs an MOS _ SW signal and the clock signal CLK _ OUT, and the MOS _ SW signal controls the capacitor charging and discharging circuit.
Optionally, in the digital RC oscillator in the above embodiment, the reference voltage generating module adopts a resistor voltage dividing structure, and controls the size of the access resistor according to the RC _ calibration, so as to dynamically control the size of the reference voltage Vref.
Optionally, in the digital RC oscillator in any of the above embodiments, the clock calibration module is configured to determine whether the clock signal CLK _ OUT and the reference clock signal CLK _ REF are synchronous.
Alternatively, in the digital RC oscillator in any of the above embodiments, the comparator circuit outputs a high level when Vref > Vc and outputs a low level when Vref < Vc.
Optionally, in the digital RC oscillator in any embodiment, the digital signal processing module is a digital logic circuit.
Optionally, in the digital RC oscillator in any of the above embodiments, the digital signal processing module includes a D divider and a digital logic gate circuit. When the signal RC _ success is low, one path of the periodic high-low signals output by the comparator is used as a sampling clock of the D trigger to be divided by 2 and then converted into a CLK _ OUT clock signal with the duty ratio of 50%; and the other path of the clock signal needs to output an MOS _ SW signal after passing through a digital logic delay delta t circuit to be used as a switch of a capacitor charging and discharging circuit, wherein in delta t time, the CLK _ OUT signal changes an RC _ Calibration signal through a clock Calibration module, and then the size of an input signal Vref of the operational amplifier is changed. When the signal RC _ success is high, one path of the output signal of the comparator is used to generate a CLK _ OUT clock signal through the D flip-flop, and the other path of the output signal can directly output a MOS _ SW signal without digital logic. In summary, the D flip-flop is used to generate the CLK _ OUT signal, so that when the same frequency is obtained, the power consumption of the circuit is reduced by nearly half, and the mismatch of two current sources is eliminated.
Optionally, in the digital RC oscillator in any of the above embodiments, a current source is used to charge the capacitor charging and discharging circuit, and the capacitor charging and discharging circuit charges the generated voltage Vc.
Optionally, in the digital RC oscillator in any of the above embodiments, when the RC _ success signal is at a high level, it indicates that the calibration is completed, at this time, the signal Vref maintains a constant voltage, and the MOS _ SW signal output by the digital processing DSP module is at a high level and a low level that are regularly and periodically changed; when the RC _ success signal is low, it indicates that the reference voltage Vref changes to cause the frequency of the output clock signal CLK _ OUT to change continuously during calibration of the circuit.
Optionally, in the digital RC oscillator in any embodiment, a charging and discharging time of a capacitor of the capacitor charging and discharging circuit is T = T + Δ T, where T is an output clock period and Δ T is a delay generated by the digital signal processing module, so as to reduce a change of an output clock frequency with a process corner, and Δ T < < T needs to be satisfied.
In another preferred embodiment of the present invention, using any one of the digital RC oscillators in the above embodiments, the inventors designed an automatic calibration method, which can realize internal automatic calibration. The method comprises the following steps:
s10, converting a reference clock signal with a fixed period, wherein the reference clock CLK _ REF is converted into the reference clock signal with the fixed period in the clock calibration module through internal logic;
s20, calculating a time window, and taking a half of the fixed period as a time window;
s30, recording the frequency of the clock signal, and recording the frequency of the clock signal CLK _ OUT passing through a zero-crossing counter in the time window;
s40, judging whether a calibration condition is met;
s50, when the calibration condition is met, completing calibration;
and S60, when the calibration condition is not met, changing the clock signal CLK _ OUT according to the change of the reference voltage Vref, and returning to the step of executing S30.
Optionally, in the automatic calibration method in the above embodiment, the step S60 further includes:
s61, the clock calibration module changes the output signal RC _ calibration;
s62, in response to the change of the output signal RC _ calibration, the reference voltage Vref output by the reference voltage generation module changes;
s63, responding to the change of the reference voltage Vref, and changing the output of the comparator circuit;
s64, in response to the output change of the comparator OP circuit, the frequency transmission of the clock signal CLK _ OUT is changed, and step S30 is executed again.
Optionally, in the automatic calibration method in any one of the above embodiments, the calibration condition in S40 is that the number of times that the clock signal CLK _ OUT passes through the zero-cross counter in the time window is two, which is a ratio of the time window to an oscillation clock period.
Optionally, in the automatic calibration method in any of the above embodiments, in the step S50, the RC _ success signal is output as a high level, and the clock signal CLK _ OUT is a required frequency.
Optionally, in the automatic calibration method in any of the above embodiments, a frequency of the reference clock CLK _ REF is 125KHz, the fixed period is 128us, and a frequency of the clock signal CLK _ OUT is 31.25KHz.
The digital RC oscillator and the automatic calibration method provided by the invention realize automatic clock calibration and output stable clock signals through a closed loop feedback system. Has the following advantages: 1. the digital processing module is utilized to reduce the power consumption of the circuit and reduce the change of the output frequency along with the process angle; 2. a digital calibration algorithm is provided, which can realize internal automatic calibration; 3. the use of automatic calibration improves the accuracy of the generated clock.
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.
Drawings
FIG. 1 is a schematic diagram of a conventional digital RC oscillator;
FIG. 2 is a schematic structural diagram of a preferred embodiment of the present invention;
FIG. 3 is a flow chart of a preferred embodiment of the present invention;
FIG. 4 is a flowchart of step S60 according to a preferred embodiment of the present invention.
Detailed Description
The technical contents of the preferred embodiments of the present invention will be more clearly and easily understood by referring to the drawings attached to the specification. The present invention may be embodied in many different forms of embodiments and the scope of the invention is not limited to the embodiments set forth herein.
In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.
As shown in fig. 1, in a conventional digital RC oscillator using a controllable current source array, the main components of the circuit include: the circuit comprises a reference voltage generating module, a calibratable current generating module, a comparator circuit CMP1, a comparator circuit CMP2, an RS shaping circuit and a charging and discharging capacitor circuit. The reference voltage generation module and the calibratable current generation module are composed of a current source, a current mirror circuit and a frequency calibration circuit, and the basic working principle is as follows: the capacitor is charged through the calibratable current generating module to obtain a charging voltage, the reference voltage is obtained through the reference voltage generating module, the charging voltage and the reference voltage are input into the comparator circuit, and the charging and discharging of the capacitor are controlled through the output of the comparator circuit to generate the oscillation clock. The derivation of the frequency of the oscillator generated clock is as follows:
the inventor analyzes that in the traditional digital RC oscillator, the digital calibration needs to be controlled by an external MCU (microprogrammed control Unit), the automatic calibration cannot be realized, and the differential structure is adopted, so that the power consumption of the circuit is increased. Further, the inventors have found that automatic calibration can be achieved using a digital processing module in a digital RC oscillator and that the power consumption of the circuit can be reduced.
As shown in fig. 2, the digital RC oscillator according to the first embodiment of the present invention includes a comparator circuit, a capacitor charging and discharging circuit (within a dotted square frame), a reference voltage generating module, a clock calibration module, and a digital signal processing module; the clock calibration module comprises a zero-crossing counter, a clock signal CLK _ OUT and a reference clock signal CLK _ REF are used as the input of the clock calibration module, output signals RC _ calibration and RC _ success of the clock calibration module are respectively used as the input of a reference voltage generation module and a digital processing module, reference voltage Vref generated by a reference voltage parameter module and voltage Vc generated by charging of a capacitor charging and discharging circuit are used as the input voltages at two ends of a comparison operational amplifier of a comparator OP circuit, the RC _ success signal and the output signal of a comparator circuit are used as the input of a digital processing DSP module, the digital signal processing module outputs an MOS _ SW signal and the clock signal CLK _ OUT, and the MOS _ SW signal controls the capacitor charging and discharging circuit.
The reference voltage generation module realizes dynamic control of the size of the reference voltage Vref, and can adopt a resistance voltage division structure, realize the dynamic control of the size of the access resistance through RC _ calibration, and also adopt other structures capable of realizing the dynamic control of the size of the reference voltage Vref.
The clock calibration module is used for judging whether the clock signal CLK _ OUT and the reference clock signal CLK _ REF are synchronous or not, when the clock signal CLK _ OUT and the reference clock signal CLK _ REF are synchronous, the signal Vref keeps constant voltage, and the MOS _ SW signal output by the digital processing DSP module is a high level and a low level which are regularly and periodically changed; otherwise, the RC _ success signal is low, and the change of the reference voltage Vref causes the frequency of the output clock signal CLK _ OUT to change continuously.
The comparator circuit outputs a high level or a low level according to the comparison result of Vref and Vc. For example, when Vref > Vc, a high level is output, and when Vref < Vc, a low level is output; the opposite rule may also be used.
In the digital RC oscillator of any of the above embodiments, the digital signal processing module includes a D divider and a digital logic gate circuit. When the signal RC _ success is low, one path of the periodic high-low signals output by the comparator is used as a sampling clock of the D trigger to be divided by 2 and then converted into a CLK _ OUT clock signal with the duty ratio of 50%; and the other path of the clock signal needs to output an MOS _ SW signal after passing through a digital logic delay delta t circuit to be used as a switch of a capacitor charging and discharging circuit, wherein in delta t time, the CLK _ OUT signal changes an RC _ Calibration signal through a clock Calibration module, and then the size of an input signal Vref of the operational amplifier is changed. When the signal RC _ success is high, one path of the output signal of the comparator is used to generate a CLK _ OUT clock signal through the D flip-flop, and the other path of the output signal can directly output a MOS _ SW signal without digital logic. In summary, the D flip-flop is used to generate the CLK _ OUT signal, so that when the same frequency is obtained, the power consumption of the circuit is reduced by nearly half, and the mismatch of two current sources is eliminated.
The voltage Vc of the capacitor charging and discharging circuit can be generated by selectively charging the capacitor charging and discharging circuit using a current source.
In the digital RC oscillator of the embodiment, calibration conditions need to be set for automatic calibration, surface calibration is completed when the calibration conditions are met, the output clock signal CLK _ OUT meets the accuracy requirement, at this time, the signal Vref maintains a constant voltage, and the MOS _ SW signal output by the digital signal processing module is a regularly and periodically changing high-low level; when the calibration condition is not met, the variation of the reference voltage Vref causes the frequency of the output clock signal CLK _ OUT to vary continuously. Optionally, when the RC _ success signal is high as the calibration condition and the RC _ success signal is low, it indicates that the circuit is performing calibration.
Optionally, the charging and discharging time of the capacitor charging and discharging circuit is T = T + Δ T, where T is an output clock period and Δ T is a delay generated by the digital signal processing module, so that a change of an output clock frequency along with a process angle is reduced and Δ T < < T needs to be satisfied.
As shown in fig. 3, the automatic calibration method according to another embodiment of the present invention, using the digital RC oscillator according to the above embodiment, takes the frequency of the clock signal CLK _ OUT of 31.25KHz as an example, and includes the following steps:
s10, converting a reference clock signal with a fixed period, wherein the reference clock CLK _ REF is converted into the reference clock signal with the fixed period in the clock calibration module through internal logic, the frequency of the reference clock CLK _ REF is 125KHz, and the fixed period is 128us;
s20, calculating a time window, and taking one half of the fixed period, namely 64us, as the time window;
s30, recording the frequency of the clock signal, and recording the frequency of the clock signal CLK _ OUT passing through a zero-crossing counter in the time window;
s40, judging whether a calibration condition is met, and selecting the ratio of the number of times that the clock signal CLK _ OUT passes through the zero-crossing counter in the time window to the period of the oscillation clock as two as the calibration condition;
s50, when a calibration condition is met, completing calibration, wherein an RC _ success signal is at a high level, the clock signal CLK _ OUT is required frequency, and the frequency is 31.25KHz in the embodiment;
and S60, when the calibration condition is not met, changing the clock signal CLK _ OUT through the change of the reference voltage Vref, and returning to execute S30.
As shown in fig. 4, optionally, the step S60 further includes:
s61, the clock calibration module changes the output signal RC _ calibration;
s62, responding to the change of the output signal RC _ calibration, and changing the reference voltage Vref output by the reference voltage RC _ Vref module;
s63, responding to the change of the reference voltage Vref, and changing the output of the comparator circuit;
s64, in response to the output change of the comparator circuit, the frequency of the clock signal CLK _ OUT is changed, and step S30 is executed again.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. A digital RC oscillator is characterized by comprising a comparator circuit, a capacitor charging and discharging circuit, a reference voltage generation module, a clock calibration module and a digital signal processing module; the clock calibration module comprises a zero-crossing counter, a clock signal CLK _ OUT and a reference clock signal CLK _ REF are used as the input of the clock calibration module, output signals RC _ calibration and RC _ success of the clock calibration module are respectively used as the input of the reference voltage generation module and the digital signal processing module, reference voltage Vref generated by the reference voltage generation module and voltage Vc generated by charging of the capacitor charging and discharging circuit are used as the input voltages at two ends of the comparison operation and amplification of the comparator circuit, the RC _ success signal and the output signal of the comparator circuit are used as the input of the digital signal processing module, the digital signal processing module outputs an MOS _ SW signal and the clock signal CLK _ OUT, and the MOS _ SW signal controls the capacitor charging and discharging circuit.
2. The digital RC oscillator of claim 1, wherein the reference voltage generating module employs a resistor voltage dividing structure, controls the magnitude of the access resistor according to the RC _ calibration, and dynamically controls the magnitude of the reference voltage Vref if the clock signal CLK _ OUT is not synchronized with the reference clock signal CLK _ REF; the reference voltage Vref maintains a constant voltage if the clock signal CLK _ OUT is synchronized with the reference clock signal CLK _ REF.
3. The digital RC oscillator of claim 2, wherein the clock calibration module is to determine whether the clock signal CLK _ OUT and the reference clock signal CLK _ REF are synchronized.
4. The digital RC oscillator of claim 3, wherein the comparator circuit outputs a high level when Vref > Vc and a low level when Vref < Vc.
5. The digital RC oscillator of claim 4, wherein the digital signal processing module is a digital logic circuit.
6. The digital RC oscillator of claim 5, wherein the digital processing DSP block comprises a D flip-flop, and the clock signal CLK _ OUT is converted to a clock signal having a duty cycle of 50% after being divided by 2 by the D flip-flop.
7. The digital RC oscillator of claim 1, wherein a high level of the RC success signal indicates that calibration has been completed, and a low level of the RC success signal indicates that the circuit is in calibration.
8. A method of automatic calibration using a digital RC oscillator according to any of claims 1 to 7, characterized in that the method comprises the steps of:
s10, converting a reference clock signal with a fixed period, wherein the reference clock CLK _ REF is converted into the reference clock signal with the fixed period in the clock calibration module through internal logic;
s20, calculating a time window, and taking a half of the fixed period as a time window;
s30, recording the frequency of a clock signal, and recording the frequency of the clock signal CLK _ OUT passing through a zero-crossing counter in the time window;
s40, judging whether a calibration condition is met;
s50, when the calibration condition is met, outputting an RC _ success signal as a high level, and completing calibration;
and S60, when the calibration condition is not met, changing the clock signal CLK _ OUT through the change of the reference voltage Vref, and returning to execute S30.
9. The auto-calibration method of claim 8, wherein the S60 further comprises:
s61, the clock calibration module changes the output signal RC _ calibration;
s62, responding to the change of the output signal RC _ calibration, and changing the reference voltage Vref output by the reference voltage generation module;
s63, responding to the change of the reference voltage Vref, and changing the output of the comparator circuit;
and S64, responding to the output change of the comparator circuit, changing the frequency transmission of the clock signal CLK _ OUT, and re-executing the step S30.
10. The automatic calibration method according to claim 8, wherein the reference clock CLK _ REF has a frequency of 125KHz, the fixed period is 128us, and the clock signal CLK _ OUT has a frequency of 31.25KHz; the calibration condition is that the number of times the clock signal CLK _ OUT passes through the zero crossing counter within the time window is 2, which is the ratio of the time window to the period of the oscillation clock.
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| CN110995204B (en) * | 2019-12-12 | 2021-06-11 | 思瑞浦微电子科技（苏州）股份有限公司 | Oscillator for outputting multiple duty ratio pulse signals |
| CN113037281B (en) * | 2021-02-23 | 2024-02-20 | 宏晶微电子科技股份有限公司 | Clock signal generating device and clock signal generating method |
| CN112953465B (en) * | 2021-03-09 | 2022-06-21 | 天津大学 | Configurable relaxation oscillator based on resistance-capacitance array |
| CN113131930B (en) * | 2021-04-26 | 2022-11-29 | 广州鸿博微电子技术有限公司 | Frequency temperature compensation circuit for MCU high-frequency clock and implementation method thereof |
| CN113794446B (en) * | 2021-09-17 | 2023-10-27 | 上海磐启微电子有限公司 | RC oscillator with frequency not changing with temperature and power supply voltage |
| CN113922813B (en) * | 2021-10-18 | 2023-03-10 | 苏州聚元微电子股份有限公司 | Frequency calibration method of numerical control oscillator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
| CN104135285A (en) * | 2014-08-07 | 2014-11-05 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN107741757A (en) * | 2017-10-13 | 2018-02-27 | 广州市时芯电子科技有限公司 | Chip precision resister self-calibration circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
| CN104135285A (en) * | 2014-08-07 | 2014-11-05 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN107741757A (en) * | 2017-10-13 | 2018-02-27 | 广州市时芯电子科技有限公司 | Chip precision resister self-calibration circuit |
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