CN104135285A - Frequency calibration circuit and method thereof - Google Patents

Frequency calibration circuit and method thereof Download PDF

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Publication number
CN104135285A
CN104135285A CN201410384467.0A CN201410384467A CN104135285A CN 104135285 A CN104135285 A CN 104135285A CN 201410384467 A CN201410384467 A CN 201410384467A CN 104135285 A CN104135285 A CN 104135285A
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described
frequency
voltage
phase
controlled oscillator
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CN201410384467.0A
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CN104135285B (en
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周阳阳
严皓
秦鹏
周健军
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上海交通大学
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Abstract

The invention provides a frequency calibration circuit and a method thereof. The frequency calibration circuit comprises a phase lock loop circuit, an M-dividing divider for generating a plurality of phase signals, a sampling circuit for sampling on the rising edges of the phase signals, a first counter for counting reference frequency signals, a second counter counting first phase signals, a logical control circuit for comparing a count value with a target count value to obtain a minimum difference value, and looking up a control bit of a voltage-controlled oscillator through the difference value, and a comparison circuit for judging whether the control voltage of the voltage-controlled oscillator is in a set range or not. The method comprises the following steps: sampling the reference frequency signals to obtain a total count value; comparing the total count value with a target count value; selecting a next resonance line according to a binary lookup flow till binary lookup ends; and outputting a resonance line corresponding to a minimum error in order that the output frequency of the voltage-controlled oscillator reaches a required value. Through adoption of the frequency calibration circuit and the method thereof, the speed and accuracy are increased, and the requirement on the working frequency of a digital circuit is lowered, so that a design method is simplified.

Description

A kind of frequency calibration circuit and method thereof

Technical field

The present invention relates to integrated circuit fields, particularly relate to a kind of frequency calibration circuit and method thereof.

Background technology

At wireless communication field, phase-locked loop frequency integrator (Phase Lock Loop, PLL) is a requisite part in radio transmitting and receiving chip.Phase-locked loop circuit produces stable, the signal of the certain frequency of low phase noise.In Modern wireless communication chip, due to being on the increase of wireless communication protocol, consider cost and the market factor, support multiband, multimodal radio transmitting and receiving chip becomes main flow.Therefore, phase-locked loop module need to be supported the output of multiband.Because a plurality of phase-locked loops will certainly bring power consumption, the excessive problem of area, broadband single phase-locked loop circuit becomes the main flow in market.

In phase-locked loop circuit, voltage controlled oscillator (Voltage Control Oscillator, VCO) is the nucleus module that produces frequency, and wideband voltage controlled oscillator is the study hotspot of RF application always.Originally wideband voltage controlled oscillator is realized by the larger varactor of capacitance variations scope, but in limited voltage-controlled scope, wideband voltage controlled oscillator means larger frequency modulation gain (K vCO), can cause the deterioration of loop phase noise.Consider that radio communication has strict requirement to the phase noise of phase-locked loop, the wideband voltage controlled oscillator of this single resonance line is replaced by multiple-tuned line pressure controlled oscillator very soon.

Multiple-tuned line pressure controlled oscillator utilizes capacitor array to realize frequency coarse adjustment, varactor is realized frequency fine tuning.Fine tuning process is realized by cycle of phase-locked loop, and extra coarse adjustment process is realized by automatic frequency calibration circuit (Auto Frequency Calibration, AFC).Therefore with respect to conventional phase locked loops, modern phase-locked loop circuit needs extra frequency calibration process.When needs are used fast lock phase-locked loop, the time that extra frequency calibration process consumes is considerable.

Therefore, broadband phase-looked loop Technology Need high-speed, high precision frequency calibration technology reduces extra locking time, to realize the object of quick lock in.Closed loop calibration counting is the earliest eliminated because it needs a large amount of closed loops locking time already, repeats no more.Frequency calibration technology is in recent years mainly based on the reference frequency signal cycle, with time-voltage transfer circuit (Time Voltage Converter, TVC) or be counted as sampling means, the former precision is higher, but be only suitable for integral frequency divisioil, the raising of the latter's velocity accuracy needs logical circuit more at a high speed, and optimal design is complicated.

Publication number is the patent of CN103312323A, what adopt is counted by the signal that in loop, frequency divider frequency division obtains reference frequency signal and oscillator output, two of phase frequency detector in loop input signals are counted, because these two signal frequencies differ less and reference frequency signal is lower, therefore time that need to be longer could differentiate.

Publication number is the patent of CN103346790A, employing is directly counted reference frequency signal and oscillator output, because oscillator frequency is larger, the method goes up a kind of method speed and precision all has a distinct increment, but lock into digital circuit operating frequency and design difficulty, high-frequency circuit cannot be applied, and needs first oscillator to be exported and carried out frequency division, thereby has reduced precision and speed.

Therefore, how can be fast, the high accuracy frequency calibration that must carry out phase-locked loop is those skilled in the art's problem demanding prompt solution.

Summary of the invention

The problems such as the shortcoming of prior art, the object of the present invention is to provide a kind of frequency calibration circuit and method thereof in view of the above, slow for solving prior art medium frequency collimation technique speed, and precision is low.

For achieving the above object and other relevant objects, the invention provides a kind of frequency calibration circuit, described frequency calibration circuit at least comprises:

Phase frequency detector, filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider, ÷ M divider, sample circuit, the first counter, the second counter, comparison circuit, logic control circuit;

Described phase frequency detector is connected in the reference frequency signal of input and the feedback frequency signal of described frequency divider output, for obtaining the phase difference between described reference frequency signal and described feedback frequency signal;

Described filter is connected in described phase frequency detector, for the output signal of described phase frequency detector is carried out to filtering;

Described voltage-setting circuitry is connected in described filter, for setting the control voltage of described voltage controlled oscillator;

Described voltage controlled oscillator is connected in described voltage-setting circuitry, and is subject to the control of the control bit signal of described logic control circuit output, for regulating frequency of oscillation;

Described ÷ N divider is connected in described voltage controlled oscillator, for the output signal of described voltage controlled oscillator is carried out to frequency division, and feeds back to described phase frequency detector;

Described ÷ M divider is connected in described voltage controlled oscillator, for the output signal of described voltage controlled oscillator is carried out to frequency division, produces a plurality of phase signals simultaneously;

Described sample circuit is connected in described ÷ M divider, for other phase signals except first phase signal of described ÷ M divider output are sampled;

Described the first counter is connected in described reference frequency signal, for described reference frequency signal is counted;

Described the second counter is connected in first phase signal of described ÷ M divider output, and it is counted;

Described comparison circuit is connected in the input of described voltage controlled oscillator, for the control voltage of judging described voltage controlled oscillator, whether in setting range, and exports result of determination;

Described logic control circuit is connected in described sample circuit, described the first counter, described the second counter and described comparison circuit; According to the Output rusults of described sample circuit, described the first counter, described the second counter, draw total count value, and relatively draw difference with objective count value, and difference and minimal difference are compared, get less difference as the minimal difference of next round comparison, according to described difference, utilize binary lookup rule searching resonance line, and export the control bit of its corresponding voltage controlled oscillator; According to the Output rusults of described comparison circuit, control described voltage-setting circuitry simultaneously.

Preferably, also comprise charge pump, described charge pump is connected between described phase frequency detector and described filter, for improving gain.

Preferably, described voltage-setting circuitry comprises the first switch and second switch, and one end of described the first switch connects the output of described filter, and the other end connects the input of described voltage controlled oscillator; Described second switch one end connects the input of described voltage controlled oscillator, and the other end connects the first setting voltage.

Preferably, described ÷ M divider produces 4 phase signals.

More preferably, described sample circuit comprises 3 high speed flip flops, and the signal input part of described high speed flip flop connects described reference frequency signal, and clock control end connects respectively each phase signal, and output is connected to described logic control circuit.

Preferably, described comparison circuit comprise the first comparator, the second comparator and or door, the positive input of described the first comparator is connected with the reverse input end of described the second comparator, and be connected in the output of described voltage-setting circuitry, the reverse input end of described the first comparator connects the first reference voltage, the positive input of described the second comparator connects the second reference voltage, described or door is connected to the output of described the first comparator and described the second comparator, and output described or door is connected to described logic control circuit.

Preferably, described logic control circuit comprises logic comparison module, is connected in minimal error comparison module and the binary lookup module of described logic comparison module, and the selection module that is connected in described minimal error comparison module and described binary lookup module.

For achieving the above object and other relevant objects, the invention provides a kind of transmitting frequency calibration method, described transmitting frequency calibration method at least comprises the following steps:

Step 1: disconnect cycle of phase-locked loop based on described voltage-setting circuitry, and the control voltage that described voltage controlled oscillator is set is the first setting voltage Vset;

Step 2: produce a first quantity P phase signal based on described ÷ M divider frequency division; Based on described sample circuit, described reference frequency signal is sampled; Based on described the first counter, described reference frequency signal fref is counted up to the second quantity k; Within the count cycle of described the first counter, based on described the second counter, the first phase signal is counted, be designated as N c; Sampled value when the record count cycle starts and finishes, and obtain corresponding quadrature, be designated as respectively Rb and Rd; Calculate total count value Ntotal=N c* P+Rd-Rb;

Step 3: total count value Ntotal and objective count value PkN/M are compared and draw difference, and difference and minimal difference are compared, the initial value of described minimal difference is objective count value PkN/M, get less difference as the minimal difference of next round comparison, wherein N is the rate of removing of ÷ N divider, and M is the rate of removing of ÷ M divider; According to described difference, draw the speed of current frequency, utilize binary lookup rule to find out next resonance line, and export the control bit of its corresponding voltage controlled oscillator; Return to step 2, continue to search resonance line, until binary lookup is complete;

Step 4: the control bit of the corresponding voltage controlled oscillator of optimal tuning line of output minimal difference record, based on the closed cycle of phase-locked loop of described voltage-setting circuitry, recover closed loop state, after the first setting-up time, cycle of phase-locked loop is stable, detects the control voltage of described voltage controlled oscillator, if the control voltage of described voltage controlled oscillator exceeds setting range based on described comparison circuit, return to step 1, recalibrate; If the control voltage of described voltage controlled oscillator, in setting range, completes calibration.

Preferably, in step 1, described the first setting voltage Vset is half of supply voltage amplitude.

Preferably, in step 2, described sample circuit is sampled to described reference frequency signal at the rising edge of each phase signal.

Preferably, in step 3, described binary lookup rule is dichotomy.

Preferably, in step 4, described the first setting-up time completes by the counting of described the second counter.

As mentioned above, frequency calibration circuit of the present invention and method thereof, have following beneficial effect:

The invention provides a kind of frequency calibration technology that can be applied to broadband phase-looked loop in the multi-mode wireless communications transceiver of broadband.Exemplary application of the present invention can realize the frequency calibration of quick high accuracy in the multiple-tuned line phase-locked loop of broadband.With respect to existing frequency calibration technology, the present invention can reduce the requirement of the operating frequency of digital circuit when realizing raising speed and precision, thus simplified design method.The present invention adopts open loop sampling, and the method based on counting is improved, and has increased the sampling mechanism of four phase places, thereby in the situation that not promoting count frequency, greatly improve sampling precision, thereby promoted frequency resolution, reduced the needed gate time of unitary sampling.Meanwhile, the present invention samples to the control voltage of voltage controlled oscillator, for automatically recalibrate in the situation of losing lock, has avoided the losing lock in the course of work.The selection algorithm of the oscillator optimal tuning line in the present invention has adopted binary lookup rule, added minimal error comparison mechanism simultaneously, avoided the error of binary lookup rule final step, guaranteed that the centre frequency of selected resonance line approaches the frequency of needs most.

Accompanying drawing explanation

Fig. 1 is shown as frequency calibration circuit diagram of the present invention.

Fig. 2 is shown as the ÷ 2 divider schematic diagrames that produce four phase signals in the present invention.

Fig. 3 is shown as logic control circuit schematic diagram of the present invention.

Fig. 4 is shown as transmitting frequency calibration method schematic flow sheet of the present invention.

Fig. 5 is shown as detection sampling time sequence figure of the present invention.

Fig. 6 is shown as voltage and the frequency change schematic diagram of transmitting frequency calibration method of the present invention.

Fig. 7 is shown as the frequency calibration process schematic diagram of transmitting frequency calibration method binary lookup of the present invention.

Element numbers explanation

1 frequency calibration circuit

11 phase frequency detectors

12 charge pumps

13 filters

14 voltage-setting circuitries

141 first switches

142 second switches

15 voltage controlled oscillators

16 ÷ N dividers

17 ÷ M dividers

171 first D-latchs

172 second D-latchs

18 sample circuits

181 first high speed flip flops

182 second high speed flip flops

183 third high speed triggers

19 first counters

20 second counters

21 comparison circuits

211 first comparators

212 second comparators

213 or door

22 logic control circuits

221 logic comparison modules

222 minimal error comparison modules

223 binary lookup modules

224 select module

S1~S4 step 1~step 4

Fref reference frequency signal

Vset the first setting voltage

The control voltage of Vtune voltage controlled oscillator

Phase1 the first phase signal

Phase2 the second phase signal

Phase3 third phase position signal

Phase4 the 4th phase signal

Vref1 the first reference signal

Vref2 the second reference signal

Clk the first clock signal

~Clk second clock signal

P the first quantity

K the second quantity

N cthe 3rd quantity

Embodiment

Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.

Refer to Fig. 1~Fig. 7.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.

As shown in Figure 1, the invention provides a kind of frequency calibration circuit 1, described frequency calibration circuit 1 at least comprises:

Phase frequency detector 11, filter 13, voltage-setting circuitry 14, voltage controlled oscillator 15, ÷ N divider 16, ÷ M divider 17, sample circuit 18, the first counter 19, the second counter 20, comparison circuit 21, logic control circuit 22;

As shown in Figure 1, described phase frequency detector 11 is connected in the reference frequency signal fref of input and the feedback frequency signal of described frequency divider output, for obtaining the phase difference between described reference frequency signal fref and described feedback frequency signal.

As shown in Figure 1, described frequency calibration circuit 1 also comprises charge pump 12, and described charge pump 12 is connected between described phase frequency detector 11 and described filter 13, for improving gain.

As shown in Figure 1, described filter 13 is connected in described phase frequency detector 11, for the output signal of described phase frequency detector 11 and described charge pump 12 is carried out to filtering.

As shown in Figure 1, described voltage-setting circuitry 14 is connected in described filter 13, for setting the control voltage Vtune of described voltage controlled oscillator.

As shown in Figure 1, described voltage-setting circuitry 14 comprises the first switch 141 and second switch 142, and one end of described the first switch 141 connects the output of described filter 13, and the other end connects the input of described voltage controlled oscillator 15; Described second switch 142 one end connect the input of described voltage controlled oscillator 15, and the other end connects the first setting voltage Vset.Switching by different switches can be set the control voltage Vtune of described voltage controlled oscillator.

As shown in Figure 1, described voltage controlled oscillator 15 is connected in described voltage-setting circuitry 14, and the control bit signal controlling that exported by described logic control circuit 22, for regulating frequency of oscillation, and then make described feedback frequency signal be infinitely close to described reference frequency signal fref.

As shown in Figure 1, described ÷ N divider 16 is connected in described voltage controlled oscillator 15, for the output signal of described voltage controlled oscillator 15 is carried out to frequency division, and feeds back to described phase frequency detector 11 and further adjusts.

As shown in Figure 1, described ÷ M divider 17 is connected in described voltage controlled oscillator 15, for the output signal of described voltage controlled oscillator 15 is carried out to frequency division, reduce the output frequency of described voltage controlled oscillator 15 to meet the work clock requirement of logical circuit, produce a plurality of phase signals simultaneously.

Described ÷ M divider 17 can produce a first quantity P phase signal, but described ÷ M divider 17 there is not positive connection except rate M and the first quantity P, a first quantity P phase signal can be produced by ÷ (P/2) divider, and described ÷ M divider 17 comprises that ÷ (P/2) divider and other dividers except rate take the divider that to form except rate be M.For example, when being set as 16, the first quantity P except rate M, be set as at 2 o'clock, described ÷ M divider 17 can consist of ÷ 8 dividers and ÷ 2 dividers.

In the present embodiment, described the first quantity P is set as 4, and described ÷ M divider 17 comprises ÷ 2 dividers, produces 4 phase signals.As shown in Figure 2, described ÷ 2 dividers consist of two D-latchs, the input of the second D-latch 172 described in the forward of the first D-latch 171 output termination, and export the first phase signal Phase1; The inverse output terminal output third phase position signal Phase3 of described the first D-latch 171; The forward output of described the second D-latch 172 is exported the second phase signal Phase2; The input of the first D-latch 171 described in the forward output termination of described the second D-latch 172, and export the 4th phase signal Phase4; The forward control end of described the first D-latch 171 and described the second D-latch 172 accesses the first clock signal C lk, and oppositely control end accesses second clock signal~Clk, and described second clock signal~Clk is the inverted signal of described the first clock signal C lk.

As shown in Figure 1, described sample circuit 18 is connected in described ÷ M divider 17, for other phase signals except the first phase signal Phase1 of described ÷ M divider 17 outputs are sampled.

As shown in Figure 1, in the present embodiment, described sample circuit 18 comprises 3 high speed flip flops, and the signal input part of described high speed flip flop connects described reference frequency signal fref, and the clock control end of the first high speed flip flop 181 connects described the second phase signal Phase2; The clock control end of the second high speed flip flop 182 connects described third phase position signal Phase3; The clock control end of third high speed trigger 183 connects described the 4th phase signal Phase4.The output of each high speed flip flop is connected to described logic control circuit 22.

Frequency calibration circuit of the present invention also may extend to even 16 phase places of 8 phase places, thus the significantly improving of the speed of realization and precision.8 phase places can be produced by ÷ 4 dividers, and the quantity of high speed flip flop is increased to 7; 16 phase places can be produced by ÷ 8 dividers, and the quantity of high speed flip flop is increased to 15.

As shown in Figure 1, described the first counter 19 is connected in described reference frequency signal fref, for described reference frequency signal fref is counted.

As shown in Figure 1, described the second counter 20 is connected in the first phase signal Phase1 of described ÷ M divider 17 outputs, and it is counted.

As shown in Figure 1, described comparison circuit 21 is connected in the input of described voltage controlled oscillator 15, for the control voltage Vtune that judges described voltage controlled oscillator, whether in setting range, and exports result of determination.

As shown in Figure 1, described comparison circuit 21 comprises the first comparator 211, the second comparator 212 and or door 213, the positive input of described the first comparator 211 is connected with the reverse input end of described the second comparator 212, and be connected in the output of described voltage-setting circuitry 14, the reverse input end of described the first comparator 211 connects the first reference voltage, the positive input of described the second comparator 212 connects the second reference voltage, described or door 213 is connected to the output of described the first comparator 211 and described the second comparator 212, output described or door 213 is connected to described logic control circuit 22.Described the first reference voltage is greater than described the second reference voltage, if the control voltage Vtune of described voltage controlled oscillator exceeds setting range (be greater than described the first reference voltage or be less than described the second reference voltage), described comparison circuit 21 sends frequency calibration circuit 1 described in signal controlling and re-starts calibration; If the control voltage Vtune of described voltage controlled oscillator is in setting range, calibration process completes.

As shown in Figure 1, described logic control circuit 22 is connected in described sample circuit 18, described the first counter 19, described the second counter 20 and described comparison circuit 21, according to the Output rusults of described sample circuit 18, described the first counter 19, described the second counter 20 and described comparison circuit 21, export the control signal of described voltage-setting circuitry 14 and the control bit signal of described voltage controlled oscillator 15, described voltage controlled oscillator 15 is carried out to coarse adjustment.

As shown in Figure 3, in the present embodiment, described logic control circuit 22 at least comprises logic comparison module 221, minimal error comparison module 222, binary lookup module 223 and selects module 224.Described logic comparison module 221 is exported to described minimal error comparison module 222 and described binary lookup module 223 by the difference relatively drawing; Described minimal error comparison module 222 compares continuous renewal minimal difference by difference and the current minimal difference of described logic comparison module 221 outputs; Described binary lookup module 223 is searched the control bit signal of described voltage controlled oscillator 15 according to the difference of described logic comparison module 221 outputs.In binary system comparison procedure, the control bit signal of the described voltage controlled oscillator 15 of record in the described binary lookup module 223 of described selection module 224 output.When all binary systems relatively complete, the control bit signal of the described voltage controlled oscillator 15 of record in the described minimal error comparison module 222 of described selection module 224 output.

As shown in Figure 4, the invention provides a kind of transmitting frequency calibration method, described transmitting frequency calibration method at least comprises the following steps:

Step 1 S1: disconnect cycle of phase-locked loop based on described voltage-setting circuitry 14, and be the first setting voltage Vset by the control voltage Vtune of described voltage controlled oscillator.

As shown in Figure 1, utilize described logic control circuit 22 to control described the first switch 141 disconnections, described second switch 142 closures in described voltage-setting circuitry 14, the control voltage Vtune of described voltage controlled oscillator is connected to described the first setting voltage Vset, in the present embodiment, described the first setting voltage Vset is half of supply voltage amplitude, even if the control voltage Vtune of described voltage controlled oscillator is set as VDD/2.

Step 2 S2: produce a first quantity P phase signal based on described ÷ M divider 17 frequency divisions; Based on described sample circuit, 18 couples of described reference frequency signal fref sample; Based on described the first counter, 19 couples of described reference frequency signal fref count up to the second quantity k; Within the count cycle of described the first counter 19, based on 20 couples of the first phase signal Phase1 of described the second counter, count, be designated as the 3rd quantity N c; Sampled value when the record count cycle starts and finishes, and obtain corresponding quadrature, be designated as respectively Rb and Rd; Calculate total count value Ntotal=N c* P+Rd-Rb.

For the different requirements of speed and precision, can do different settings to the first quantity P, the first quantity P is larger, and speed is faster, precision is higher.As shown in Figure 1, in the present embodiment, described the first quantity P is set as 4, produces 4 phase signals.

As shown in Figure 1, described the first phase signal Phase1 is connected to described the second counter 20, by described the second counter 20, it is counted; Described the second phase signal Phase2, described third phase position signal Phase3 and described the 4th phase signal Phase4 are connected to described sample circuit 18, be connected to respectively the clock control end of 3 high speed flip flops in described sample circuit 18, reference frequency signal fref described in the input termination of 3 high speed flip flops in described sample circuit 18, samples to described reference frequency signal fref at the rising edge of described the second phase signal Phase2, described third phase position signal Phase3 and described the 4th phase signal Phase4 respectively.

As shown in Figure 5, in the present embodiment, single gate time is kTref, and wherein the second quantity k is the count value of described first counter 19 of setting, and Tref is the cycle of reference frequency signal fref.

As shown in Figure 5, in single gate time kTref, 20 couples of described the first phase signal Phase1 of described the second counter count up to N since 1 c.

As shown in Figure 5, described the second phase signal Phase2, described third phase position signal Phase3 and described the 4th phase signal Phase4 sample to reference frequency signal fref, in single gate time kTref, sampled value when recording start and end, and the quadrant of the described first phase signal Phase1 at reference frequency signal fref rising edge place when determine starting and finishing, be designated as respectively Rb and Rd, and calculate total count value Ntotal=N c* P+Rd-Rb.As shown in Figure 5, in the present embodiment, sampled value during beginning is 011, and at quadrant 2. its corresponding rising edge, remembers Rb=2; Sampled value during end is 000, and at quadrant 4. its corresponding rising edge, remembers Rd=4.In single gate time kTref, 4 times of count values in the middle of total count cycle comprises in count cycle of 1 to Nc and the described third phase position signal Phase3 of incipient stage and the rising edge of described the 4th phase signal Phase4 counting, i.e. Ntotal=N c* P+Rd-Rb=N c* 4+4-2=N c* 4+2.Each sampled value, quadrature are concrete measuring value; Equally, described the first quantity P also can require to set according to side circuit, is not limited in data cited in the present embodiment.

In the present embodiment, do not increase high-speed counter, only increase by 3 triggers, just counting rate has been improved to 4 times; Can also show that precision is Δ f=M/4k * fref, and the precision of traditional counting structure is in the past Δ f=M/k * fref, precision of the present invention has improved 4 times.In the situation that high speed flip flop allows and phase-lock-ring output frequency is higher, the present invention can utilize ÷ 4 dividers to produce 8 phase signals, and even ÷ 8 dividers produce 16 phase signals, can realize 8 times, the precision of 16 times and speed.

Step 3 S3: based on described logic control circuit 22, total count value Ntotal and objective count value PkN/M are compared and draw difference, and difference and minimal difference are compared, the initial value of described minimal difference is objective count value PkN/M, get less difference as the minimal difference of next round comparison, wherein N is the rate of removing of ÷ N divider, and M is the rate of removing of ÷ M divider; According to described difference, draw the speed of current frequency, utilize binary lookup rule to find out next resonance line, and export the control bit of its corresponding voltage controlled oscillator; Return to step 2, continue to search resonance line, until binary lookup is complete.

Described resonance line has the control bit of corresponding voltage controlled oscillator, can control to realize the coarse adjustment to the output frequency of described voltage controlled oscillator 15 to the interior capacitor array of described voltage controlled oscillator 15.The control bit of voltage controlled oscillator corresponding to described resonance line is arranged by binary sized order, if described total count value Ntotal is less than objective count value PkN/M, illustrate that current frequency is excessively slow, by binary lookup rule (being dichotomy), seek scope is contracted to the first half of control bit, otherwise seek scope is contracted to the latter half of control bit, and by the control bit output finding.Return to step 2 S2, carry out searching of next group resonance line, according to binary lookup rule, constantly dwindle seek scope, until find last resonance line, now the resonance line of minimal difference record is optimal tuning line, by its corresponding control bit output.

Step 4 S4: the control bit of the corresponding voltage controlled oscillator of optimal tuning line of output minimal difference record, based on the closed cycle of phase-locked loop of described voltage-setting circuitry 14, recover closed loop state, after the first setting-up time, cycle of phase-locked loop is stable, detects the control voltage Vtune of described voltage controlled oscillator, if the control voltage Vtune of described voltage controlled oscillator exceeds setting range based on described comparison circuit 21, return to step 1, recalibrate; If the control voltage Vtune of described voltage controlled oscillator, in setting range, completes calibration.

As shown in Figure 1, utilize described logic control circuit 22 to control described the first switch 141 closures in described voltage-setting circuitry 14,142 disconnections of described second switch, make described cycle of phase-locked loop closed, enter operating state, cycle of phase-locked loop carries out phase adjusted.After the first setting-up time, cycle of phase-locked loop is stable, phase place locking, and described the first setting-up time is realized by described the second counter 20 countings, can set according to the corresponding time of physical circuit.When described the second counter 20 counts up to after described the first setting-up time, the control voltage Vtune of 21 pairs of described voltage controlled oscillators of described comparison circuit detects, if the control voltage Vtune of described voltage controlled oscillator exceeds setting range, in the present embodiment, the control voltage Vtune of described voltage controlled oscillator is greater than described the first reference voltage Vref 1 or is less than described the second reference voltage Vref 2, return to step 1 S1, recalibrate.If the control voltage Vtune of described voltage controlled oscillator is in setting range, in the present embodiment, the control voltage Vtune of described voltage controlled oscillator is greater than described the second reference voltage Vref 2 and is less than described the first reference voltage Vref 1, completes calibration.

Fig. 6 is voltage and the frequency change of transmitting frequency calibration method of the present invention, the frequency calibration process that Fig. 7 is binary lookup.The present invention is using 65nm process modeling, utilize Candence AMS emulation tool to carry out simulating, verifying, use Verilog A model partly to carry out modeling to phase-locked loop, build the voltage-controlled inductance and capacitance type oscillator of 9.75GHz~11.5GHz as described voltage controlled oscillator 15, the capacitor array of controlling with 6 bits, reference frequency 25MHz.First the described voltage controlled oscillator signal of high frequency is carried out to 16 frequency divisions (M=16), produce 4 phase signals.Single gate time kTref is 12 times of reference frequency cycles (k=12), and target setting frequency is 10.6GHz.As shown in Figure 6, the control voltage Vtune of described voltage controlled oscillator has just started to be set in 650mV (half of supply voltage), described frequency calibration circuit is searched the resonance line of described voltage controlled oscillator 15 according to binary lookup method, as shown in Figure 7,6 bit-binary are searched and need to be carried out 6 times, the control bit finding is first 100000, and now the output frequency of voltage controlled oscillator 15 is 10.67GHz; The control bit finding is for the second time 010000, and output frequency is 9.931GHz; The control bit finding is for the third time 011000, and output frequency is 10.3GHz; The control bit finding for the 4th time is 011100, and output frequency is 10.49GHz; The control bit finding for the 5th time is 011110, and output frequency is 10.58GHz; The control bit finding is for the last time 011111, and output frequency is 10.63GHz; Due to the existence of minimal error comparison algorithm, loop non-selected last binary lookup obtain 011111, but selected error less 011110, said frequencies search procedure used times 3.4 μ s.Then phase-locked loop enters operating state, and after phase-locked loop locking, the control voltage Vtune of described voltage controlled oscillator is stabilized in 822.8mV; The output frequency of described voltage controlled oscillator 15 is stabilized in 10.6GHz, consistent with target frequency.By the demonstration of the invention described above, can obtain frequency accuracy is Δ f=M/4k * fref=16/48 * 25MHz ≈ 8.3MHz.Hence one can see that, utilizes frequency calibration circuit of the present invention and method, for above-mentioned high frequency phase-locked ring model, realized high-precision high-speed frequency calibration.

Frequency calibration circuit of the present invention utilizes the control voltage of sample circuit sampling voltage controlled oscillator, to judge whether losing lock; Frequency divider carries out frequency division to voltage controlled oscillator output signal, reduces the frequency of voltage controlled oscillator to meet the work clock requirement of logical circuit, produces four phase signals simultaneously; The signal of counter after to frequency division counted, and reference frequency signal is counted; Logic control circuit compares according to the value of counter, to determine frequency speed; According to the result of logic comparison, carry out binary system hunting; Minimal error comparator compares the result of binary lookup, selects the resonance line of frequency error minimum.

First the present invention utilizes sample circuit, and rear three signals of take in four phase signals are clock, and reference frequency signal is sampled; Simultaneously, reference frequency signal and first phase signal are counted, when reference frequency signal count value reaches the second quantity k, read the value of another counter and the value of three phase samples, according to these values, carry out computing, obtain final total count value, the then count value comparison corresponding with the frequency of needs, thus draw the speed of current frequency, then according to the flow process of binary lookup, select next resonance line, repeat process above, until binary lookup finishes.Meanwhile, when each binary lookup finishes, all can relatively draw the frequency that minimal error is corresponding, finally export resonance line corresponding to minimal error.

The invention provides a kind of frequency calibration technology that can be applied to broadband phase-looked loop in the multi-mode wireless communications transceiver of broadband.Exemplary application of the present invention can realize the frequency calibration of quick high accuracy in the multiple-tuned line phase-locked loop of broadband.With respect to existing frequency calibration technology, the present invention can reduce the requirement of the operating frequency of digital circuit when realizing raising speed and precision, thus simplified design method.The present invention adopts open loop sampling, and the method based on counting is improved, and has increased the sampling mechanism of four phase places, thereby in the situation that not promoting count frequency, greatly improve sampling precision, thereby promoted frequency resolution, reduced the needed gate time of unitary sampling.Meanwhile, the present invention samples to the control voltage of voltage controlled oscillator, for automatically recalibrate in the situation of losing lock, has avoided the losing lock in the course of work.The selection algorithm of the oscillator optimal tuning line in the present invention has adopted binary lookup rule, added minimal error comparison mechanism simultaneously, avoided the error of binary lookup rule final step, guaranteed that the centre frequency of selected resonance line approaches the frequency of needs most.

The patent that the present invention is CN103346790A than China Patent Publication No. is in identical phase-locked loop application, can improve 4 times of precision, in the situation that keeping precision identical, speed can improve 4 times, break through the restriction that original technology locks into circuit work frequency, utilized simple 3 high speed flip flops to realize the breakthrough in speed and precision.Meanwhile, along with constantly dwindling of integrated circuit technology, trigger speed improves constantly, the present invention also can extend to even 16 phase places of 8 phase places very easily, thereby significantly improving of the speed of realization and progress, different from 4 phase places is the number that only increases trigger, less for the change of algorithm.In the present invention simultaneously, except frequency divider, outside trigger needs manually to optimize, all the other module operating frequencies are not high, are Verilog code and write, and portability is higher.

In sum, frequency calibration circuit of the present invention comprises phase frequency detector, filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider, ÷ M divider, sample circuit, the first counter, the second counter, comparison circuit, logic control circuit.Described phase frequency detector, filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider form cycle of phase-locked loop.Described ÷ M divider carries out frequency division to the output signal of described voltage controlled oscillator, and produces a plurality of phase signals.Described sample circuit is sampled to other phase signals except first phase signal of described ÷ M divider output.Described the first counter is counted the rising edge of described reference frequency signal.Described the second counter is counted the first phase signal rising edge of described ÷ M divider output.Described logic control circuit is exported the control signal of described voltage-setting circuitry and the control bit signal of described voltage controlled oscillator according to the Output rusults of described sample circuit, described the first counter, described the second counter and described comparison circuit, and described voltage controlled oscillator is carried out to coarse adjustment.Described comparison circuit whether in setting range, and is exported result of determination for the control voltage of judging described voltage controlled oscillator.First the present invention utilizes sample circuit, and rear three signals of take in four phase signals are clock, and reference frequency signal is sampled; Simultaneously, reference frequency signal and the first phase signal are counted, when reference frequency signal count value reaches the second quantity k, read the value of another counter and the value of three phase samples, according to these values, carry out computing, obtain final total count value, the then count value comparison corresponding with the frequency of needs, thus draw the speed of current frequency, then according to the flow process of binary lookup, select next resonance line, repeat process above, until binary lookup finishes.Meanwhile, when each binary lookup finishes, all can relatively draw the frequency that minimal error is corresponding, finally export resonance line corresponding to minimal error.The invention provides a kind of frequency calibration technology that can be applied to broadband phase-looked loop in the multi-mode wireless communications transceiver of broadband.Exemplary application of the present invention can realize the frequency calibration of quick high accuracy in the multiple-tuned line phase-locked loop of broadband.With respect to existing frequency calibration technology, the present invention can reduce the requirement of the operating frequency of digital circuit when realizing raising speed and precision, thus simplified design method.The present invention adopts open loop sampling, and the method based on counting is improved, and has increased the sampling mechanism of four phase places, thereby in the situation that not promoting count frequency, greatly improve sampling precision, thereby promoted frequency resolution, reduced the needed gate time of unitary sampling.Meanwhile, the present invention samples to the control voltage of voltage controlled oscillator, for automatically recalibrate in the situation of losing lock, has avoided the losing lock in the course of work.The selection algorithm of the oscillator optimal tuning line in the present invention has adopted binary lookup rule, added minimal error comparison mechanism simultaneously, avoided the error of binary lookup rule final step, guaranteed that the centre frequency of selected resonance line approaches the frequency of needs most.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.

Claims (12)

1. a frequency calibration circuit, is characterized in that, described frequency calibration circuit at least comprises:
Phase frequency detector, filter, voltage-setting circuitry, voltage controlled oscillator, ÷ N divider, ÷ M divider, sample circuit, the first counter, the second counter, comparison circuit, logic control circuit;
Described phase frequency detector is connected in the reference frequency signal of input and the feedback frequency signal of described frequency divider output, for obtaining the phase difference between described reference frequency signal and described feedback frequency signal;
Described filter is connected in described phase frequency detector, for the output signal of described phase frequency detector is carried out to filtering;
Described voltage-setting circuitry is connected in described filter, for setting the control voltage of described voltage controlled oscillator;
Described voltage controlled oscillator is connected in described voltage-setting circuitry, and is subject to the control of the control bit signal of described logic control circuit output, for regulating frequency of oscillation;
Described ÷ N divider is connected in described voltage controlled oscillator, for the output signal of described voltage controlled oscillator is carried out to frequency division, and feeds back to described phase frequency detector;
Described ÷ M divider is connected in described voltage controlled oscillator, for the output signal of described voltage controlled oscillator is carried out to frequency division, produces a plurality of phase signals simultaneously;
Described sample circuit is connected in described ÷ M divider, for other phase signals except first phase signal of described ÷ M divider output are sampled;
Described the first counter is connected in described reference frequency signal, for described reference frequency signal is counted;
Described the second counter is connected in first phase signal of described ÷ M divider output, and it is counted;
Described comparison circuit is connected in the input of described voltage controlled oscillator, for the control voltage of judging described voltage controlled oscillator, whether in setting range, and exports result of determination;
Described logic control circuit is connected in described sample circuit, described the first counter, described the second counter and described comparison circuit; According to the Output rusults of described sample circuit, described the first counter, described the second counter, draw total count value, and relatively draw difference with objective count value, and difference and minimal difference are compared, get less difference as the minimal difference of next round comparison, according to described difference, utilize binary lookup rule searching resonance line, and export the control bit of its corresponding voltage controlled oscillator; According to the Output rusults of described comparison circuit, control described voltage-setting circuitry simultaneously.
2. frequency calibration circuit according to claim 1, is characterized in that: also comprise charge pump, described charge pump is connected between described phase frequency detector and described filter, for improving gain.
3. frequency calibration circuit according to claim 1, it is characterized in that: described voltage-setting circuitry comprises the first switch and second switch, one end of described the first switch connects the output of described filter, and the other end connects the input of described voltage controlled oscillator; Described second switch one end connects the input of described voltage controlled oscillator, and the other end connects the first setting voltage.
4. frequency calibration circuit according to claim 1, is characterized in that: described ÷ M divider produces 4 phase signals.
5. frequency calibration circuit according to claim 4, it is characterized in that: described sample circuit comprises 3 high speed flip flops, the signal input part of described high speed flip flop connects described reference frequency signal, clock control end connects respectively each phase signal, and output is connected to described logic control circuit.
6. frequency calibration circuit according to claim 1, it is characterized in that: described comparison circuit comprises the first comparator, the second comparator and or door, the positive input of described the first comparator is connected with the reverse input end of described the second comparator, and be connected in the output of described voltage-setting circuitry, the reverse input end of described the first comparator connects the first reference voltage, the positive input of described the second comparator connects the second reference voltage, described or door is connected to the output of described the first comparator and described the second comparator, output described or door is connected to described logic control circuit.
7. frequency calibration circuit according to claim 1, it is characterized in that: described logic control circuit comprises logic comparison module, be connected in minimal error comparison module and the binary lookup module of described logic comparison module, and the selection module that is connected in described minimal error comparison module and described binary lookup module.
8. a transmitting frequency calibration method for the frequency calibration circuit as described in claim 1~7 any one, is characterized in that, described transmitting frequency calibration method comprises the following steps:
Step 1: disconnect cycle of phase-locked loop based on described voltage-setting circuitry, and the control voltage that described voltage controlled oscillator is set is the first setting voltage Vset;
Step 2: produce a first quantity P phase signal based on described ÷ M divider frequency division; Based on described sample circuit, described reference frequency signal is sampled; Based on described the first counter, described reference frequency signal is counted up to the second quantity k; Within the count cycle of described the first counter, based on described the second counter, the first phase signal is counted, be designated as N c; Sampled value when the record count cycle starts and finishes, and obtain corresponding quadrature, be designated as respectively Rb and Rd; Calculate total count value Ntotal=N c* P+Rd-Rb;
Step 3: total count value Ntotal and objective count value PkN/M are compared and draw difference, and difference and minimal difference are compared, the initial value of described minimal difference is objective count value PkN/M, get less difference as the minimal difference of next round comparison, wherein N is the rate of removing of ÷ N divider, and M is the rate of removing of ÷ M divider; According to described difference, draw the speed of current frequency, utilize binary lookup rule to find out next resonance line, and export the control bit of its corresponding voltage controlled oscillator; Return to step 2, continue to search resonance line, until binary lookup is complete;
Step 4: the control bit of the corresponding voltage controlled oscillator of optimal tuning line of output minimal difference record, based on the closed cycle of phase-locked loop of described voltage-setting circuitry, recover closed loop state, after the first setting-up time, cycle of phase-locked loop is stable, detects the control voltage of described voltage controlled oscillator, if the control voltage of described voltage controlled oscillator exceeds setting range based on described comparison circuit, return to step 1, recalibrate; If the control voltage of described voltage controlled oscillator, in setting range, completes calibration.
9. transmitting frequency calibration method according to claim 8, is characterized in that: in step 1, described the first setting voltage Vset is half of supply voltage amplitude.
10. transmitting frequency calibration method according to claim 8, is characterized in that: in step 2, described sample circuit is sampled to described reference frequency signal at the rising edge of each phase signal.
11. transmitting frequency calibration method according to claim 8, is characterized in that: in step 3, described binary lookup rule is dichotomy.
12. transmitting frequency calibration method according to claim 8, is characterized in that: in step 4, described the first setting-up time completes by the counting of described the second counter.
CN201410384467.0A 2014-08-07 2014-08-07 Frequency calibration circuit and method thereof CN104135285B (en)

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CN106301355A (en) * 2015-06-08 2017-01-04 京微雅格(北京)科技有限公司 A kind of device of multiphase clock output
CN106788404A (en) * 2016-11-15 2017-05-31 中国电子科技集团公司第四十研究所 A kind of phase-locked loop frequency synthesizer auto-calibration circuits and method
CN106936428A (en) * 2017-02-24 2017-07-07 苏州威发半导体有限公司 The implementation method of automatic frequency control in phase-locked loop circuit
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CN103346790A (en) * 2013-07-19 2013-10-09 苏州磐启微电子有限公司 Frequency synthesizer capable of being locked quickly
CN103346787A (en) * 2013-06-14 2013-10-09 浙江大学 Phase-locked loop frequency synthesizer structure with automatic frequency correction
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CN101257304A (en) * 2008-04-03 2008-09-03 北京大学 Double-loop circuit frequency synthesizer and method for tuning gross adjustment loop circuit
CN203289409U (en) * 2013-05-23 2013-11-13 江苏天源电子有限公司 Rapid automatic frequency calibration circuit capable of optimization
CN103346787A (en) * 2013-06-14 2013-10-09 浙江大学 Phase-locked loop frequency synthesizer structure with automatic frequency correction
CN103346790A (en) * 2013-07-19 2013-10-09 苏州磐启微电子有限公司 Frequency synthesizer capable of being locked quickly

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Publication number Priority date Publication date Assignee Title
CN105991130A (en) * 2015-03-02 2016-10-05 原相科技股份有限公司 Four-phase clock pulse generator with timing sequence self-detection
CN105991130B (en) * 2015-03-02 2019-02-05 原相科技股份有限公司 The four phase clock pulse generators with self detection of timing
CN106301355A (en) * 2015-06-08 2017-01-04 京微雅格(北京)科技有限公司 A kind of device of multiphase clock output
CN106301355B (en) * 2015-06-08 2019-03-08 京微雅格(北京)科技有限公司 A kind of device of multiphase clock output
CN106788404A (en) * 2016-11-15 2017-05-31 中国电子科技集团公司第四十研究所 A kind of phase-locked loop frequency synthesizer auto-calibration circuits and method
CN106936428A (en) * 2017-02-24 2017-07-07 苏州威发半导体有限公司 The implementation method of automatic frequency control in phase-locked loop circuit
CN108988853A (en) * 2018-07-04 2018-12-11 西安电子科技大学 Digital auxiliary lock circuit

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