CN110995204B - Oscillator for outputting multiple duty ratio pulse signals - Google Patents
Oscillator for outputting multiple duty ratio pulse signals Download PDFInfo
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- CN110995204B CN110995204B CN201911273993.9A CN201911273993A CN110995204B CN 110995204 B CN110995204 B CN 110995204B CN 201911273993 A CN201911273993 A CN 201911273993A CN 110995204 B CN110995204 B CN 110995204B
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- H03K3/017—Adjustment of width or dutycycle of pulses
Abstract
The invention discloses an oscillator for outputting a plurality of duty ratio pulse signals, comprising: a voltage generating unit for outputting a linearly raised voltage Vcap; a data selector for selecting different reference voltages as reference voltages Vref; the comparator is used for receiving the voltage Vcap output by the linear voltage generation unit and the reference voltage Vref selected by the data selector, and outputting an Out signal after comparison; the oscillation unit comprises a plurality of triggers and is used for outputting a plurality of control signals Q according to an Out signal and a clock signal; the Reset unit is used for generating a Reset signal Reset to Reset the oscillation unit and the data selector and generating a Reset signal Reset _ cap to Reset the voltage generation unit; and the output unit is used for generating a plurality of duty ratio pulse signals clk _ duty according to the Reset signal Reset and the control signal Q. The oscillator can output a plurality of pulse signals with accurate duty ratios under the same clock frequency.
Description
Technical Field
The invention belongs to the technical field of oscillators, and particularly relates to an oscillator for outputting a plurality of duty ratio pulse signals.
Background
An oscillator in an analog integrated circuit is a common circuit, and is used for generating a system clock, wherein an important index is a Duty Cycle (DC). Duty cycle is defined as the ratio of the high time to the clock cycle time in a clock cycle.
An oscillator in the prior art can provide a clock signal with a relatively accurate duty ratio, but in many applications, pulse signals with a plurality of accurate duty ratios need to be output at the same clock frequency for controlling functions such as maximum/minimum duty ratios, and the like, which cannot be realized by a conventional oscillator.
Therefore, in view of the above technical problems, it is necessary to provide an oscillator for outputting a plurality of duty ratio pulse signals.
Disclosure of Invention
The invention aims to provide an oscillator for outputting pulse signals with a plurality of duty ratios, so as to output the pulse signals with a plurality of accurate duty ratios at the same clock frequency.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
an oscillator for outputting a plurality of duty cycle pulse signals, the oscillator comprising:
a voltage generating unit for outputting a linearly raised voltage Vcap;
a data selector for selecting different reference voltages as reference voltages Vref;
the comparator is used for receiving the voltage Vcap output by the linear voltage generation unit and the reference voltage Vref selected by the data selector, and outputting an Out signal after comparison;
the oscillation unit comprises a plurality of triggers and is used for outputting a plurality of control signals Q according to an Out signal and a clock signal;
the Reset unit is used for generating a Reset signal Reset to Reset the oscillation unit and the data selector and generating a Reset signal Reset _ cap to Reset the voltage generation unit;
and the output unit is used for generating a plurality of duty ratio pulse signals clk _ duty according to the Reset signal Reset and the control signal Q.
In an embodiment, the voltage generating unit includes a first current source, a first MOS transistor and a first capacitor, the first MOS transistor is an NMOS transistor, and the first MOS transistor and the first capacitor are connected in parallel and then connected to the first current source.
In one embodiment, the oscillating unit includes a first D flip-flop and a second D flip-flop, the first D flip-flop is connected to the output terminal of the comparator, the second D flip-flop is connected to the first D flip-flop, and the first D flip-flop and the second D flip-flop are configured to output a first control signal Q1 and a second control signal Q2.
In one embodiment, the first D flip-flop and the second D flip-flop are respectively connected to a data selector, the first control signal Q1 and the second control signal Q2 are used for controlling the data selector, when Vcap crosses a reference voltage, a next reference voltage is selected as a reference voltage Vref, the reference voltages include a first reference voltage Vref1, a second reference voltage Vref2 and a third reference voltage Vref3, and Vref1 < Vref2 < Vref 3.
In one embodiment, the Reset unit includes a first and-gate device and a third D flip-flop, an input end of the first and-gate device is connected to the comparator and the oscillation unit, an output end of the first and-gate device is connected to an input end of the third D flip-flop, and an output end of the third D flip-flop is connected to the voltage generation unit, the data selector and the oscillation unit, respectively, and is configured to output the Reset signal Reset and the Reset signal Reset _ cap.
In an embodiment, a first delay unit and a first inverter are further connected in parallel between the output ends of the third D flip-flop.
In one embodiment, the output unit includes an RS flip-flop and a plurality of second inverters, the Reset signal Reset and the first control signal Q1 generate the first duty pulse signal clk _ duty1, and the Reset signal Reset and the second control signal Q2 generate the first duty pulse signal clk _ duty 2.
In an embodiment, a self-circulation anti-lock unit is arranged between the oscillation unit and the output end of the comparator, the self-circulation anti-lock unit includes a second voltage generation unit, a schmitt trigger and a third and gate device, the second voltage generation unit is used for outputting a linearly-increased voltage Vcap2, the voltage Vcap2 outputs an Out2 signal after passing through the schmitt trigger, and the Out signal and the Out2 signal output an Out _ Tick signal through the third and gate device.
In an embodiment, the second voltage generating unit includes a second current source, a second MOS transistor, a third MOS transistor, and a third inverter, the second MOS transistor is a PMOS transistor, the third MOS transistor is an NMOS transistor, a drain of the second MOS transistor is connected to a drain of the third MOS transistor, a source of the second MOS transistor is connected to the second current source, a source of the third MOS transistor is connected to the ground potential, an output end of the third inverter is connected to gates of the second MOS transistor and the third MOS transistor, and a second capacitor is connected between the drain of the second MOS transistor and the drain of the third MOS transistor and the ground potential.
In an embodiment, a fourth inverter, a second delay unit, and a fourth MOS transistor are connected between the third and device and the second voltage generating unit, and the fourth MOS transistor is an NMOS transistor.
Compared with the prior art, the invention has the following advantages:
the oscillator can output a plurality of pulse signals with accurate duty ratios under the same clock frequency;
the situation that the oscillator is locked under various accidental or extreme conditions can be avoided by the self-circulation anti-locking unit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of an oscillator in embodiment 1 of the present invention;
fig. 2a and 2b are schematic circuit diagrams of an output unit in embodiment 1 of the present invention, and fig. 2c is a schematic diagram of a clock signal clk;
FIG. 3 is a timing chart of the oscillator in accordance with embodiment 1 of the present invention during normal operation;
FIG. 4 is a timing diagram illustrating the oscillator locked according to embodiment 1 of the present invention;
fig. 5 is a schematic circuit diagram of an oscillator in embodiment 2 of the present invention;
FIG. 6 is a schematic circuit diagram of a self-circulation anti-lock unit in embodiment 2 of the present invention;
fig. 7 is a timing chart of the oscillator in normal operation according to embodiment 2 of the present invention;
fig. 8 is another timing chart of the oscillator in embodiment 2 of the present invention during normal operation.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
Also, it should be understood that, although the terms first, second, etc. may be used herein to describe various elements or structures, these described elements should not be limited by these terms. These terms are only used to distinguish these descriptive objects from one another. For example, the first control signal may be referred to as the second control signal, and similarly the second control signal may also be referred to as the first control signal, without departing from the scope of the present application.
The invention discloses an oscillator for outputting a plurality of duty ratio pulse signals, which comprises:
a voltage generating unit for outputting a linearly raised voltage Vcap;
a data selector for selecting different reference voltages as reference voltages Vref;
the comparator is used for receiving the voltage Vcap output by the linear voltage generation unit and the reference voltage Vref selected by the data selector, and outputting an Out signal after comparison;
the oscillation unit comprises a plurality of triggers and is used for outputting a plurality of control signals Q according to an Out signal and a clock signal;
the Reset unit is used for generating a Reset signal Reset to Reset the oscillation unit and the data selector and generating a Reset signal Reset _ cap to Reset the voltage generation unit;
and the output unit is used for generating a plurality of duty ratio pulse signals clk _ duty according to the Reset signal Reset and the control signal Q.
Furthermore, a self-circulation anti-lock unit is arranged between the output ends of the oscillation unit and the comparator, the self-circulation anti-lock unit comprises a second voltage generation unit, a Schmidt trigger and a second AND gate device, the second voltage generation unit is used for outputting a linearly-increased voltage Vcap2, the voltage Vcap2 outputs an Out2 signal after passing through the Schmidt trigger, and the Out signal and the Out2 signal output an Out _ Tick signal through the second AND gate device.
The present invention is further illustrated by the following specific examples.
Example 1:
referring to fig. 1 and fig. 2a to 2c, which are schematic circuit diagrams of the oscillator in this embodiment, fig. 3 is a timing diagram of the oscillator in this embodiment during normal operation, which can output two pulse signals with precise duty ratios at the same clock frequency.
The oscillator in this embodiment includes:
a voltage generating unit 10 for outputting a linearly-raised voltage Vcap;
a data selector 20 for selecting different reference voltages Vref;
a comparator 30, configured to receive the voltage Vcap output by the linear voltage generation unit and the reference voltage Vref selected by the data selector, and output an Out signal after comparing the voltages Vcap and Vref;
an oscillation unit 40, including a plurality of flip-flops, for outputting a plurality of control signals Q according to an Out signal and a clock signal;
a Reset unit 50 for generating a Reset signal Reset to Reset the oscillation unit and the data selector, and generating a Reset signal Reset _ cap to Reset the voltage generation unit;
and the output unit is used for generating a plurality of duty ratio pulse signals clk _ duty according to the Reset signal Reset and the control signal Q.
The voltage generating unit 10 in this embodiment includes a first current source Iref, a first MOS transistor M1 and a first capacitor C1, the first MOS transistor M1 is an NMOS transistor, and the first MOS transistor M1 and the first capacitor C1 are connected in parallel and then connected to the first current source Iref. As shown in fig. 3, the voltage Vcap generated by the voltage generation unit 10 in the present embodiment increases linearly in voltage in each clock cycle.
The oscillating unit 40 includes a first D flip-flop D1 and a second D flip-flop D2, the first D flip-flop D1 is connected to the comparator output terminal, the second D flip-flop D2 is connected to the first D flip-flop D1, and the first D flip-flop D1 and the second D flip-flop D2 are configured to output a first control signal Q1 and a second control signal Q2.
The first D flip-flop D1 and the second D flip-flop D2 in this embodiment are respectively connected to the data selector, the first control signal Q1 and the second control signal Q2 are used for controlling the data selector, and when Vcap crosses a reference voltage, a next reference voltage is selected as the reference voltage Vref, as shown in fig. 3, the reference voltages include a first reference voltage Vref1, a second reference voltage Vref2, and a third reference voltage Vref3, and Vref1 < Vref2 < Vref 3.
The Reset unit 50 includes a first AND-gate device AND1 AND a third D flip-flop D3, an input terminal of the first AND-gate device AND1 is respectively connected to the comparator AMP AND the oscillating unit 40, an output terminal of the first AND-gate device AND1 is connected to an input terminal of the third D flip-flop D3, an output terminal of the third D flip-flop D3 is respectively connected to the voltage generating unit 10, the data selector 20 AND the oscillating unit 40, AND is configured to output a Reset signal Reset AND a Reset signal Reset _ cap, Reset the first flip-flop D1, the second flip-flop D2 AND the data selector by the Reset signal Reset, AND Reset the voltage generating unit by the Reset signal Reset _ cap.
Preferably, a first Delay unit Delay1 and a first inverter are further connected in parallel between the output ends of the third D flip-flop D3 in this embodiment.
Referring to fig. 2a and 2b, the output unit includes an RS flip-flop and a plurality of second inverters, the Reset signal Reset and the first control signal Q1 generate the first duty pulse signal clk _ duty1 through the RS flip-flop R1 and the plurality of inverters, and the Reset signal Reset and the second control signal Q2 generate the first duty pulse signal clk _ duty2 through the RS flip-flop R2 and the plurality of inverters.
In addition, referring to fig. 2c, in the present embodiment, the first control signal Q1 AND the second control signal Q2 output the clock signal clk after passing through the second AND gate device AND2, AND the pulse width of the clock signal clk is determined by the time delay of the first delay unit delay 1.
Referring to fig. 1 to fig. 3, when the oscillator normally operates, the voltage Vcap linearly increases every clock cycle, AND sequentially crosses the reference voltages Vref1, Vref2, AND Vref3, AND the control signals Q1 AND Q2 output by the D flip-flops D1 AND D2 control the data selector, so that the next reference voltage is selected as the reference voltage Vref of the comparator each time Vcap crosses one reference voltage, when the voltage Vcap crosses the third reference voltage Vref3, the first AND gate device AND1 outputs a rising edge pulse to generate Reset AND Reset _ cap signals, so that the voltage Vcap, all the D flip-flops, AND the data selector are Reset to the starting point of the next cycle, AND the next cycle is started along with the increase of the voltage Vcap, AND the cycle is repeated.
Referring to fig. 3, the final oscillator of this embodiment can accurately output two pulse signals clk _ duty1 and clk _ duty2 with different duty ratios.
Example 2:
the oscillator in embodiment 1 has a risk of being locked, and as shown in fig. 4, when two adjacent reference voltages are relatively close to each other, so that the graph Δ t is smaller than the flip speed of the comparator in the oscillator, the output of the comparator cannot generate two rising edge pulses and only one rising edge pulse when the two reference voltages are crossed, so that a logic error occurs later, and the oscillator is always locked and cannot output a clock signal any more.
Referring to fig. 5, in order to prevent the oscillator from being locked due to the above factors, a self-loop anti-lock unit 60 is added on the basis of embodiment 1, and when the output of the comparator fails to output the correct number of rising edges, the self-loop anti-lock unit intervenes to complement the missing rising edges, thereby preventing the oscillator from being locked.
Referring to fig. 5 AND 6, a self-circulation anti-lock unit 60 is disposed between the output ends of the oscillation unit AND the comparator in the embodiment, the self-circulation anti-lock unit 60 includes a second voltage generation unit 61, a schmitt trigger 62 AND a third AND gate device 63(AND3), the second voltage generation unit 60 is configured to output a linearly-increased voltage Vcap2, the voltage Vcap2 outputs an Out2 signal after passing through the schmitt trigger, AND the Out signal AND the Out2 signal output an Out _ Tick signal through the third AND gate device AND 3.
Specifically, the second voltage generating unit 61 includes a second current source, a second MOS transistor M2, a third MOS transistor M3, and a third inverter, the second MOS transistor M2 is a PMOS transistor, the third MOS transistor M3 is an NMOS transistor, a drain of the second MOS transistor M2 is connected to a drain of the third MOS transistor M3, a source of the second MOS transistor M2 is connected to the second current source, a source of the third MOS transistor M3 is connected to the ground potential, an output terminal of the third inverter is connected to gates of the second MOS transistor M2 and the third MOS transistor M2, and a second capacitor C2 is connected between the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 and the ground potential.
Further, a fourth inverter, a second Delay unit Delay2 AND a fourth MOS transistor M4 are connected between the third AND device AND3 AND the second voltage generating unit 61, AND the fourth MOS transistor M4 is an NMOS transistor.
Referring to fig. 7, in the case that the comparator cannot be turned over after outputting a rising edge, the Out output first rising edge is kept high all the time, and at this time, the self-circulation anti-lock unit internally oscillates itself, and two extra rising edge pulses (Out2) are generated every clock cycle, so that the oscillator can return to the initial state every time even if the oscillator is in error, and the oscillator cannot be locked.
Referring to fig. 8, in the case that the comparator cannot be turned over after outputting two rising edges, the Out output second rising edge is kept high all the time, and at this time, the self-circulation anti-lock unit internally oscillates itself, and an extra rising edge pulse (Out2) is generated every clock cycle, so that the oscillator can return to the initial state every time even if the oscillator is in error, and the oscillator cannot be locked.
It should be understood that, in the above embodiments, the generation of two pulse signals with accurate duty ratios is taken as an example for description, and in other embodiments, the generation of more pulse signals with accurate duty ratios can be realized by changing the number of the reference voltages Vref, and the like, which is not described herein any more.
The technical scheme shows that the invention has the following beneficial effects:
the oscillator can output a plurality of pulse signals with accurate duty ratios under the same clock frequency;
the situation that the oscillator is locked under various accidental or extreme conditions can be avoided by the self-circulation anti-locking unit.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (9)
1. An oscillator for outputting a plurality of duty cycle pulse signals, the oscillator comprising:
a voltage generating unit for outputting a linearly raised voltage Vcap;
a data selector for selecting different reference voltages as reference voltages Vref;
the comparator is used for receiving the voltage Vcap output by the linear voltage generation unit and the reference voltage Vref selected by the data selector, and outputting an Out signal after comparison;
the oscillation unit comprises a plurality of triggers and is used for outputting a plurality of control signals Q according to the Out signals, the oscillation unit comprises a first D trigger and a second D trigger, the input end clk of the first D trigger is connected with the output end of the comparator, the input end clk of the second D trigger is connected with the output end of the first D trigger, and the output end clk of the second D trigger is connected with the output end of the first D trigger
Connected to the output of the first D flip-flop
Connected to the input D of the first flip-flop and the output of the second flip-flop
The output end Q of the first D flip-flop and the output end Q of the second D flip-flop are respectively used for outputting a first control signal Q1 and a second control signal Q2;
the Reset unit is used for generating a Reset signal Reset to Reset the oscillation unit and the data selector and generating a Reset signal Reset _ cap to Reset the voltage generation unit;
the output unit is used for generating a plurality of duty ratio pulse signals clk _ duty according to the Reset signal Reset and the control signal Q, the Reset signal Reset and the first control signal Q1 generate a first duty ratio pulse signal clk _ duty1, and the Reset signal Reset and the second control signal Q2 generate a second duty ratio pulse signal clk _ duty 2.
2. The oscillator according to claim 1, wherein the voltage generating unit comprises a first current source, a first MOS transistor and a first capacitor, the first MOS transistor is an NMOS transistor, and the first MOS transistor and the first capacitor are connected in parallel and then connected to the first current source.
3. The oscillator of claim 1, wherein the output terminal Q of the first D flip-flop and the output terminal Q of the second D flip-flop are respectively connected to a data selector, the first control signal Q1 and the second control signal Q2 are used for controlling the data selector to select a next reference voltage as the reference voltage Vref when Vcap crosses a reference voltage, the reference voltages include a first reference voltage Vref1, a second reference voltage Vref2 and a third reference voltage Vref3, and Vref1 < Vref2 < Vref 3.
4. The oscillator according to claim 1, wherein the Reset unit comprises a first and gate device and a third D flip-flop, an input terminal of the first and gate device is connected to the comparator and the oscillating unit, an output terminal of the first and gate device is connected to an input terminal of the third D flip-flop, and an output terminal of the third D flip-flop is connected to the voltage generating unit, the data selector and the oscillating unit, respectively, for outputting the Reset signal Reset and the Reset signal Reset _ cap.
5. The oscillator according to claim 4, wherein a first delay unit and a first inverter are connected in parallel between the output terminal Q and the reset terminal R of the third D flip-flop.
6. The oscillator according to claim 1, wherein the output unit comprises an RS flip-flop and a plurality of second inverters.
7. The oscillator of claim 1, wherein a self-circulation anti-lock unit is disposed between the oscillation unit and the output terminal of the comparator, the self-circulation anti-lock unit includes a second voltage generation unit, a schmitt trigger, and a third and gate device, the second voltage generation unit is configured to output a linearly-increased voltage Vcap2, the voltage Vcap2 outputs an Out2 signal after passing through the schmitt trigger, and the Out signal and the Out2 signal output an Out _ Tick signal through the third and gate device.
8. The oscillator according to claim 7, wherein the second voltage generating unit comprises a second current source, a second MOS transistor, a third MOS transistor, and a third inverter, the second MOS transistor is a PMOS transistor, the third MOS transistor is an NMOS transistor, a drain of the second MOS transistor is connected to a drain of the third MOS transistor, a source of the second MOS transistor is connected to the second current source, a source of the third MOS transistor is connected to the ground potential, an output of the third inverter is connected to gates of the second MOS transistor and the third MOS transistor, and a second capacitor is connected between the drain of the second MOS transistor and the drain of the third MOS transistor and the ground potential.
9. The oscillator according to claim 7, wherein a fourth inverter, a second delay unit, and a fourth MOS transistor are connected between the third and gate device and the second voltage generating unit, and the fourth MOS transistor is an NMOS transistor.
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| US8754690B2 (en) * | 2012-10-26 | 2014-06-17 | International Business Machines Corporation | Programmable duty cycle setter employing time to voltage domain referenced pulse creation |
| CN105048811B (en) * | 2015-08-17 | 2017-06-09 | 西安交通大学 | The fixed frequency of ON time correction of DC DC converters is across period controller and method |
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