CN106559061B

CN106559061B - Duty ratio corrector

Info

Publication number: CN106559061B
Application number: CN201611059870.1A
Authority: CN
Inventors: 刘惩
Original assignee: Beijing Zhaoxin Electronic Technology Co ltd
Current assignee: Beijing Zhaoxin Electronic Technology Co ltd
Priority date: 2016-11-25
Filing date: 2016-11-25
Publication date: 2021-12-14
Anticipated expiration: 2036-11-25
Also published as: CN106559061A

Abstract

A duty ratio corrector. The duty cycle corrector comprises a first pulse swallower, a second pulse swallower and a decision and hold circuit. The first pulse swallower provides a first clock signal having a second duty cycle in accordance with a first input clock having a first duty cycle. The second pulse swallower provides a second clock signal having the second duty cycle in accordance with a second input clock having the first duty cycle. The decision and hold circuit provides an output clock having a duty ratio of 50% according to the first clock signal and the second clock signal. The phase difference between the first input clock and the second input clock is 180 degrees, and the second duty ratio is smaller than the first duty ratio.

Description

Duty ratio corrector

Technical Field

The present invention relates to a duty ratio corrector, and more particularly, to a duty ratio corrector generating a duty ratio of 50%.

Background

In recent years, the performance of consumer electronic products, such as mobile phones and tablet computers, has become more and more demanding. The need for increased clock speeds and accurate signal timing has also increased in order to be able to perform proper operations. In different electronic products, a clock signal having a Duty Cycle (Duty Cycle) of 50% is very important, for example: electronic products applied in Double Data Rate (DDR) or communication application fields. By using a clock signal with a stable duty cycle, jitter (jitter) can be avoided and a better eye diagram (eye diagram) can be obtained.

Disclosure of Invention

The invention provides a duty ratio corrector. The duty cycle corrector comprises a first pulse swallower (swallow), a second pulse swallower and a decision and hold circuit. The first pulse swallower provides a first clock signal having a second duty cycle in accordance with a first input clock having a first duty cycle. The second pulse swallower provides a second clock signal having the second duty cycle in accordance with a second input clock having the first duty cycle. The decision and hold circuit provides an output clock having a duty ratio of 50% according to the first clock signal and the second clock signal. The phase difference between the first input clock and the second input clock is 180 degrees, and the second duty ratio is smaller than the first duty ratio.

Furthermore, the present invention provides another duty cycle corrector. The duty cycle corrector comprises a decision and hold circuit. The decision and hold circuit provides an output clock having a duty ratio of 50% according to the first clock signal and the second clock signal. The phase difference between the first clock signal and the second clock signal is 180 degrees. The decision and hold circuit includes a first single-ended to differential converter, a second single-ended to differential converter, a first transmission gate, and a second transmission gate. The first single-ended to differential converter is configured to convert the first clock signal into a first differential clock signal and a second differential clock signal. The second single-ended to differential converter is configured to convert the second clock signal into a third differential clock signal and a fourth differential clock signal. The first transmission gate is coupled between a power source and an output terminal, wherein the first transmission gate is controlled by the first differential clock signal and the second differential clock signal. The second transmission gate is coupled between a ground terminal and the output terminal, wherein the second transmission gate is controlled by the third differential clock signal and the fourth differential clock signal. The decision and hold circuit provides the output clock via the output terminal. The first transmission gate and the second transmission gate are not simultaneously turned on.

Drawings

FIG. 1 is a diagram illustrating an electronic device according to an embodiment of the invention;

FIG. 2 is an exemplary circuit diagram showing the duty cycle corrector of FIG. 1;

fig. 3 is a signal waveform diagram showing the duty ratio corrector of fig. 2;

FIG. 4 is a diagram illustrating an electronic device according to another embodiment of the invention;

FIG. 5 is an exemplary circuit diagram showing the duty cycle corrector of FIG. 4; and

fig. 6 is a signal waveform diagram showing the duty ratio corrector in fig. 5.

Detailed Description

In order to make the aforementioned and other objects, features, and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:

fig. 1 shows an electronic device 100 according to an embodiment of the invention. The electronic device 100 includes a Phase Lock Loop (PLL) 110 and a Duty Cycle Corrector (DCC) 120. The phase-locked loop circuit 110 may provide the input clock CLK0 and the input clock CLK180 to the duty cycle corrector 120. In this embodiment, the input clock CLK0 and the input clock CLK180 have the same frequency F, i.e., the same period T and the same duty cycle. The phase difference between the input clock CLK0 and the input clock CLK180 is 180 degrees. In other words, the rising edge of the input clock CLK0 is different from the rising edge of the input clock CLK180 by a half cycle (i.e., T/2). The duty ratio corrector 120 includes a decision and hold (decision and hold) circuit 130. The decision and hold circuit 130 may provide an output clock CLKOUT having a 50% duty cycle based on the input clocks CLK0 and CLK180 for use by other circuits within the electronic device 100. In some embodiments, the phase-locked loop circuit 110 and the duty cycle corrector 120 are provided in the same integrated circuit.

Fig. 2 is an exemplary circuit diagram showing the duty ratio corrector 120 of fig. 1. Fig. 3 is a signal waveform diagram showing the duty ratio corrector 120 of fig. 2. Referring to fig. 2 and 3, the decision and hold circuit 130 includes single to differential (S2D)

converters

210 and 220 and

transmission gates

230 and 240. The single-ended to differential converter 210 may convert the input clock CLK0 into differential clock signals CLK0X and CLK 0B. In addition, the single-ended to differential converter 220 may convert the input clock CLK180 into differential clock signals CLK180X and CLK 180B. As shown in FIG. 3, the rising edge of the input clock CLK0 differs from the rising edge of the input clock CLK180 by one-half cycle (i.e., T/2). Furthermore, the rising edge of the clock signal CLK0X and the falling edge of the clock signal CLK0B are delayed by time D1 compared to the input clock CLK 0. Similarly, the rising edge of the clock signal CLK180X and the falling edge of the clock signal CLK180B are also delayed by time D1 compared to the input clock CLK 180.

The transmission gate 230 is coupled between the power supply VDD and the output terminal 250, and includes a PMOS transistor P1 and an NMOS transistor N1 connected in parallel. The PMOS transistor P1 is controlled by the differential clock signal CLK0B and the NMOS transistor N1 is controlled by the differential clock signal CLK 0X. When the transmission gate 230 is turned on, the output terminal 250 is coupled to the power supply VDD through the transmission gate 230, and the output clock CLKOUT at the output terminal 250 is maintained at the voltage value (i.e., the high logic level) of the power supply VDD. The transmission gate 240 is coupled between the ground GND and the output terminal 250, and includes a PMOS transistor P2 and an NMOS transistor N2 connected in parallel. The PMOS transistor P2 is controlled by the differential clock signal CLK180B and the NMOS transistor N2 is controlled by the differential clock signal CLK 180X. When the transmission gate 240 is turned on, the output terminal 250 is coupled to the ground GND through the transmission gate 240, and the output clock CLKOUT at the output terminal 250 maintains the voltage value (i.e., the low logic level) of the ground GND. Therefore, when the transmission gate 230 is turned on, the decision and hold circuit 120 operates at the first decision stage PD 1. Then, when the transmission gate 230 is switched from the conductive state to the non-conductive state and the transmission gate 240 is not yet conductive, the decision and hold circuit 120 operates in the first hold phase PH 1. Then, when the transmission gate 240 is turned on, the decision and hold circuit 120 operates in the second decision stage PD 2. Then, when the transmission gate 240 is switched from the conductive state to the non-conductive state and the transmission gate 230 is not yet conductive, the decision and hold circuit 120 operates at the second hold phase PH 2. It is noted that the time period of the first decision phase PD1 plus the first hold phase PH1 is the same as the time period of the second decision phase PD2 plus the second hold phase PH2, i.e. PD1+ PH 1-PD 2+ PH 2-T/2. In addition, the duty cycle of the input clocks CLK0 and CLK180 from the phase-locked loop circuit 110 of fig. 1 is less than 50%. Thus, it is ensured that the

transmission gates

230 and 240 of the decision and hold circuit 120 are not turned on at the same time, so as to avoid power consumption and cause an incorrect duty ratio of the output clock CLKOUT.

Fig. 4 shows an electronic device 400 according to another embodiment of the invention. The electronic device 400 includes a phase-locked loop circuit 410 and a duty cycle corrector 420. The phase-locked loop circuit 410 may provide the input clock CLK0 and the input clock CLK180 to the duty cycle corrector 420. In this embodiment, the input clock CLK0 and the input clock CLK180 have the same frequency F (i.e., the same period T) and duty cycle. The phase difference between the input clock CLK0 and the input clock CLK180 is 180 degrees. The duty cycle corrector 420 includes a decision and hold circuit 430 and pulse swallowers (pulse swallows) 440 and 450. The pulse swallower 440 may provide the clock signal CLK _ SWA0 in accordance with the input clock CLK0, where the duty cycle of the clock signal CLK _ SWA0 is less than the duty cycle of the input clock CLK 0. In addition, the pulse swallower 450 may provide the clock signal CLK _ SWA180 according to the input clock CLK180, wherein a duty cycle of the clock signal CLK _ SWA180 is less than a duty cycle of the input clock CLK 180. In some embodiments, the duty cycle of the input clocks CLK0 and CLK180 is greater than 50%, and the duty cycle of the clock signals CLK _ SWA0 and CLK _ SWA180 is less than 50%. The decision and hold circuit 430 may provide an output clock CLKOUT having a 50% duty cycle for use by other circuits within the electronic device 100 based on the clock signals CLK _ SWA0 and CLK _ SWA 180. In some embodiments, the phase-locked loop circuit 410 and the duty cycle corrector 420 are provided on the same integrated circuit.

Fig. 5 is an exemplary circuit diagram showing the duty ratio corrector 420 of fig. 4. Fig. 6 is a signal waveform diagram showing the duty ratio corrector 420 of fig. 5. Referring to both fig. 5 and 6, the pulse swallower 440 includes an inverter string 442 formed of a plurality of inverters (nor gates) 442_1-442_ n and a logic unit 444. Inverters 442_1-442_ n in inverter string 442 are connected in series to provide a delayed clock CLK _ DLY0 according to an input clock CLK 0. The rising edge of the delayed clock CLK _ DLY0 is delayed by time D2 compared to the input clock CLK 0. In addition, the pulse swallower 450 includes an inverter string 452 formed of a plurality of inverters 452_1-452_ n and a logic unit 454. In the inverter string 452, inverters 452_1-452_ n are connected in series to provide a delayed clock CLK _ DLY180 according to an input clock CLK 180. The rising edge of the delayed clock CLK _ DLY180 is delayed by time D2 compared to the input clock CLK 180. In this embodiment, the number and circuit characteristics (e.g., size, driving capability, etc.) of the inverters 442_1-442_ n are the same as the inverters 452_1-452_ n. In addition, the number of inverters is determined according to practical applications. Logic units 444 AND 454 are AND gates (ANDs). The and gate 444 may generate a clock signal CLK _ SEA0 according to the input clock CLK0 and the delayed clock CLK _ DLY0 and provide the clock signal CLK _ SWA0 to the decision and hold circuit 430. When the input clock CLK0 or the delayed clock CLK _ DLY0 is at a low logic level, the clock signal CLK _ SWA0 is at a low logic level. When the input clock CLK0 and the delayed clock CLK _ DLY0 are both at a high logic level, the clock signal CLK _ SWA0 is at a high logic level. Thus, the pulse swallower 440 may provide the clock signal CLK _ SWA0 with a smaller duty cycle according to the input clock CLK0, i.e., the duty cycle of the clock signal CLK _ SWA0 is smaller than the duty cycle of the input clock CLK 0. Similarly, the AND gate 454 may generate the clock signal CLK _ SWA180 according to the input clock CLK180 and the delayed clock CLK _ DLY180 and provide the clock signal CLK _ SEA180 to the decision and hold circuit 430. When the input clock CLK180 or the delayed clock CLK _ DLY180 is at a low logic level, the clock signal CLK _ SWA180 is at a low logic level. When the input clock CLK180 and the delayed clock CLK _ DLY180 are at a high logic level at the same time, the clock signal CLK _ SWA180 is at a high logic level. Thus, the pulse swallower 450 may provide the clock signal CLK _ SWA180 with a smaller duty cycle according to the input clock CLK180, i.e., the duty cycle of the clock signal CLK _ SWA180 is smaller than the duty cycle of the input clock CLK 180. It is noted that the

logic units

444 and 454 are AND gates for illustrative purposes only and are not meant to limit the present invention.

As previously described, the decision and hold circuit 430 includes single-ended to

differential converters

510 and 520 and

transmission gates

530 and 540. The single-ended to differential converter 510 may convert the clock signal CLK _ SWA0 into differential clock signals CLK0X and CLK 0B. In addition, the single-ended to differential converter 520 may convert the clock signal CLK _ SWA180 into differential clock signals CLK180X and CLK 180B. The transmission gate 530 is coupled between the power VDD and the output terminal 550, and is controlled by the differential clock signals CLK0B and CLK 0X. When the transmission gate 530 is turned on, the output terminal 550 is coupled to the power supply VDD via the transmission gate 530, and the output clock CLKOUT at the output terminal 550 is maintained at the voltage value (i.e., the high logic level) of the power supply VDD. The transmission gate 540 is coupled between the ground GND and the output terminal 550, and is controlled by the differential clock signals CLK180B and CLK 180X. When the transmission gate 540 is turned on, the output terminal 550 is coupled to the ground GND through the transmission gate 540, and the output clock CLKOUT at the output terminal 550 maintains the voltage value (i.e., the low logic level) of the ground GND. It is noted that the duty cycle of the clock signals CLK _ SWA0 and CLK _ SWA180 is less than 50%, so that it is ensured that the

transmission gates

530 and 540 are not turned on simultaneously, thereby avoiding power consumption and causing incorrect duty cycle of the output clock CLKOUT.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention, and therefore, the scope of the invention should be determined by that of the appended claims.

Claims

1. A duty cycle corrector, comprising:

a first pulse swallower comprising a first logic unit, said first logic unit receiving a first input clock having a first duty cycle and said first input clock delayed to provide a first clock signal having a second duty cycle;

a second pulse swallower for providing a second clock signal having the second duty ratio based on a second input clock having the first duty ratio, wherein the first input clock and the second input clock are provided by a phase locked loop circuit, the phase difference between the first input clock and the second input clock is 180 degrees, and the second duty ratio is smaller than the first duty ratio; and

a decision and hold circuit for receiving the first and second input clocks directly from the phase-locked loop circuit when a first duty ratio of the first and second input clocks provided from the phase-locked loop circuit is less than 50%, and providing an output clock having a duty ratio of 50% based on the first and second input clocks, and receiving the first and second clock signals having the second duty ratio from the first and second pulse swallowers when the duty ratio of the first and second input clocks provided from the phase-locked loop circuit is greater than 50%, and providing an output clock having a duty ratio of 50% based on the first and second clock signals.

2. The duty cycle corrector of claim 1, wherein said first pulse swallower comprises:

a first delay unit including a plurality of inverters connected in series to provide the delayed first input clock according to the first input clock;

wherein said second pulse swallower comprises:

a second delay unit including a plurality of inverters connected in series to provide the delayed second input clock according to the second input clock; and

and a second logic unit for providing the second clock signal according to the second input clock and the delayed second input clock.

3. The duty ratio corrector of claim 2, wherein the number of the inverters of the first delay unit is the same as the number of the inverters of the second delay unit.

4. The duty cycle corrector of claim 2, wherein said first logic unit and said second logic unit each comprise an and gate.

5. The duty cycle corrector of claim 1, wherein said decision and hold circuit comprises:

a first single-ended to differential converter for converting the first clock signal into a first differential clock signal and a second differential clock signal;

a second single-ended to differential converter for converting the second clock signal into a third differential clock signal and a fourth differential clock signal;

a first transmission gate coupled between a power source and an output terminal, wherein the first transmission gate is controlled by the first differential clock signal and the second differential clock signal; and

a second transmission gate coupled between ground and the output terminal, wherein the second transmission gate is controlled by the third differential clock signal and the fourth differential clock signal,

wherein the decision and hold circuit provides the output clock via the output terminal,

wherein the first transmission gate and the second transmission gate are not turned on simultaneously.

6. The duty cycle corrector of claim 5 wherein said first transmission gate comprises:

a first P-type transistor coupled between the power supply and the output terminal, having a control terminal for receiving one of the first and second differential clock signals; and

a first N-type transistor coupled between the power supply and the output terminal and having a control terminal for receiving the other of the first and second differential clock signals,

wherein the second transmission gate comprises:

a second P-type transistor coupled between the ground terminal and the output terminal, and having a control terminal for receiving one of the third and fourth differential clock signals; and

a second N-type transistor coupled between the ground terminal and the output terminal and having a control terminal for receiving the other of the third and fourth differential clock signals.

7. A duty cycle corrector, comprising:

a decision and hold circuit for providing an output clock having a duty ratio of 50% according to a first clock signal and a second clock signal, wherein a phase difference between the first clock signal and the second clock signal is 180 degrees, the duty ratio of the first clock signal is the same as the duty ratio of the second clock signal,

wherein the decision and hold circuit comprises:

wherein the first transmission gate and the second transmission gate are not conducted at the same time,

wherein, when the first duty ratio of the first input clock and the second input clock with the same duty ratio provided by the phase-locked loop circuit is less than 50%, the first input clock and the second input clock are directly provided to the decision and hold circuit as the first clock signal and the second clock signal, so that the decision and hold circuit provides an output clock with 50% duty ratio according to the first input clock and the second input clock,

wherein, when the first duty ratio of the first input clock and the second input clock provided by the phase-locked loop circuit is greater than 50%, the duty ratio corrector further comprises:

a first pulse swallower, including a first logic unit, receiving a first input clock from a phase-locked loop circuit and the first input clock after delay, to provide the first clock signal to the decision and hold circuit, so that a duty ratio of the first clock signal is smaller than that of the first input clock;

and a second pulse swallower for supplying the second clock signal to the decision and hold circuit in accordance with a second input clock from the phase-locked loop circuit so that a duty ratio of the second clock signal is smaller than a duty ratio of the second input clock.

8. The duty cycle corrector of claim 7, wherein the phase difference between the first input clock and the second input clock is 180 degrees.

9. The duty cycle corrector of claim 7 wherein said first pulse swallower comprises:

wherein said second pulse swallower comprises:

10. The duty ratio corrector of claim 9, wherein the number of the inverters of the first delay unit is the same as the number of the inverters of the second delay unit.

11. The duty cycle corrector of claim 9, wherein said first logic unit and said second logic unit each comprise an and gate.

12. The duty cycle corrector of claim 7 wherein said first transmission gate comprises:

a first P-type transistor coupled between the power supply and the output terminal, and having a control terminal for receiving the first differential clock signal; and

a first N-type transistor coupled between the power supply and the output terminal and having a control terminal for receiving the second differential clock signal,

wherein the second transmission gate comprises:

a second P-type transistor coupled between the ground terminal and the output terminal, and having a control terminal for receiving the third differential clock signal; and

and a second N-type transistor coupled between the ground terminal and the output terminal and having a control terminal for receiving the fourth differential clock signal.