CN102983842A - Duty ratio adjusting circuit - Google Patents

Duty ratio adjusting circuit Download PDF

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CN102983842A
CN102983842A CN2012105071076A CN201210507107A CN102983842A CN 102983842 A CN102983842 A CN 102983842A CN 2012105071076 A CN2012105071076 A CN 2012105071076A CN 201210507107 A CN201210507107 A CN 201210507107A CN 102983842 A CN102983842 A CN 102983842A
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clock signal
transistor
capacitor
charge pump
duty ratio
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陈丹凤
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention provides a duty ratio adjusting circuit which is used for adjusting the duty ratio of a first clock signal to acquire a third clock signal. The duty ratio adjusting circuit comprises a pulse width adjusting unit, a shaping unit, an inverse phase unit and a control signal generating unit, wherein the pulse width adjusting unit inputs a second clock signal and outputs the third clock signal; the inverse phase unit inputs the third clock signal and outputs a fourth clock signal; the third clock signal and the fourth clock signal have opposite phase position; and the control signal generating unit inputs the third clock signal and the fourth clock signal and outputs a control signal. The duty ratio adjusting circuit is simple in structure and can stably output the clock signal with the expected duty ratio.

Description

Duty ratio adjusting circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a duty ratio adjusting circuit which is not influenced by manufacturing process, voltage and temperature parameters.
Background
With the continuous development of integrated circuit technology, the working speed of the chip is continuously increased, and the increase of the working speed means more rigorous timing precision, so that the requirement on the performance of the system clock is also continuously increased. The duty ratio of the clock is a relatively important performance index in clock performance. Duty Cycle generally refers to the ratio of the duration of a positive pulse to the pulse period in a train of ideal pulse periods (e.g., a square wave). Such as: a duty cycle of 50% means that the width of the high level clock period is equal to the width of the low level clock period. At present, a 50% duty cycle is advantageous for data transmission, and is one of the requirements for stable operation of the system. For example: for a double data Rate Synchronous Random Access Memory (DDR-SDRAM), data is transmitted twice in one clock cycle, that is, data is transmitted once on each of a rising edge and a falling edge of a clock, and therefore, it is important that a clock duty ratio reaches 50%.
In practical applications, the system Clock is generally generated by a Clock and Data Recovery (CDR), a Phase-Locked Loop (PLL) or a Delay-Locked Loop (DLL) due to the requirement of higher frequency and strict synchronization. Due to mismatch generated by circuit design and deviation of a process and a simulation model in a chip manufacturing process, a clock generated after frequency multiplication and synchronization cannot always ensure a 50% duty ratio. In addition, even if the duty ratio of the generated clock is strictly 50%, in the subsequent transmission process of the clock signal, the duty ratio may be out of order due to system and process deviations existing in the transmission link, and in the case of a high frequency, the out of order of the duty ratio may even make the clock signal not normally flip, thereby causing a serious timing error. Therefore, it is necessary to adjust the duty ratio of the input clock in addition to the duty ratio of the system clock generated by the PLL or DLL.
A duty cycle correction circuit (duty cycle circuit) or a duty cycle regulator (DDC) is used to adjust the duty cycle of the clock signal. The duty ratio adjusting circuit can be generally classified into a digital adjusting type or an analog adjusting type. The duty ratio adjusting circuit of the digital adjusting mode generally has higher loop stability and faster adjusting time, but the adjusting precision, the adjusting frequency range and the duty ratio range are limited, and the structure is complex. The duty ratio adjusting circuit of the analog adjusting mode has the characteristics of high precision, wide range and simple structure.
Fig. 1 is a conventional duty ratio adjusting circuit. The duty cycle adjusting circuit shown in fig. 1 is a feedback system, in which the Delay Unit (DU) includes a plurality of inverters connected in series. The charge pump CPA is a capacitor C5Providing a charge current and a discharge current, the charge pump CPB providing the charge current and the discharge current to the capacitor C6. The charging and discharging time of the capacitor C5 is CK20The charging and discharging time of the capacitor C6 is determined by a clock signal output from a Ring Oscillator (RO). The duty ratio adjusting circuit shown in fig. 1 changes the control voltage V5 by changing the voltage V5 at one end of the capacitor C510And further by controlling the voltage V10To adjust the input clock signal CK10So that the clock signal CK finally outputted via DU20Up to 50%.
The inventors found that the duty ratio adjusting circuit of fig. 1 is used for the input clock signal CK10Such as: a square wave or sine wave with a duty ratio less than 50%, or a square wave or sine wave with a duty ratio greater than 50%, and the like, and adjusting the output clock signal CK20The duty cycle of (c) is often less than 50%.
The inventors have studied to determine the output clock signal CK20The main reason why the duty ratio of (C) is less than 50% is that the reference voltage V6 inputted to the inverting input terminal of the amplifier shown in fig. 1 is unstable, and the reference voltage V6 depends on the voltage at one terminal of the capacitor C6 connected to the charge pump CPB. Generally, the charging current and the discharging current output by the charge pump CPB are equal, so if the charging time and the discharging time of the capacitor C6 are equal, the voltage at the end of the capacitor C6 will remain stable, i.e. the reference voltage V6 at the inverting input terminal of the input amplifier is stable. However, the time to charge and discharge capacitor C6 depends on RO which provides the clock signal for charge pump CPB. For RO, it is usually implemented by an inverter connected end to end, the inverter is composed of transistors, and both the performance of the transistors and the operating voltage of RO have an influence on the clock signal of the RO output.
The performance of a transistor depends on the process conditions under which the transistor is produced and the temperature at which the transistor operates, the process conditions varying the process corners of the transistor such as: TT (NFET-generic corner & PFET-generic corner), FF (Fast corner), SS (Slow slope corner), etc. vary. Where typical means that the transistor drive current is an average, Fast means that the transistor drive current is its maximum, and Slow means that the transistor drive current is its minimum (this current is the Ids current). Therefore, the clock signal output by the RO depends on the process conditions, the temperature, the operating voltage of the RO, and other factors to a great extent, and these all cause the duty ratio of the clock signal finally output by the RO to be less than 50%, which causes the charging time and the discharging time of the capacitor C6 by the charge pump CPB to be unequal, and further causes the reference voltage V6 input to the inverting input end of the amplifier not to have the dc potential corresponding to the clock signal with the duty ratio of 50%.
In summary, with the duty ratio adjusting circuit shown in fig. 1, the adjusted clock signal often does not reach a duty ratio of 50%, and the adjusting circuit is complex.
Therefore, it is one of the problems to be solved by the present invention to provide a circuit that has a simple structure and can stably output a clock signal with a desired duty ratio.
Disclosure of Invention
The invention provides a duty ratio adjusting circuit which is simple in structure and can stably output expected duty ratio.
In order to solve the above problem, the present invention provides a duty ratio adjusting circuit for adjusting a duty ratio of a first clock signal to obtain a third clock signal, including: the pulse width adjusting unit, the shaping unit, the inverting unit and the control signal generating unit; the pulse width adjusting unit inputs the first clock signal and a control signal and outputs a second clock signal; the shaping unit inputs the second clock signal and outputs the third clock signal; the inverting unit inputs the third clock signal and outputs a fourth clock signal; the third clock signal is in opposite phase to the fourth clock signal; the control signal generating unit inputs the third clock signal and the fourth clock signal and outputs the control signal.
Optionally, the pulse width adjusting unit includes: a first transistor and a second transistor; the gate of the first transistor is input with the control signal, and the gate of the second transistor is input with the first clock signal; the drain electrode of the first transistor is connected with the drain electrode of the second transistor to output the second clock signal; the source electrode of the first transistor is connected with a first voltage source, and the source electrode of the second transistor is connected with a second voltage source.
Optionally, the shaping unit includes a plurality of inverters connected in series.
Optionally, the control signal generating unit includes: the circuit comprises a first charge pump, a second charge pump, an amplifier, a first capacitor, a second capacitor and a third capacitor; the input end of the first charge pump inputs the third clock signal, and the output end of the first charge pump is connected with the first end of the first capacitor; the input end of the second charge pump inputs the fourth clock signal, and the output end of the second charge pump is connected with the first end of the second capacitor; the non-inverting input end of the amplifier is connected with the first end of the first capacitor, the inverting input end of the amplifier is connected with the first end of the second capacitor, and the output end of the amplifier is connected with the first end of the third capacitor to output the control signal; and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are respectively connected with a grounding voltage source.
Optionally, the shaping unit includes an odd number of inverters connected in series, and the equidirectional output end of the amplifier is connected to the first end of the third capacitor.
Optionally, the shaping unit includes an even number of inverters connected in series, and an inverted output terminal of the amplifier is connected to the first terminal of the third capacitor.
Optionally, the first charge pump includes: a first current source, a second current source, a third transistor, and a fourth transistor; the first end of the first current source is connected with a power supply voltage source, and the second end of the first current source is connected with the source stage of the third transistor; the first end of the second current source is connected with the source stage of the fourth transistor, and the second end of the second current source is connected with a grounding voltage source; the gate of the third transistor is connected to the gate of the fourth transistor, the third clock signal is input, and the drain of the third transistor and the drain of the fourth transistor are connected to the first end of the first capacitor.
Optionally, the second charge pump includes: a third current source, a fourth current source, a fifth transistor, and a sixth transistor; the first end of the third current source is connected with a power supply voltage source, and the second end of the third current source is connected with the source stage of the fifth transistor; a first end of the fourth current source is connected with a source stage of the sixth transistor, and a second end of the fourth current source is connected with a grounding voltage source; and the grid electrode of the fifth transistor is connected with the grid electrode of the sixth transistor to input the fourth clock signal, and the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are connected with the first end of the second capacitor.
Optionally, the inverting unit is an odd number of inverters connected in series.
Optionally, the inverting unit is an inverter.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the input signal of the control signal generating unit is provided by the third clock signal output by the shaping unit and the fourth clock signal output by the inverting unit, and the fourth clock signal is provided by the inverting unit formed by one inverter, instead of the self-oscillation signal generated by the ring oscillator formed by a plurality of inverters connected end to end. And the input signal of the inverting unit is provided by the third clock signal output by the shaping unit, whereby the fourth clock signal output by the inverting unit is in opposite phase to the third clock signal output by said shaping unit. The high and low levels of the third clock signal respectively discharge or charge the first capacitor by controlling the first charge pump, and the high and low levels of the fourth clock signal respectively discharge or charge the second capacitor by controlling the second charge pump, so that the first voltage on the first capacitor and the second voltage on the second capacitor respectively reflect the duty ratios of the third clock signal and the fourth clock signal. As the positive input end voltage and the negative input end voltage of the amplifier are finally equal through the adjustment of the negative feedback loop, the duty ratios of the third clock signal and the fourth clock signal are equal after the negative feedback loop is stabilized. Because the third clock signal and the fourth clock signal are in an inverse phase relation, after the loop is stabilized, the duty ratios of the two clock signals can only be 50%, so that the accurate duty ratio adjustment of 50% is realized. Since the self-calibration method is adopted, the reference voltage and the reference clock serving as the amplifier are derived from the self-calibration method, the influences of the process, the temperature and the voltage on the circuit can be counteracted, and the calibration of outputting the 50% duty cycle clock is realized.
The duty ratio adjusting circuit is composed of a pulse width adjusting unit, a shaping unit, an inverting unit and a control signal generating unit, and the inverting unit is only composed of one inverter, so that the duty ratio adjusting circuit is simpler in structure and lower in cost.
Drawings
Fig. 1 is a circuit diagram of a conventional duty ratio adjustment circuit;
FIG. 2 is a block schematic diagram of a duty cycle adjustment circuit of an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a duty cycle adjustment circuit according to a first embodiment of the present invention;
fig. 4 is a circuit schematic of a first charge pump according to a first embodiment of the present invention;
fig. 5 is a circuit schematic of a second charge pump according to a first embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a duty ratio adjustment circuit according to a second embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
Fig. 2 is a block schematic diagram of a duty cycle adjustment circuit according to an embodiment of the present invention.
As shown in fig. 2, the duty ratio adjustment circuit includes: a pulse width adjusting unit 1, a shaping unit 2, an inverting unit 4 and a control signal generating unit 3.
Wherein, the pulse width adjusting unit 1 inputs a first clock signal CKinAnd a control signal VctrOutputs a second clock signal CK2。
Wherein the shaping unit 2 inputs the second clock signal CK2Outputs a third clock signal CKout。
Wherein, the inverting unit 4 inputs the third clock signal CKoutAnd outputs a fourth clock signal CKref。
The third clock signal CKoutAnd the fourth clock signal CKrefAre opposite in phase.
Wherein the control signal generating unit 3 inputs the third clock signal CKoutAnd a fourth clock signal CKrefOutputs the control signal Vctr。
In this embodiment, the duty ratio adjusting circuit is a feedback system, and the first clock signal CKinCan be any duty ratioThe second clock signal CK outputted from the pulse width adjusting unit 12And a first clock signal CKinIs inverted and has a duty ratio with respect to the first clock signal CKinIs properly adjusted; the shaping unit 2 can not only convert the second clock signal CK2For a second clock signal CK in addition to the delay2Is performed, and the second clock signal CK is realized by setting the determined flip threshold voltage to ' 0 ' and ' 12So that the third clock signal CK output by the shaping unit 2outThe rising and falling edges are steeper.
Control signal generating unit 3 third clock signal CK output by shaping unit 2outAnd a fourth clock signal CK output from the inverting unit 4refProviding and the fourth clock signal CKrefThe inversion unit 4, which is formed by one inverter 41, is provided instead of the self-oscillation signal generated by the ring oscillator RO formed by a plurality of inverters connected end to end. And the fourth clock signal CK output from the inverting unit 4refAnd a third clock signal CK output by the shaping unit 2outThe inverse phase, control signal generating unit 3 is based on the third clock signal CKoutAnd a fourth clock signal CKrefOutput control signal Vctr。
The technical solution of the present invention will be described in detail below with reference to the first and second examples.
Example one
Fig. 3 is a circuit diagram of a duty ratio adjusting circuit according to a first embodiment of the present invention.
As shown in fig. 3, the duty ratio adjustment circuit includes: a pulse width adjusting unit 1, a shaping unit 2, a control signal generating unit 3 and an inverting unit 4.
Wherein the pulse width adjusting unit 1 includes: a first transistor 11 and a second transistor 12;
a gate of the first transistor 11 is input with a control signal VctrSaidThe gate of the second transistor 12 is inputted with the first clock signal CKin；
The drain of the first transistor 11 is connected to the drain of the second transistor 12 to output a second clock signal CK2；
The source of the first transistor 11 is connected to a first voltage source, and the source of the second transistor 12 is connected to a second voltage source.
Wherein the shaping unit 2 comprises: an odd number of the inverters 21 connected in series, wherein the second clock signal CK is input to an input terminal of the odd number of the inverters 21 connected in series2And the output end outputs a third clock signal CKout。
Wherein the inverting unit 4 is an inverter 41, which inputs the third clock signal CKoutAnd outputs a fourth clock signal CKref。
The third clock signal CKoutAnd a fourth clock signal CKrefAre opposite in phase.
Wherein the control signal generating unit 3 comprises a first charge pump CP1, a second charge pump CP2, an amplifier 31, a first capacitor C1, a second capacitor C2 and a third capacitor C3;
the third clock signal CK is input to an input terminal of the first charge pump CP1outThe output end of the first capacitor C1 is connected with the first end of the first capacitor C1;
the fourth clock signal CK is input to an input terminal of the second charge pump CP2refThe output end of the second capacitor C2 is connected with the first end of the second capacitor C2;
the non-inverting input terminal of the amplifier 31 is connected to the first terminal of the first capacitor C1, the inverting input terminal is connected to the first terminal of the second capacitor C2, the non-inverting output terminal is connected to the first terminal of the third capacitor C3, and the amplifier outputs a control signal Vctr；
The second end of the first capacitor C1, the second end of the second capacitor C2 and the second end of the third capacitor C3 are respectively connected with a ground voltage source.
In this embodiment, the first transistor 11 may be a PMOS transistor, and a source thereof is connected to a first voltage source, where the first voltage source is a power supply voltage source; the second transistor 12 may be an NMOS transistor, and the source thereof is connected to a second voltage source, which is a ground voltage source.
Fig. 4 is a schematic circuit diagram of a first charge pump according to a first embodiment of the present invention. The first charge pump CP1 provides a charging current or a discharging current for the capacitor C1.
As shown in fig. 4, the first charge pump CP1 includes: a first current source 101, a second current source 102, a third transistor 13, and a fourth transistor 14; in conjunction with the figures 3 and 4,
a first end of the first current source 101 is connected to a power supply voltage source, and a second end is connected to a source stage of the three transistors 13;
a first terminal of the second current source 102 is connected to the source of the fourth transistor 14, and a second terminal thereof is connected to a ground voltage source;
the gate of the third transistor 13 is connected to the gate of the fourth transistor 14, and the third clock signal CK is input theretooutThe drain of the third transistor 13 and the drain of the fourth transistor 14 are connected to a first end of the first capacitor C1.
In this embodiment, the first current source 101 provides a charging current I to the first capacitor C1pThe second current source 102 provides a discharge current I to the first capacitor C1nA duty cycle of the third clock signal is related to a ratio of a charging current of the first current source to a discharging current of the second current source. Specifically, the high level of the third clock signal lasts for a time period longer than the low level of the third clock signal and is equal to the charging current and the discharging current. For example, if the first clock signal CK is wantedinIs adjusted to 50%, the charging current I is then adjustedpAnd said putElectric current InAre equal. If want to use the first clock signal CKinIs adjusted to 60%, then the charging current IpFor said discharge current In1.5 times of the total weight of the powder. The third transistor 13 may be a PMOS transistor, and the fourth transistor 14 may be an NMOS transistor.
Fig. 5 is a schematic circuit diagram of a second charge pump according to a first embodiment of the invention. The second charge pump CP2 provides a charging current or a discharging current for the capacitor C2.
As shown in fig. 5, the second charge pump CP2 includes: a third current source 103, a fourth current source 104, a fifth transistor 15, and a sixth transistor 16; in connection with the figures 3 and 5,
a first end of the third current source 103 is connected to a power supply voltage source, and a second end is connected to a source stage of the five-transistor 15;
a first terminal of the fourth current source 104 is connected to the source of the sixth transistor 16, and a second terminal thereof is connected to a ground voltage source;
the gate of the fifth transistor 15 is connected to the gate of the sixth transistor 16, and the fourth clock signal CK is input theretorefThe drain of the fifth transistor 15 and the drain of the sixth transistor 16 are connected to the first end of the second capacitor C2.
In this embodiment, the third current source 103 provides a charging current I for the second capacitor C2pThe fourth current source 104 provides a discharge current I to the second capacitor C2nTo ensure the voltage V input to the inverting input terminal of the amplifier 31refStabilized, charging current I provided by the third current source 103pAnd the discharge current I provided by the fourth current source 104nAre equal. The fifth transistor 15 may be a PMOS transistor, and the sixth transistor 16 may be an NMOS transistor.
It should be noted that, in this embodiment, the shaping unit 2 is implemented by a plurality of inverters connected in series, and in other embodiments, the shaping unit may also be implemented by a nor gate or a nand gate.
The first clock signal CK is obtained by using the first transistor 11 as a PMOS transistor, the second transistor 12 as an NMOS transistor, the third transistor 13 as a PMOS transistor, the fourth transistor 14 as an NMOS transistor, the fifth transistor 15 as a PMOS transistor, and the sixth transistor 16 as an NMOS transistorinThe duty ratio of (1) is adjusted to 50% for example, and the operation process of the duty ratio adjusting circuit of the present embodiment is described accordingly.
Please refer to fig. 3 to 5, if the first clock signal CK is inputtedinThe clock signal with a duty ratio less than 50%, the output of the drains of the PMOS transistor and the NMOS transistor of the pulse width adjusting unit 1 and the first clock signal CKinInverted second clock signal CK2Second clock signal CK2Delayed by odd inverters 21, and output the first clock signal CKinThird clock signal CK of same phaseout。
Due to the first clock signal CKinIs less than 50%, the shaping unit 2 comprises an odd number of inverters 21, so that the third clock signal CKoutIs also less than 50%, i.e. the time taken for the low level is greater than the time taken for the high level. The third clock signal CK is input to an input terminal of the first charge pump CP1outFor the first charge pump CP1, the low level turns on the PMOS transistor in the first charge pump CP1 to charge the first capacitor C1; the high level turns on the NMOS transistor in the first charge pump CP1, discharging the first capacitor C1. Since the PMOS transistor of the first charge pump CP1 is turned on for a longer time than the NMOS transistor, the first charge pump CP1 charges the first capacitor C1 for a longer time than the first capacitor C1 is discharged. The charging current I provided by the first current source 101 in the first charge pump CP1pAnd a discharge current I provided by a second current source 102nEqual, voltage V at the first end of the first capacitor C1cAnd (4) rising.
And due to the third clock signal CKoutIs less than 50%, and the fourth clock signal CKrefAnd a third clock signal CKoutIs inverted, so that the fourth clock signal CKrefIs greater than 50%, i.e. the time occupied by high levels is greater than the time occupied by low levels. The fourth clock signal CK is input to the second charge pump CP2refFor the second charge pump CP2, the low level turns on the PMOS transistor in the second charge pump CP2 to charge the second capacitor C2; the high level turns on the NMOS transistor in the second charge pump CP2, discharging the second capacitor C2. Since the NMOS transistor of the second charge pump CP1 is turned on for a longer time than the PMOS transistor, the second charge pump CP2 charges the second capacitor C2 for a shorter time than the second capacitor C1. The charging current I provided by the third current source 103 in the second charge pump CP2pAnd a discharge current I provided by a fourth current source 104nEqual, voltage V at the first end of the second capacitor C2refAnd decreases.
The non-inverting input of the amplifier 31 is connected to the first terminal of the first capacitor C1, and the inverting input is connected to the first terminal of the second capacitor C2. The amplifier 31 has a non-inverting output terminal that changes in phase with the input and an inverting output terminal that changes in phase with the input. Specifically, when the voltage at the non-inverting input terminal rises, the voltage at the non-inverting output terminal also rises; when the voltage at the non-inverting input terminal decreases, the voltage at the non-inverting output terminal also decreases.
The non-inverting input terminal of the amplifier 31 is connected to the first terminal of the first capacitor C1 when the first clock signal CK is assertedinIs less than 50%, the voltage V at the first end of the first capacitor C1cThe voltage V of the first end of the second capacitor C2 is increasedrefDecrease, i.e. VcGreater than VrefSo that the control signal V output from the in-phase output terminalctrAnd (4) rising.
Control signal VctrInput to the PMOS transistor of the pulse width adjusting unit 1 to control it, VctrWhen rising, the current flowing through the PMOS tube becomes small, the charging to the point a becomes slow, namely the second clock signal CK2The rising edge of (c) becomes slow. The third clock signal CK output after being shaped by the inverter in the shaping unit 2outRelative to the first clock signalNumber CKinWill become larger, i.e. the adjusted first clock signal CKin(third clock signal CKout) The pulse width of the rising edge of (c) is widened relative to that before the adjustment.
Following the third clock signal CKoutThe duty ratio of the first charge pump CP1 is gradually increased, the conduction time of the PMOS transistor and the conduction time of the NMOS transistor in the first charge pump CP1 are gradually close, the charging time and the discharging time of the first capacitor C1 are also gradually close, and V iscDecrease when Vc=VrefVoltage V output by non-inverting output terminal of time amplifierctrStabilized at a specific value, the feedback system is stabilized, and the third clock signal CKoutHas a duty ratio of 50%, that is, the first clock signal CKin(input clock signal) is adjusted by the duty ratio adjusting circuit, and then the output clock signal (third clock signal CK)out) The duty cycle of (2) reaches 50%.
If the first clock signal CKin(the input clock signal) is a clock signal with a duty ratio of more than 50%, the third clock signal CKoutIs also greater than 50%, i.e., the time occupied by the low level is less than the time occupied by the high level. Therefore, the time for the first charge pump CP1 to charge the first capacitor C1 is less than the time for the first capacitor C1 to discharge. Due to the charging current I provided by the first current source 101 in the first charge pump CP1pAnd a discharge current I provided by a second current source 102nEqual, voltage V at the first end of the first capacitor C1cAnd decreases.
And due to the third clock signal CKoutIs greater than 50%, and the fourth clock signal CKrefAnd a third clock signal CKoutIs inverted, so that the fourth clock signal CKrefIs less than 50%, i.e. the time occupied by the low level is greater than the time occupied by the high level. The fourth clock signal CK is input to the second charge pump CP2refFor the second charge pump CP2, the low level turns on the PMOS transistor in the second charge pump CP2 to charge the second capacitor C2; the high level makes the NMOS transistor in the second charge pump CP2Conducting and discharging the second capacitor C2. Since the NMOS transistor of the second charge pump CP1 is turned on for a longer time than the PMOS transistor, the second charge pump CP2 charges the second capacitor C2 for a longer time than the second capacitor C1 is discharged. The charging current I provided by the third current source 103 in the second charge pump CP2pAnd a discharge current I provided by a fourth current source 104nEqual, voltage V at the first end of the second capacitor C2refAnd (4) rising.
Since the non-inverting input terminal of the amplifier 31 is connected to the first terminal of the first capacitor C1 and the inverting input terminal is connected to the first terminal of the second capacitor C2, when the first clock signal CK is assertedinIs greater than 50%, the voltage V at the first end of the first capacitor C1cDecrease the voltage V at the first terminal of the second capacitor C2refIs raised, i.e. VcLess than VrefSo that the control signal V output from the in-phase output terminalctrAnd decreases.
VctrWhen the voltage is reduced, the current flowing through the PMOS tube is increased, so that the discharge of the NMOS tube to the point a is slowed, namely the second clock signal CK2The falling edge of (2) becomes gentle. The third clock signal CK output after being shaped by the inverter in the shaping unit 2outRelative to the first clock signal CKinBecomes smaller.
Following the third clock signal CKoutThe duty ratio of (b) is gradually reduced, the time for charging and discharging the first capacitor C1 by the first charge pump CP1 is also gradually close, and V iscIs raised when Vc=VrefVoltage V output by non-inverting output terminal of time amplifierctrStabilized at a specific value, the feedback system is stabilized, and the third clock signal CKoutHas a duty ratio of 50%, that is, the first clock signal CKinThe duty ratio of the power supply reaches 50% after being adjusted by the duty ratio adjusting circuit.
It should be noted that, in the present embodiment, the duty ratio of the input clock signal is adjusted to 50% as an example, but the duty ratio adjusting circuit in the present embodiment is not limited to adjusting the duty ratio of the input clock signal to 50%, and the duty ratio of the input clock signal can be adjusted to a desired value by controlling the magnitudes of the charging current and the discharging current in the first charge pump CP 1. Therefore, the adjustment of the duty ratio of the input clock signal to 50% should not be taken as a limitation to the technical solution of the present invention.
Example two
In this embodiment, the duty ratio adjusting circuit is similar to that in the first embodiment, except that the shaping unit in this embodiment includes an even number of inverters, and the connection manner of the amplifiers in the control signal generating unit is different from that in the first embodiment.
Fig. 6 is a schematic circuit diagram of a duty ratio adjustment circuit according to a second embodiment of the present invention.
As shown in fig. 6, the duty ratio adjustment circuit includes: a pulse width adjusting unit 1, a shaping unit 2 ', a control signal generating circuit 3' and an inverting unit 4.
The pulse width adjusting unit 1 and the inverting unit 4 are the same as or similar to those in the first embodiment, and are not described herein again. The shaping unit 2 'includes an even number of inverters 21, and the structures of the first charge pump CP1 and the second charge pump CP2 included in the control signal generating unit 3' are similar to those of the first embodiment, and are not described herein again. The amplifier 31 has its non-inverting input still connected to the first terminal of the first capacitor C1, its inverting input still connected to the first terminal of the second capacitor C2, and its inverting output connected to the first terminal of the third capacitor C3.
Hereinafter, the first clock signal CK is still provided by using the first transistor 11 as a PMOS transistor, the second transistor 12 as an NMOS transistor, the third transistor 13 as a PMOS transistor, the fourth transistor 14 as an NMOS transistor, the fifth transistor 15 as a PMOS transistor, and the sixth transistor 16 as an NMOS transistorinThe duty ratio of (1) is adjusted to 50% for example, and the operation process of the duty ratio adjusting circuit of the present embodiment is described accordingly.
Please refer to fig. 4 to 6, if the first clock signal CKin(the input clock signal) is a clock signal having a duty cycle of less than 50%,the output of the drains of the PMOS transistor and the NMOS transistor of the pulse width adjusting unit 1 and the first clock signal CKinInverted second clock signal CK2Second clock signal CK2Delayed by an even number of inverters 21, and output the delayed signal as a first clock signal CKinInverted third clock signal CKout。
Due to the first clock signal CKinIs less than 50%, so the third clock signal CKoutIs greater than 50% due to the third clock signal CKoutAfter passing through the inverter 41 of the inverting unit 4, the fourth clock signal CK opposite to the third clock signal is outputrefSo that four clock signal CKrefIs less than 50%. Therefore, the time for the first charge pump CP1 to charge the first capacitor C1 is less than the time for the first capacitor C1 to discharge. Due to the charging current I provided by the first current source 101 in the first charge pump CP1pAnd a discharge current I provided by a second current source 102nEqual, voltage V at the first end of the first capacitor C1cAnd decreases. Similarly, the charging current I provided by the third current source 103 in the second charge pump CP2pAnd a discharge current I provided by a fourth current source 104nThe voltage V at the first end of the second capacitor C2 is equalizedrefAnd (4) rising.
Since the non-inverting input terminal of the amplifier 31 is connected to the first terminal of the first capacitor C1, when the first clock signal CKinIs less than 50%, the voltage V at the first end of the first capacitor C1cReducing the voltage V at the first terminal of the second power supply C2refIs raised, i.e. VcLess than VrefSo that the control signal V output from the inverting output terminal of the amplifier 31ctrAnd (4) rising.
Control signal VctrInput to the PMOS transistor of the pulse width adjusting unit 1 to control it, VctrWhen rising, the current flowing through the PMOS tube becomes small, the charging to the point a becomes slow, namely the second clock signal CK2The rising edge of (c) becomes slow. The third clock signal CK output after being shaped by the inverter in the shaping unit 2outRelative to the first clock signalCKinWill become larger, i.e. the adjusted first clock signal CKin(third clock signal CKout) The rising edge has a wider pulse width than before the adjustment.
Following the third clock signal CKoutThe duty ratio of the first charge pump CP1 is gradually reduced, the conduction time of the PMOS transistor and the conduction time of the NMOS transistor in the first charge pump CP1 are closer, the charging time and the discharging time of the first capacitor C1 are also closer, and V is smallercIs raised when Vc=VrefVoltage V output from inverting output terminal of time amplifierctrStabilized at a specific value, the feedback system is stabilized, and the third clock signal CKoutThe duty ratio of the first clock signal CK reaches 50%, namely the first clock signal CKin(input clock signal) is adjusted by the duty ratio adjusting circuit, and then the output clock signal (third clock signal CK)out) The duty cycle of (2) reaches 50%.
If the first clock signal CKin(the input clock signal) is a clock signal with a duty ratio of more than 50%, the third clock signal CKoutIs less than 50%, i.e. the time occupied by the low level is greater than the time occupied by the high level. Therefore, the first charge pump CP1 charges the first capacitor C1 for a time longer than the time for discharging the first capacitor C1. Due to the charging current I provided by the first current source 101 in the first charge pump CP1pAnd a discharge current I provided by a second current source 102nEqual, voltage V at the first end of the first capacitor C1cAnd (4) rising.
And due to the first clock signal CKinIs greater than 50%, then the third clock signal CKoutThe duty ratio is less than 50% after passing through a shaping unit 2' consisting of a pulse width adjusting unit 1 and an even number of inverters 21; due to the third clock signal CKoutConversely, therefore, the fourth clock signal CKrefThe second duty ratio is also larger than 50%, namely the time occupied by the high level is larger than the time occupied by the low level. Therefore, the second charge pump CP2 charges the second capacitor C1 for a shorter time than the first capacitor C1, so the second capacitor CVoltage V of first terminal of capacitor C2refAnd decreases.
Since the non-inverting input terminal of the amplifier 31 is connected to the first terminal of the first capacitor C1 and the inverting input terminal is connected to the first terminal of the second capacitor C2, when the first clock signal CK is assertedinIs greater than 50%, the voltage V at the first end of the first capacitor C1cRaising the voltage V at the first terminal of the second power supply C2refUp and down, i.e. VcGreater than VrefSo that the control signal V output from the inverting output terminal of the amplifier 31ctrIt is reduced accordingly.
VctrWhen the voltage is reduced, the current flowing through the PMOS tube is increased, so that the discharge of the NMOS tube to the point a is slowed, namely the second clock signal CK2The falling edge of (2) becomes gentle. The third clock signal CK output after being shaped by the inverter in the shaping unit 2outRelative to the first clock signal CKinBecomes smaller.
Following the third clock signal CKoutThe duty ratio of (b) is gradually increased, the time for the first charge pump CP1 to charge and discharge the first capacitor C1 is also gradually close, and V iscDecrease when Vc=VrefVoltage V output from inverting output terminal of time amplifierctrStabilized at a specific value, the feedback system is stabilized, and the third clock signal CKoutHas a duty ratio of 50%, that is, the first clock signal CKinThe duty ratio of the power supply reaches 50% after being adjusted by the duty ratio adjusting circuit.
In summary, the technical scheme of the invention has at least the following beneficial effects:
third clock signal CKoutRespectively, the first capacitor C1 is discharged or charged by controlling the first charge pump CP1, and the fourth clock signal CKrefRespectively, by controlling the second charge pump CP2 to discharge or charge the second capacitor C2, the first voltage V across the first capacitor C1cAnd a second voltage V across a second capacitor C2refRespectively reflect the third clock signal CKoutAnd a fourth clock signal CKrefThe duty cycle of (c). Since the voltage at the non-inverting input terminal of the amplifier 31 is finally made equal to the voltage at the inverting input terminal by the negative feedback loop adjustment, the third clock signal CK is stabilized by the negative feedback loopoutAnd a fourth clock signal CKrefAre equal. Due to the third clock signal CKoutAnd a fourth clock signal CKrefThe duty ratio of the two clock signals can only be 50% after the loop is stabilized, so that the accurate duty ratio adjustment of 50% is realized. Since the self-calibration method is used as the reference Voltage of the amplifier and the reference clock of the inverter of the inverting unit is derived from the circuit, not from a separate clock source, the influence of the Process, the Temperature and the Voltage on the circuit can be counteracted, namely, the PVT (Process Voltage Temperature) variation is overcome, and the calibration of the clock outputting 50% duty ratio is realized.
The duty ratio adjusting circuit is composed of a pulse width adjusting unit, a shaping unit, an inverting unit and a control signal generating unit, and the inverting unit is only composed of one inverter, so that the duty ratio adjusting circuit is simpler in structure and lower in cost.
It should be noted that the inverting unit in the above embodiment only uses one inverter, and the purpose is to make the inverting unit output the fourth clock signal with the opposite phase to the third clock signal output by the shaping unit, so it can be inferred that the inverting unit can be formed by using odd number of serial inverters such as three, five, seven, etc.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims (10)

1. A duty cycle adjustment circuit for adjusting a duty cycle of a first clock signal to obtain a third clock signal, comprising: the pulse width adjusting unit, the shaping unit, the inverting unit and the control signal generating unit; wherein,
the pulse width adjusting unit inputs the first clock signal and the control signal and outputs a second clock signal;
the shaping unit inputs the second clock signal and outputs the third clock signal;
the inverting unit inputs the third clock signal and outputs a fourth clock signal;
the third clock signal is in opposite phase to the fourth clock signal;
the control signal generating unit inputs the third clock signal and the fourth clock signal and outputs the control signal.
2. The duty cycle adjustment circuit of claim 1, wherein the pulse width adjustment unit comprises: a first transistor and a second transistor;
the gate of the first transistor is input with the control signal, and the gate of the second transistor is input with the first clock signal;
the drain electrode of the first transistor is connected with the drain electrode of the second transistor to output the second clock signal;
the source electrode of the first transistor is connected with a first voltage source, and the source electrode of the second transistor is connected with a second voltage source.
3. The duty cycle adjustment circuit of claim 1, wherein the shaping unit comprises a plurality of inverters connected in series.
4. The duty cycle adjustment circuit of claim 1, wherein the control signal generation unit comprises a first charge pump, a second charge pump, an amplifier, a first capacitor, a second capacitor, and a third capacitor;
the input end of the first charge pump inputs the third clock signal, and the output end of the first charge pump is connected with the first end of the first capacitor;
the input end of the second charge pump inputs the fourth clock signal, and the output end of the second charge pump is connected with the first end of the second capacitor;
the non-inverting input end of the amplifier is connected with the first end of the first capacitor, the inverting input end of the amplifier is connected with the first end of the second capacitor, and the output end of the amplifier is connected with the first end of the third capacitor to output the control signal;
and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are respectively connected with a grounding voltage source.
5. The duty cycle adjustment circuit of claim 4, wherein the shaping unit comprises an odd number of inverters connected in series, and wherein the unidirectional output terminal of the amplifier is connected to the first terminal of the third capacitor.
6. The duty cycle adjustment circuit of claim 4, wherein the shaping unit comprises an even number of inverters connected in series, and wherein the inverted output terminal of the amplifier is connected to the first terminal of the third capacitor.
7. The duty cycle adjustment circuit of claim 4, wherein the first charge pump comprises: a first current source, a second current source, a third transistor, and a fourth transistor;
the first end of the first current source is connected with a power supply voltage source, and the second end of the first current source is connected with the source stage of the third transistor;
the first end of the second current source is connected with the source stage of the fourth transistor, and the second end of the second current source is connected with a grounding voltage source;
the gate of the third transistor is connected to the gate of the fourth transistor, the third clock signal is input, and the drain of the third transistor and the drain of the fourth transistor are connected to the first end of the first capacitor.
8. The duty cycle adjustment circuit of claim 4, wherein the second charge pump comprises: a third current source, a fourth current source, a fifth transistor, and a sixth transistor;
the first end of the third current source is connected with a power supply voltage source, and the second end of the third current source is connected with the source stage of the fifth transistor;
a first end of the fourth current source is connected with a source stage of the sixth transistor, and a second end of the fourth current source is connected with a grounding voltage source;
and the grid electrode of the fifth transistor is connected with the grid electrode of the sixth transistor to input the fourth clock signal, and the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are connected with the first end of the second capacitor.
9. The duty cycle adjustment circuit of claim 1, wherein the inverting unit is an inverter.
10. The duty cycle adjustment circuit of claim 1, wherein the inverting unit is an odd number of inverters connected in series.
CN2012105071076A 2012-11-30 2012-11-30 Duty ratio adjusting circuit Pending CN102983842A (en)

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CN114167936A (en) * 2021-12-03 2022-03-11 中国科学院半导体研究所 CMOS charge pump pumping device with wide working voltage range
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CN104734494A (en) * 2013-12-23 2015-06-24 恩智浦有限公司 Method and system for controlling a charge pump
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CN108242922A (en) * 2016-12-23 2018-07-03 颖飞公司 Compact duty cycle correction device and communication system
CN108242922B (en) * 2016-12-23 2021-03-02 颖飞公司 Compact duty ratio correction device and communication system
CN107346964B (en) * 2017-06-09 2020-06-30 中国电子科技集团公司第四十一研究所 High-speed pulse signal pulse width precise control circuit with self-calibration function and control method
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CN108039876A (en) * 2017-12-21 2018-05-15 上海华力微电子有限公司 A kind of tension and relaxation type oscillating circuit
CN109962694A (en) * 2017-12-25 2019-07-02 北京兆易创新科技股份有限公司 A kind of dutyfactor adjustment circuit
CN109962694B (en) * 2017-12-25 2023-05-02 兆易创新科技集团股份有限公司 Duty cycle adjusting circuit
CN108869718A (en) * 2018-06-15 2018-11-23 南京奥吉智能汽车技术研究院有限公司 The self-learning method of lift knob selector knob lifting speed
CN110635789A (en) * 2018-06-25 2019-12-31 瑞昱半导体股份有限公司 Clock adjusting circuit and clock adjusting method
CN111192609A (en) * 2018-11-15 2020-05-22 长鑫存储技术有限公司 Clock duty ratio calibration circuit and calibration method
CN113162586A (en) * 2021-04-16 2021-07-23 南京大学 Clock duty ratio trimming method and system
CN113162586B (en) * 2021-04-16 2024-02-13 南京大学 Clock duty cycle trimming method and system
WO2023044762A1 (en) * 2021-09-24 2023-03-30 深圳市傲科光电子有限公司 Duty cycle adjustment circuit, integrated circuit, and electronic apparatus
CN114167936A (en) * 2021-12-03 2022-03-11 中国科学院半导体研究所 CMOS charge pump pumping device with wide working voltage range

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