CN202103633U - Analog-digital mixed clock duty cycle calibration circuit - Google Patents
Analog-digital mixed clock duty cycle calibration circuit Download PDFInfo
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Abstract
The utility model discloses an analog-digital mixed clock duty cycle calibration circuit, which is characterized by comprising an impulse generator (1), a half cycle delay line (2), an RS trigger (3), a single-ended to differential switching circuit (4), an analog-digital mixed charge pump (5) and an error amplifier (6), wherein, the input end of the impulse generator (1) is connected to a to-be-calibrated original input clock signal (CKI), and the output end signal of the impulse generator (1) is a buffered input clock impulse signal (CKB) which is further connected with the clock input end of the half cycle delay line (2) and a set input end (S) of the RS trigger (3). The analog-digital mixed clock duty cycle calibration circuit solves the problem of discrete calibration of a traditional digital clock duty cycle calibration circuit, realizes the continuous adjustment of the clock duty cycle, and adopts the all-digital technology to obtain higher calibration precision with low area and power consumption.
Description
Technical Field
The utility model is suitable for an application scenario of clock duty cycle calibration in various high-speed communication transmission, like high-speed data memory, pipelined treater etc. belongs to the technical field of duty cycle calibration circuit design.
Background
With the continuous progress of the integrated circuit technology, the operating speed of the chip is continuously improved, and technologies such as Double Data Rate (DDR) and Pipeline (Pipeline) have been widely adopted to obtain a larger Data throughput Rate, which requires a stricter timing accuracy, that is, the performance requirement on the system clock is higher, wherein an important performance index is the duty ratio of the clock. A 50% duty cycle clock is most advantageous for data propagation, whereas for a system using a dual data rate, pipelined operation, a 50% duty cycle ensures that data is properly established and maintained during transmission, ensuring that the system operates properly and stably.
In practical application, a clock of a system is often generated through a phase-locked loop (PLL) or a delay-locked loop (DLL), and due to mismatch generated by circuit design itself and deviation of a process and a simulation model in a chip manufacturing process, the clock generated after frequency multiplication and synchronization cannot often guarantee 50% of duty ratio. In addition, during the clock propagation, the duty ratio of the clock is also mistuned due to the systematic and process variations in the propagation link. Especially in high frequency applications, the misalignment of the duty cycle may even cause the clock signal not to flip normally, resulting in serious timing errors. Therefore, in the occasion of strict requirement on duty ratio, it is necessary to add a duty ratio calibration circuit.
At present, duty ratio calibration modes are mainly divided into two types: analog and digital. Analog approaches generally achieve higher duty cycle correction accuracy, operate at higher frequencies, and achieve less edge jitter, but analog approaches also suffer from long settling times, difficult system stability design, and significant process-voltage-temperature (PVT) variation effects. The duty ratio calibration in a pure digital mode can achieve the excellent characteristics of quick establishment, absolute stability, insignificant influence of PVT deviation and the like. However, since the digital mode is limited by the minimum delay unit, the calibration accuracy has discreteness, and an accurate calibration result cannot be obtained. And combining the two can achieve fast set-up and high correction accuracy.
Disclosure of Invention
The technical problem is as follows:the utility model aims at providing a digital analog mixed mode clock duty cycle calibration circuit that can solve the technical problem mentioned in the above-mentioned background solves the duty cycle calibration problem of clock in high-speed system.
The technical scheme is as follows:in order to solve the technical problem, the utility model provides a digital-analog mixed mode clock duty cycle calibration circuit, this circuit include impulse generator, halfThe circuit comprises a periodic delay line, an RS trigger, a single-end-to-differential conversion circuit, a digital-analog hybrid charge pump and an error amplifier; wherein,
the input end of the pulse generator is connected with an original input clock signal to be calibrated; the output end signal of the pulse generator is a buffered input clock pulse signal which is simultaneously connected to the clock input end of the half-cycle delay line and the RS trigger bit input end; the output end signal of the half-cycle delay line, namely the half-cycle delay clock pulse signal, is connected with the reset input end of the RS trigger; the signal at the output end of the RS trigger is the calibrated clock signal; the calibrated clock signal is input to the input end of the single-end-to-differential conversion circuit; the output signals of the single end to the output end of the differential conversion circuit are a differential clock positive signal and a differential clock negative signal; the differential clock positive signal and the differential clock negative signal are respectively connected to the homonymous input end of the digital-analog hybrid charge pump, and differential voltage is generated between the first output end and the second output end of the digital-analog hybrid charge pump; the differential voltage is input to a differential input terminal of an error amplifier, an output terminal of the error amplifier is a duty ratio fine-tuning control voltage, and the duty ratio fine-tuning control voltage is input to a delay time control input terminal of a half-cycle delay line.
Preferably, the half-cycle delay line HCDL is formed by sequentially connecting a basic delay unit and one to several stages of half-cycle delay line units in series; the first signal input end of the basic delay unit, namely the input end of the forward delay line, is connected with an input clock signal of the input end of the half-cycle delay line, the second signal input end of the basic delay unit is connected with a high level, the enable end of the basic delay unit DLY is connected with a high level, the control signal input end of the basic delay unit is connected with a low level, the output end of the basic delay unit is connected with the first signal input end of the first-stage half-cycle delay line unit, the second signal input end of the first-stage half-cycle delay line unit, namely the enable input end of the delay line, is connected with a high level, the fourth signal input end of the first-stage half-cycle delay line unit, namely the edge detection input end, is grounded, and the third signal output end of the first-stage half-; a first signal input end, namely a forward delay line input end, of each stage of half-cycle delay line unit is connected with a first signal output end, namely a forward delay line output end, of a previous stage of half-cycle delay line unit, a second signal input end, namely a delay line enable input end, is connected with a second signal output end, namely a delay line enable output end, of a previous stage, and a third signal output end, namely a reverse delay line output end, is connected with a third signal input end, namely a reverse delay line input end, of the previous stage; the third signal input end of the last stage half period delay line unit, namely the reverse delay line input end, is connected with a low level; the fifth signal input end, namely the control signal input end of each stage of half-cycle delay unit is connected with the homonymous port of the basic delay unit and is connected with the delay time control input end of the half-cycle delay line in parallel; the fourth signal input end, namely the edge detection input end, of each stage of half-cycle delay line unit except the first stage is connected with the input clock pulse signal of the half-cycle delay line input end; the signal input and output terminals not mentioned above are floating in the half cycle delay line cell.
Preferably, the basic delay unit in the half-cycle delay line uses a voltage-controlled current unsaturated inverter controlled by a control voltage to realize continuous adjustable delay time; the basic delay unit adopts a dynamic structure of edge-triggered automatic refresh, and the width of the generated positive pulse is constant.
Preferably, the digital-analog hybrid charge pump and the error amplifier form an analog closed-loop fine tuning circuit; the digital-analog hybrid charge pump adopts a self-biasing structure, and converts the duty ratio deviation of a differential clock positive signal and a differential clock negative signal into differential output voltages of a first output end and a second output end of the digital-analog hybrid charge pump; the error amplifier is a complementary amplifier formed by connecting an NMOS input single-stage transconductance amplifier and a PMOS input single-stage transconductance amplifier in parallel, amplifies the differential output voltage of the digital-analog hybrid charge pump, converts the differential input into single-ended output control voltage, feeds the output control voltage back to the delay time control input end of the half-cycle delay line, and finely adjusts the delay time of the half-cycle delay line.
Has the advantages that:the circuit integrates the advantages of a digital mode and an analog mode, combines the digital mode and the analog mode, adopts a digital open-loop structure to realize coarse calibration and an analog closed-loop structure to realize fine calibration, improves the establishing speed and the calibration precision, and simultaneously adopts a full digital process to be convenient for integration with a digital system. Compared with the prior art, the utility model has the advantages of:
1. for pure simulation duty cycle calibration mode, the utility model discloses in the duty cycle calibration circuit that describes adopt half cycle delay line to carry out coarse calibration, have advantages such as quick establishment, better stability.
2. For pure digital duty cycle calibration mode, the utility model discloses an analog feedback loop carries out automatic correction to the delay time of half cycle delay line unit, has higher clock duty cycle calibration precision to overcome the discreteness of pure digital duty cycle calibration, compromise adjustment accuracy and phase resolution.
3. The utility model discloses structure to digital duty cycle calibration circuit half cycle delay line and its basic delay unit have improved, make basic delay unit delay time continuously adjustable to can save the matching delay line. The negative feedback structure enables the PVT deviation to be resisted better, and the work is more reliable under the same process condition.
4. The utility model discloses a continuous adjustable closed loop fine setting circuit, under the same input clock frequency range, need the basic delay unit still less, reduced area and consumption.
The utility model discloses a digital analog mixed mode clock duty cycle calibration is realized to the full digital technology, is convenient for integrate with other digital systems.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a global timing diagram of the present invention;
FIG. 3 is a schematic diagram of a pulse generator;
FIG. 4 is a schematic diagram of a half-cycle delay line structure;
FIG. 5 is a schematic diagram of a half-cycle delay line unit structure;
FIG. 6 is a schematic diagram of a basic delay cell circuit structure according to the present invention;
FIG. 7 is a schematic diagram of an RS flip-flop;
FIG. 8 is a schematic diagram of a single-ended to differential conversion circuit;
FIG. 9 is a schematic diagram of an in-phase buffer structure;
fig. 10 is a schematic diagram of the circuit structure of the digital-analog hybrid charge pump of the present invention.
Fig. 11 is a schematic diagram of an error amplifier circuit.
Among them are: a pulse generator PG 1, an original input clock signal CKI, a buffer clock signal CKB generated by the pulse generator, a half-cycle delay line HCDL2, an RS trigger 3, a half-cycle delay clock signal CKD, a clock signal CKG synthesized by the RS trigger, a calibrated homodromous clock signal CKO +, a calibrated reverse clock signal CKO-, a half-cycle delay line unit 2-1 forward delay line input end FDI, a half-cycle delay line unit delay line enable input end ENI, a half-cycle delay line unit reverse delay line output end BDO, a half-cycle delay line unit reverse delay line input end BDI, a half-cycle delay line unit delay line enable output end ENO, a half-cycle delay line unit forward delay line output end FDO, a half-cycle delay line delay time control input end, a half-cycle delay line unit edge detection input end CI, a traditional basic delay unit, A modified elementary delay unit 2-2, a single-ended to differential conversion circuit STD 4, a digital-to-analog hybrid charge pump CCP 5, an error amplifier 6.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings.
An object of the utility model is to provide a not enough to current digital mode duty cycle calibration circuit existence, provide one kind and can carry out the circuit structure that the duty cycle was calibrated at wideer frequency, duty cycle within range under appointed technology. In addition, the proposed scheme has better inhibition on phenomena such as process mismatch and the like.
The utility model discloses full digital technology digital analog mixed mode clock duty cycle calibration circuit, this circuit include impulse generator PG 1, half cycle delay line HCDL2, RS flip-flop 3, single-ended to difference converting circuit STD 4, digital analog mixed charge pump CCP 5, error amplifier 6.
The input end of a pulse generator 1 in the circuit is connected with an original input clock signal CKI to be calibrated; the output end signal of the pulse generator 1 is a buffered narrow pulse CKB with a fixed pulse width after the original input clock signal is buffered, and the signal is simultaneously connected to the clock input end of the half-period delay line HCDL2 and the set input end S of the RS flip-flop 3; the output end signal of the half-cycle delay line HCDL2 is a half-cycle delay signal CKD delayed by a half clock cycle relative to the buffered narrow pulse signal CKB, and the half-cycle delay signal is connected with the reset input end R of the RS flip-flop 3; a signal at an output end Q of the RS trigger 3 is a calibrated clock signal CKG with 50% duty ratio, the signal is connected with a single end to an input end of the differential conversion circuit STD 4, and two output signals from the single end to the differential conversion circuit STD 4 are calibrated differential calibration clock signals CKO + and CKO-with 50% duty ratio; meanwhile, two output signals CKO + and CKO-of the single-end to differential conversion circuit STD 4 are respectively connected to differential homonymous input ends CKO + and CKO-of the charge pump CCP 5 with the digital-analog mixed structure; a first output signal FP and a second output signal FN of the charge pump CCP with the digital-analog mixed structure are respectively connected to an inverting input end V-and a homodromous input end V + of the error amplifier 5; the output signal of the error amplifier 5 is fed back to the delay time control input end VCR of the half-cycle delay line HCDL2, the delay time of the half-cycle delay unit 2-1 is adjusted, and the duty ratio is finely corrected. The pulse generator 1 is used for buffering an original input clock signal, generating a buffering narrow pulse signal CKB with constant pulse width and fixed delay relative to the rise of the original input clock signal, and ensuring the fan-out capability of the clock signal to a subsequent circuit; the half-cycle delay line HCDL2 is used for generating a half-cycle delayed clock signal CKD having a half-clock cycle delay with respect to the buffered narrow pulse signal CKB; the RS trigger 3 synthesizes a calibration clock signal CKG with 50% duty ratio by using a buffer narrow pulse signal CKB and a half-cycle delay signal CKD, the difference of the rising edges of which is exactly half a cycle, and utilizing a rising edge triggering principle; the single-end-to-differential conversion circuit STD 4 converts the single-end signal into differential signals CKO + and CKO-; the digital-analog hybrid charge pump CCP 5 is used to detect the difference between the CKO + and CKO-duty ratios and convert the difference into a voltage difference between FP and FN, the voltage difference is amplified by the error amplifier 6 and fed back to the delay time control input end VCR of the half-cycle delay line HCDL2, the delay time of the basic delay unit DLY 2-1-1 is adjusted, the delay time of the output clock signal of the half-cycle delay line HCDL2 relative to the input clock thereof is made to be exactly half clock cycle, and thus the differential calibration clock signals CKO + and CKO-with high calibration accuracy and 50% duty ratios are obtained.
The pulse generator PG 1, as shown in fig. 1, is a basic pulse generating circuit, and the size of the inverter 101 is appropriately selected to change the output pulse width and provide sufficient fan-out driving capability.
The half-cycle delay line HCDL2 is formed by sequentially connecting a basic delay unit DLY 2-2 and one to a plurality of stages of half-cycle delay line units HCDLU 2-1 in series, and the series connection method comprises the following steps: the first signal input terminal IN1 of the basic delay cell DLY 2-2, i.e., the forward delay line input terminal, is connected to the input clock signal CKB at the half-cycle delay line HCDL2 input terminal, the second signal input terminal IN2 of the basic delay cell DLY 2-2 is connected to the high level, the enable terminal EN of the basic delay cell DLY 2-2 is connected to the high level, the control input terminal VC of the basic delay cell DLY 2-2 is connected to the low level, the output terminal OUT of the basic delay cell DLY 2-2 is connected to the first signal input terminal FDI of the first-stage half-cycle delay line cell HCDLU 2-1, the second signal input terminal EDI of the first-stage half-cycle delay line cell DLU 2-1, i.e., the delay line enable input terminal, the fourth signal input terminal CI at the first-stage half-cycle delay line cell HCDLU 2-1, the third signal output terminal CI of the reverse delay line at the first-stage half-cycle delay line cell HCDL 2-1 The BDO signal at the end is a half-cycle delay clock signal at the output end of the half-cycle delay line HCDL 2; a first signal input end FDI (forward delay line input end) of each stage of half-cycle delay line unit HCDLU 2-1 is connected with a first signal output end FDO (forward delay line output end) of the previous stage of half-cycle delay line unit HCDLU 2-1, a second signal input end EDI is connected with a second signal output end EDO of the previous stage, and a third signal output end BDO is connected with a third signal input end BDI of the previous stage; the third signal input end BDI of the last stage half-cycle delay line unit HCDLU 2-1, namely the reverse delay line input end BDI, is connected with low level; a fifth signal input end, namely a control signal input end VC of each stage of half-period delay unit HCDLU 2-1 is connected with a delay time control input end VCR of the HCDL 2; the fourth signal input end, namely the edge detection input end CI of each stage of half-cycle delay line unit HCDLU 2-1 except the first stage is connected with the input clock signal CKB of the half-cycle delay line HCDL2 input end; the signal input and output terminals not mentioned above are floating in all half-cycle delay line units HCDLU 2-1.
In the RS trigger 3, a set input end S of the RS trigger is connected with an input end of a first phase inverter, and a reset input end R of the RS trigger 3 is connected with an input end of a second phase inverter; the output ends of the first inverter and the second inverter are respectively connected with the first signal input ends of the first NAND gate and the second NAND gate, and the second signal input ends of the first NAND gate and the second NAND gate are respectively connected with the output ends of the second NAND gate and the first NAND gate; the input end of the third inverter is connected with the output end of the first NAND gate, and the fourth inverter is connected with the output end of the second NAND gate; the output end of the fourth inverter is the output end Q of the RS flip-flop 3.
The single-ended to differential conversion circuit STD 4 is composed of an in-phase buffer 4-1 and an inverter, and the structure is completely symmetrical. In the circuit, a single-ended input signal CKG is connected with the input ends of a first inverter, a second inverter and a first in-phase buffer 4-1; the output end of the first inverter is connected with the input ends of the third inverter and the second in-phase buffer 4-1; the output end of the first non-inverting buffer 4-1 is connected with the output end of the third inverter, is connected with one end of a latch formed by connecting the fourth inverter and the fifth inverter end to end, and is also connected with the input end of the sixth inverter; the output end of the second in-phase buffer 4-1 is connected with the output end of the second inverter, is connected with the other end of the latch formed by the end-to-end connection of the fourth inverter and the fifth inverter, and is also connected with the input end of the seventh inverter; the output ends of the sixth inverter and the seventh inverter are the reverse output end CKO-and the homodromous output end CKO +.
The sources, drains and substrates of the first and second transistors NM1, NM2 in the digital-analog hybrid charge pump CCP 5 are all grounded, and the gates are respectively connected with the gates of the third and fourth transistors NM3, NM 4; the sources and the substrates of the third and the fourth transistors are grounded, and the drains are connected with the sources of the fifth and the sixth transistors NM5 and NM6 in parallel; the grid electrodes of the fifth transistor and the sixth transistor are respectively connected with the grid electrodes of the seventh transistor, the eighth transistor PM1 and the PM2 and respectively connected with a charge pump homodromous input end CKO + and a reverse input end CKO-, the drain electrodes of the fifth transistor and the sixth transistor are respectively connected with the drain electrodes of the seventh transistor and the eighth transistor, and the substrates of the fifth transistor and the sixth transistor are grounded; the sources of the seventh transistor and the eighth transistor are connected with the drains of the ninth transistor and the tenth transistor PM3 and PM4, and the substrates of the seventh transistor and the eighth transistor are connected with high level; the source electrodes and the substrate of the ninth transistor and the tenth transistor are both connected with high level; the grids of the first, third and ninth transistors and the drains of the fifth and seventh transistors are connected to the inverted output FN of the charge pump CCP 5, and the grids of the second, fourth and tenth transistors and the drains of the sixth and eighth transistors are connected to the unidirectional output FP of the charge pump CCP 5.
The error amplifier OTA 6 is formed by connecting a basic NMOS tube differential input transconductance amplifier and a single-end output transconductance amplifier in parallel with a basic PMOS tube differential input transconductance amplifier and a single-end output transconductance amplifier, and has wider bandwidth and rail-to-rail input and output voltage swing amplitude.
The utility model discloses well half cycle delay line and have its closed loop circuit who forms with digital analog mixed charge pump, error amplifier etc. is the key module who realizes the duty cycle calibration. As shown in fig. 4, the buffered narrow pulse signal CKB input into the half-cycle delay line first propagates rightward in the forward delay line composed of the basic delay cells whose delay times Δ are not adjustable. When the next external clock signal arrives, the clock signal that has propagated for one clock cycle in the forward delay line propagates to the left through a series of decision and gating circuits into the reverse delay line. The circuit is designed such that the clock signal passes through 2N +1 elementary delay cells in the sinusoidal delay line and N elementary delay cells in the inverted delay line. The control input end VC of a basic delay unit in the forward delay line is always grounded, and the delay time of the basic delay unit is fixed to delta; and the control input end of the basic delay unit in the reverse delay line is connected with the output end of the error amplifier, and the output voltage is determined by the duty ratio of the calibrated differential clock signals CKO + and CKO-, so that the delay time of the basic delay unit in the reverse delay line is adjustable and is delta + delta. When the loop is stable, the clock signal is propagated through the forward and reverse delay lines and then the total time of the clock signal is just 1.5 clock cycles, so that the accurate half-cycle phase difference is generated with the original buffered clock signal. The RS flip-flop alternately sets and resets using edge triggering using the buffered original input clock signal and the half-period delayed clock signal, synthesizing a calibrated output clock signal CKG having a duty cycle of 50%. The single-end to double-end conversion circuit, the digital-analog mixed charge pump and the error amplifier detect the duty ratio information of the calibration output clock signal CKG and feed back the duty ratio information to the half-period delay line, and the delay time of the reverse delay line is adjusted to enable the duty ratio of the calibration output clock signal CKG to be gradually close to 50%. The operating waveform of the circuit for completing the duty ratio calibration is shown in fig. 2.
1. Pulse generator
Because the requirement clock signal of half cycle delay line has great driving force to require input clock pulse can not too wide nor too narrow in order to guarantee to measure accurate reliable, the utility model discloses pulse generator circuit produces and has a fixed delayed positive narrow pulse signal for input clock rising edge, as shown in fig. 3, and the output phase inverter size that uses in this example is great, has stronger load capacity, makes the width of narrow pulse satisfy above-mentioned requirement simultaneously, is about 2.5 delta.
2. Half-cycle delay line
The half-cycle delay line is formed by sequentially connecting a basic delay unit and a plurality of stages of half-cycle delay line units in series, as shown in fig. 4. Each stage of half-cycle delay line unit, the forward delay line input FDI and the forward delay line output FDO in fig. 5 and two basic delay units therebetween, together form a forward delay line unit of the input clock signal. Each rising edge of the input clock signal CKB will fire a positive narrow pulse propagating to the right in the forward delay line. Each stage of half-cycle delay line unit, the inverted delay line input terminal BDI and the inverted delay line output terminal BDO in fig. 5 and a basic delay unit therebetween, together constitute an inverted delay line unit of the input clock signal. When a positive pulse is obtained at the input IN2 of any one of the basic cells of the backward delay line, a narrow positive pulse propagating to the left is excited IN the backward delay line.
When the rising edge of the next input clock signal CKB arrives, it is assumed that a positive narrow pulse excited by the rising edge of the previous input clock signal CKB in the forward delay line propagates to the kth half-cycle delay line unit, and at this time, the voltage of the node a in each half-cycle delay unit before the kth stage is all at a low level, so that the ENO voltage at the enable output terminal is always at a high level; a node A in the kth stage half-cycle delay line unit has a positive narrow pulse, and an enable output end ENO has a negative pulse; the voltage of the node A in each stage of half-cycle delay unit after the kth stage is all low level, the ENO voltage at the enable output end is always low level, the enable end signal prohibits the signal from propagating in each stage of half-cycle delay unit after the ENO voltage, and the redundant positive pulse is prevented from continuously propagating in the forward or reverse delay line. The positive narrow pulse at the node a IN the kth stage half-period delay line unit is transmitted to the second input terminal IN2 of the reverse basic delay unit, and a positive narrow pulse delayed by delta + delta relative to the narrow pulse at the reverse delay line output terminal BDO of the kth stage half-period delay unit is obtained, the narrow pulse is transmitted to the reverse delay input terminal BDI of the kth-1 stage half-period delay line, and is output from the reverse delay output terminal BDO of the kth-1 stage half-period delay line through delta + delta delay, and so on, the narrow pulse is transmitted IN reverse until the reverse delay output terminal BDO of the first stage half-period delay line is output, so that the output signal CKD of the half-period delay line is obtained.
In the signal propagation process, a signal is transmitted in the forward direction through the first basic delay unit and k half-cycle delay units after the first basic delay unit, each half-cycle delay unit comprises two basic delay units on a forward transmission path, and therefore the total delay time of the forward propagation is (2 k + 1) delta and is about 1 clock cycle T. The signal is reversely transmitted through k half-cycle delay units, each half-cycle delay unit comprises a basic delay unit on a reverse transmission path, and the delay time of the basic delay unit on the reverse delay path is adjustable, so that the total delay time of reverse propagation is k (delta + delta), wherein the value of delta is controlled by a closed loop, and after the establishment of the duty ratio calibration circuit is completed, 2k (delta + delta) = T is met, and at the moment, the output signal of the duty ratio calibration circuit is a clock signal with a duty ratio of 50%.
The elementary delay cells are the key elements of a half-cycle delay line. The traditional basic delay unit is formed by connecting a NAND gate and a NOT gate in series. Due to the objective existence of the performance mismatch between the P-transistor and the N-transistor in the CMOS process, the propagation speeds of the front edge and the back edge of the clock signal are not equal when the clock signal propagates in the basic delay unit. The speed difference is accumulated gradually to be light, so that the calibration error of the circuit is increased, and the performance is degraded; the heavy pulse causes the positive or negative narrow pulse propagating in the delay line to disappear, and the circuit cannot work. In addition, the delay time of the traditional basic delay unit is uncontrollable and cannot meet the requirement.
The utility model discloses a basic delay cell is as shown in FIG. 6, and initial, basic delay cell enable signal EN is invalid level (low level), and control signal input VC is the low level, and then PM1 switches on, and NM1, PM2 end, and PM4 and NM6 grid are the high level. When the first delayed signal input terminal IN1 node is low, the gate of NM2 is precharged to high. At the instant when the node of the first delayed signal input terminal IN1 generates a rising edge, the gate of NM4 is charged high, and the precharge of the gate of NM2 is not fully discharged, so that NM2 and NM4 are turned on simultaneously. If the basic delay cell enable signal EN is active (high), NM1 is also turned on, PM1 is turned off, and the PM4 and NM6 gates are discharged to low level. However, IN the low or high continuous period of the signal at the first delay signal input terminal IN1, the falling time of the signal at the first delay signal input terminal IN1, or the low period of the basic delay unit enable signal EN, the conditions of NM1, NM2, and NM4 turning on simultaneously cannot be satisfied, and at this time, the gates of PM4 and NM6 are gradually charged from PM1 or PM2 to high level. IN general, when the enable signal EN is high and the voltage at the control signal input VC is sufficient to turn on PM3, a rising edge of the signal at the first delayed signal input IN1 will generate a negative pulse at the gates P4 and N8. The negative pulse passes through a delay time controllable inverter consisting of PM3, PM4 and NM6 to generate a positive pulse with an ideal edge as a delay output signal of the basic delay unit. The second delayed signal input IN2 is logically ORed with IN1, as is the first delayed signal input IN 1. The improved basic delay unit has the advantages that the pulse width of the positive pulse propagating in the delay line formed by the basic delay unit can be stably maintained at an appropriate value, and the specific width of the pulse width does not influence the performance of the circuit. Meanwhile, in the forward and reverse delay lines, the propagation delay of the rising edge of the pulse is used as the propagation delay of the whole delay line, so that the forward and reverse delay lines have better consistency. In addition, the basic unit uses a voltage-controlled current unsaturated inverter to realize continuous adjustment of the delay time of the basic delay unit, the larger the voltage value of the control voltage is, the larger the delay time of the basic delay unit is, so that the delay time of the basic delay unit is delta + delta (delta is variable), the delay time of the half-cycle delay line is accurate to a half cycle, and the discrete error existing in the digital duty ratio calibration circuit is eliminated, so that the calibration accuracy is more accurate.
3. RS trigger
The design key of the RS flip-flop that synthesizes the calibration clock signal CKG with a 50% duty cycle is to more precisely match the path delays from the set terminal S to the output terminal Q, and from the reset terminal R to the output terminal Q. The present invention uses the structure shown in fig. 7 to achieve the desired functionality. The utility model discloses the adoption comprises input/output phase inverter and two NAND gates, like the complete symmetry of picture structure, guarantees that set input S and reset input R have the same delay to RS flip-flop' S output Q. In addition, in the invention, because the duty ratio maladjustment can be automatically adjusted through the loop, the requirement on the RS trigger is reduced, even if the delay time from the set input end S and the reset input end R to the output end Q of the RS trigger is slightly different, the loop can correct the duty ratio to 50 percent, and the strength of the circuit for resisting PVT change is improved.
4. Single-ended to differential conversion circuit
The single-ended to differential conversion circuit STD converts the output clock signal CKG synthesized by the RS flip-flop into differential output clocks CKO + and CKO-. The utility model discloses in the STD circuit structure that adopts is complete symmetrical, as shown in fig. 8, this circuit can reduce the skew of differential clock and the output clock duty cycle maladjustment that arouses by the PVT change, has improved the performance of circuit.
5. Analog closed loop fine tuning circuit
The adjustment of the conventional pure digital duty ratio calibration circuit has discreteness, and the adjustment accuracy is determined by the delay time of the basic delay unit, so that the adjustment accuracy and the phase resolution are difficult to be compatible in terms of power consumption and area. The utility model provides a closed loop fine setting circuit that constitutes by duty cycle fine setting detection and control and traditional half cycle delay line has overcome above-mentioned shortcoming. The utility model provides a mixed mode duty cycle calibration circuit overcomes above-mentioned shortcoming through the closed loop fine setting circuit of introducing the simulation on traditional pure digital mode's duty cycle calibration circuit basis. The closed-loop fine-tuning circuit is composed of a digital-analog hybrid charge pump CCP 5 (figure 10) and an error amplifier OTA 6 (figure 11), completes duty ratio maladjustment detection, generates a duty ratio fine-tuning control signal, adjusts the delay time of a half-period delay line, and achieves duty ratio fine tuning.
The duty cycle deviation of difference output clock signal is detected and is converted into the voltage difference between charge pump differential output FP and the FN by the mixed charge pump of digifax (fig. 10), the utility model provides a mixed charge pump of digifax can reduce the output voltage ripple, produces the output voltage of accurate reflection duty cycle information. In order to obtain sufficient calibration accuracy, an error amplifier needs to be added after the charge pump, namely, the voltage difference between the differential output ends FP and FN of the charge pump is amplified by the error amplifier to obtain the duty fine-tuning control voltage signal Vout. Considering that the stability and lock time of an analog closed loop trimming circuit is proportional to the error amplifier bandwidth and inversely proportional to its gain, this requires a compromise between gain and bandwidth for the error amplifier. The utility model discloses an error amplifier as shown in fig. 11, this error amplifier is parallelly connected the complementary amplifier that forms by a NMOS input single-stage transconductance amplifier and a PMOS input single-stage transconductance amplifier, has wideer bandwidth and rail to rail input/output swing. The digital-analog hybrid charge pump CCP 5 and the error amplifier OTA 6 both save a constant current source, save a bias circuit, reduce power consumption and facilitate full-digital integration.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, but all equivalent modifications or changes made by those skilled in the art according to the present invention should be included in the protection scope of the claims.
Claims (4)
1. A digital-analog mixed mode clock duty cycle calibration circuit is characterized in that: the circuit comprises a pulse generator (1), a half-cycle delay line (2), an RS trigger (3), a single-ended-to-differential conversion circuit (4), a digital-analog hybrid charge pump (5) and an error amplifier (6); wherein,
the input end of the pulse generator (1) is connected with an original input clock signal (CKI) to be calibrated; the output end signal of the pulse generator (1) is a buffered input clock pulse signal (CKB), and the signal is simultaneously connected to the clock input end of the half-cycle delay line (2) and the set input end (S) of the RS trigger (3); the output end signal of the half-cycle delay line (2), namely the half-cycle delay clock pulse signal (CKD), is connected with the reset input end (R) of the RS trigger (3); the signal at the output end (Q) of the RS trigger (3) is the calibrated clock signal (CKG); the calibrated clock signal (CKG) is input to an input end of the single-ended-to-differential conversion circuit (4); the output signals of the output end of the single-end to differential conversion circuit (4) are a differential clock positive signal (CKO +) and a differential clock negative signal (CKO-); the differential clock positive signal (CKO +) and the differential clock negative signal (CKO-) are respectively connected to the homonymous input end of the digital-analog hybrid charge pump (5), and differential voltage is generated between a first output end (FP) and a second output end (FN) of the digital-analog hybrid charge pump; the differential voltage is input to a differential input terminal of an error amplifier (6), and an output terminal of the error amplifier (6) is a duty ratio fine adjustment control voltage which is input to a delay time control input terminal (VCR) of a half-cycle delay line (2).
2. The digital-to-analog mixed mode clock duty cycle calibration circuit of claim 1, wherein: the half-cycle delay line (2) is formed by sequentially connecting a basic delay unit (2-2) and one to a plurality of stages of half-cycle delay line units (2-1) in series; wherein, a first signal input terminal (IN 1), namely a forward delay line input terminal, of the basic delay unit (2-2) is connected with an input clock signal (CKB) of an input terminal of the half-period delay line (2), a second signal input terminal (IN 2) of the basic delay unit (2-2) is connected with a high level, an enable terminal (EN) of the basic delay unit (2-2) is connected with a high level, a control signal input terminal (VC) of the basic delay unit (2-2) is connected with a low level, an output terminal (OUT) of the basic delay unit (2-2) is connected with a first signal input terminal (FDI) of the first-stage half-period delay line unit (2-1), a second signal input terminal, namely a delay line enable input terminal (EDI) of the first-stage half-period delay line unit (2-1) is connected with a high level, a fourth signal input terminal, namely an edge detection input terminal (CI) of the first-stage half-period delay line unit (2, the third signal output end of the first stage half-cycle delay line unit (2-1), namely the output end (BDO) of the reverse delay line, is also the output end of the half-cycle delay line (2); a first signal input end (FDI), namely a forward delay line input end (FDI), of each stage of half-cycle delay line unit (2-1) is connected with a first signal output end (FDO), namely a forward delay line output end (FDO), of the previous stage of half-cycle delay line unit (2-1), a second signal input End (EDI), namely a delay line enable input End (EDI), is connected with a second signal output End (EDO), namely a delay line enable output End (EDO), and a third signal output end (BDO), namely a reverse delay line output end (BDO), is connected with a third signal input end (BDI), namely a reverse delay line input end (BDI), of the previous stage; the third signal input end of the last stage half-cycle delay line unit (2-1), namely the reverse delay line input end (BDI), is connected with low level; a fifth signal input end, namely a control signal input end (VC) of each stage of half-cycle delay unit (2-1) is connected with a homonymous port of the basic delay unit (2-2) and is connected with a delay time control input end (VCR) of the half-cycle delay line (2) in parallel; the fourth signal input end, namely an edge detection input end (CI) of each stage of half-period delay line unit (2-1) except the first stage is connected with an input clock pulse signal (CKB) of the input end of the half-period delay line (2); the signal input and output terminals in the half-cycle delay line unit (2-1) are floating.
3. The digital-to-analog mixed mode clock duty cycle calibration circuit of claim 2, wherein: the basic delay unit (2-2) in the half-cycle delay line (2) uses a voltage-controlled current unsaturated inverter controlled by a control voltage to realize continuous adjustable delay time; the basic delay unit (2-2) adopts a dynamic structure of edge-triggered automatic refresh, and the width of the generated positive pulse is constant.
4. The digital-to-analog mixed mode clock duty cycle calibration circuit of claim 1, wherein: the digital-analog hybrid charge pump (5) and the error amplifier (6) form an analog closed loop fine tuning circuit; the digital-analog hybrid charge pump (5) adopts a self-biasing structure, and the digital-analog hybrid charge pump (5) converts the duty ratio deviation of a differential clock positive signal (CKO +) and a differential clock negative signal (CKO-) into differential output voltages of a first output end (FP) and a second output end (FN) of the digital-analog hybrid charge pump (5); the error amplifier (6) is a complementary amplifier formed by connecting an NMOS input single-stage transconductance amplifier and a PMOS input single-stage transconductance amplifier in parallel, differential output voltage of the digital-analog hybrid charge pump (5) is amplified by the error amplifier (6), differential input is converted into single-ended output control voltage, the output control voltage is fed back to a delay time control input end (VCR) of the half-cycle delay line (2), and delay time of the half-cycle delay line is finely adjusted.
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