CN105958971A - Clock duty ratio calibration circuit - Google Patents

Clock duty ratio calibration circuit Download PDF

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Publication number
CN105958971A
CN105958971A CN201610388948.8A CN201610388948A CN105958971A CN 105958971 A CN105958971 A CN 105958971A CN 201610388948 A CN201610388948 A CN 201610388948A CN 105958971 A CN105958971 A CN 105958971A
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China
Prior art keywords
clock
clock signal
signal
pmos
nmos tube
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CN201610388948.8A
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Inventor
楼文峰
凌宇
谢循
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Micro Electronics (shanghai) Co Ltd
Telink Semiconductor Shanghai Co Ltd
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Micro Electronics (shanghai) Co Ltd
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Priority to CN201610388948.8A priority Critical patent/CN105958971A/en
Publication of CN105958971A publication Critical patent/CN105958971A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/017Adjustment of width or dutycycle of pulses

Abstract

The invention relates to the integrated circuit design field, and discloses a clock duty ratio calibration circuit. The invention discloses a clock duty ratio calibration circuit. The clock duty ratio calibration circuit includes a pulse generator, a pulse width modulator, a trigger, a comparator and a low pass filter, wherein the pulse generator inputs a first clock signal and outputs a second clock signal; the duty ratio of the second clock signal is less than 50%; the pulse width modulator inputs the second clock signal and a feedback signal, and outputs a third clock signal; the trigger inputs the third clock signal and outputs a calibration clock signal; the low pass filter inputs the calibration clock signal and outputs a fourth clock signal; and the positive end of the comparator inputs the fourth clock signal, and the negative end of the comparator inputs the reference voltage, and the comparator outputs the feedback signal. Compared with the prior art, the clock duty ratio calibration circuit can improve the duty ratio calibration accuracy of any one duty ratio input clock and output any one duty ratio clock, and also has the advantages of being simple in the circuit structure, being small in the area of the chip, and being high in resistance to the influence of changes of technology, temperature and voltage.

Description

A kind of clock duty cycle calibration circuit
Technical field
The present invention relates to IC design field, particularly to a kind of clock duty cycle calibration circuit.
Background technology
Along with the development of electronic technology, and electron controls technology is constantly employed and controls various The Circuits System of various kinds.The simple circuit that controls can only realize connecting operation element circuit or cutting off work unit Two kinds of situations of part circuit, namely open or close.But this simple on-off control action can not be expired The requirement of foot many accuracy-control systems work.And, for the requirement of system control accuracy be subject to The many factors such as power consumption limit, the line style that most element can realize from gradually reaching gradually close regulates and controls. This linear regulation gradually reaching gradually close, it is necessary to be applied to Duty ratio control.
High-speed serial data is received and dispatched when, typically reduce power consumption with reduction working clock frequency and make an uproar Sound, so being used for sending data at the rising edge of transmitter clock and trailing edge, upper at receptor equally Rising edge and trailing edge is used for sampling data, this just requires that the dutycycle of clock must assure that is 50%. The clock of 50% dutycycle is widely used in the static RAM of double data rate (DDR) (DDR) SRAM, delay phase-locked loop (DDL) circuit, the D/A converting circuit of bilateral sampling so that it is upper Rise edge and trailing edge can work simultaneously, improve the transfer rate of signal.Nowadays at a lot of phaselocked loops (PLL) In the overtones band circuit of reference clock, before frequency multiplication, the reference clock of input must be carried out 50% dutycycle Calibration, so that the later clock signal of frequency multiplication can be as the ginseng of two frequencys multiplication of phaselocked loop (PLL) Examine clock, the overall performance improving phaselocked loop (PLL) frequency synthesizer.In realizing process of the present invention, Inventor finds clock duty cycle calibration circuit system design complexity in prior art, and chip occupying area is relatively Greatly, the precision of this type of calibration circuit is easily affected by technique, temperature, voltage etc., and can only adjust relatively The dutyfactor value of little scope is calibrated, it is not possible to carries out any clock duty cycle calibration, greatly limit The practicality of calibration circuit.
It addition, there is a kind of pulse-width controlled under high-speed cmos clock buffer circulation electricity in prior art Road, the most as shown in Figure 1:
The program is by CK to be adjustedin, by clock signal CK after being adjusted by pulse width regulating circuitoutSend Detect to electric charge pump 1 (CP1) and electric capacity C1, then compared with reference voltage by comparator, If CKoutPulse less than 50%, then the charging interval extending C1 makes the voltage V on electric capacity C1c Increase, until VcValue more than reference voltage Vref, so that voltage raises on C3, thus regulate arteries and veins Wide modulation circuit, makes dutycycle reduce, carrying out detection feedback the most repeatedly so that whole system reaches One balance, CKoutOutput duty cycle be 50%, whole duty-ratio calibrating circuit have employed closed loop. But there is following a few point defect in this scheme:
1) this scheme is passed through ring oscillator and the electric charge pump CP2 of three grades of phase inverters composition and fills Electricity electric capacity C2 produces the reference voltage representing 50% dutycycle, reference voltage one side that this method produces Face circuit is complicated, and ring oscillator must be by careful design its upper and lower PMOS, NMOS Reasonable size, it is ensured that obtaining a dutycycle is the clock of 50%, and this is by technique, temperature etc. Impact can be relatively big, directly affects dutycycle Adjustment precision.
2) this ring oscillator will consume the biggest power consumption under high frequency condition.
3) in the locked state, VrefJointly determined by the charge and discharge stream of CP2 and the output impedance of current source Fixed, when there is mismatch in electric charge pump CP2, VrefMay be by by reed position to power supply or ground, then loop will not Can normally work;Additionally this structure can only carry out the adjustment of 50% dutycycle.
4) overal system design is complicated, has two electric charge pumps (CP1/CP2), and comparator has three Integrating capacitor, will take bigger chip area.
Prior art additionally provides the duty-ratio calibrating circuit that a kind of totally digital circuit realizes, concrete such as Fig. 2 Shown in:
Use digital open loop its Thoughts of formula duty-ratio calibrating circuit substantially: input clock ClkinBy prolonging Link (being formed by the delay cell cascade that several retardations are t), generates a series of equiphase poor late Signal Clk [i], Clk [i] rising edge excitation trigger is to ClkinSample, permissible by combination logic Judge ClkinTrailing edge is relative to the position of delay chain, and concrete signal intensity is as shown in Figure 3.Example As trigger from left to right sampled result is followed successively by 11111111110000, then ClkinTrailing edge is positioned at 1 Between the two-stage delayed clock of 0, now will be with ClkinThe corresponding delayed clock in trailing edge position (as Clk [n+1] in Fig. 3) negate, the most respectively to ClkinWith/the rising edge of Clk [n+1], trailing edge Carry out inserting phase, it is assumed that the most slotting phase process makes the clock inserted out edge be exactly in two centres by slotting edge, Then the final clock duty cycle obtained will be 50%.
This class formation itself have employed open loop form, and it sets up speed quickly, but in this class technology Have the disadvantage that
1) insert the relative size that phase position depends on phase inverter A, B, easily affected by process deviation;
2) affected by technique, temperature, voltage etc. between each delay unit and be there are differences, it is difficult to ensure that The concordance of delay time, thus greatly have impact on dutycycle calibration accuracy.
3) insert phase process only to carry out in clock limited rise or fall time, thus greatly limit Its adjustable frequency and dutycycle, adjustable duty cycle scope is only ± 10%, greatly limit practicality.
Summary of the invention
It is an object of the invention to provide a kind of clock duty cycle calibration circuit so that circuit structure is simple, Chip occupying area is less, and the dutycycle precision of output clock signal is greatly improved, and improves calibration The anti-integrated circuit technology of circuit, temperature, the impact of change in voltage.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of clock duty cycle calibration electricity Road, including:
Pulse generator, pulse width modulator, trigger, comparator and low pass filter;
Pulse generator, inputs the first clock signal, exports second clock signal;Second clock signal Dutycycle is less than 50%;
Pulse width modulator, input second clock signal and feedback signal, export the 3rd clock signal;
Trigger, inputs the 3rd clock signal, output calibration clock signal;
Low pass filter, input calibration clock signal, export the 4th clock signal;
Comparator, anode input the 4th clock signal, negative terminal input reference voltage, output feedback signal.
In terms of existing technologies, pulse generator is for defeated with any dutycycle for embodiment of the present invention The clock signal entered, the output duty cycle clock signal less than 50%, input the clock letter of this calibration circuit Number dutycycle be arbitrarily, variable-size numerical value.Pulse width modulator to input clock signal and feedback Signal carries out pulse-width regulated, owing to signal is constantly fed back to an input of pulse width modulator, by This, input signal is just carried out constantly pulse-width regulated.And pulse width modulator, trigger, low pass filtered Ripple device and comparator collectively form a closed loop circuit, and the structure comparison of closed loop circuit is stable, Lao Gu, no It is easily subject to the signal disturbing in the external world, therefore there is stronger robustness, and closed loop can be carried out Continuous print is calibrated so that the constantly pwm clock signal of regulation input, approaches the feedback letter of comparator output Number, until equilibrium establishment state, calibration accuracy is improved constantly.Low pass filter will be above cutoff frequency The filtered clock signal of rate, reduces output clock signal, reduces the amplitude of output signal, reduces high frequency letter Number interference.Even if the clock letter of the dutycycle of embodiment of the present invention alignment circuit input arbitrary size Number, the clock signal of output also can be calibrated to predetermined dutycycle, and calibration accuracy is greatly improved, Circuit decreases the interference of sudden change high-frequency signal simultaneously, has stronger robustness, meanwhile, anti-integrated electricity Road technique, temperature, the impact of change in voltage have also been obtained raising.
It addition, in pulse generator, specifically include: delay unit and NAND gate;The first of NAND gate is defeated Entering the input that end is pulse generator, the second input is defeated by the first of delay unit connection NAND gate Entering end, the outfan of NAND gate is as the outfan of pulse generator;The delay time of delay unit is less than The 1/2 of the cycle of the first clock signal.According to the computing formula of dutycycle, when dutycycle is signal pulse Between divided by cycle of this signal, delay unit delay time less than the first clock signal cycle 1/2, I.e. through a series of logical operationss such as NAND gate, the burst length is less than 1/2 divided by the cycle of this signal, Produce the dutycycle signal less than 50%.Pulse generator includes delay unit and NAND gate, time delay The version that unit and NAND gate composition are fixed, the duty cycle signals needed for generation, simple in construction, real Existing property is good.
It addition, the second input of NAND gate connects delay unit by least one first phase inverter.Prolong Shi Danyuan can have repeatedly operated in anti-phase after carrying out signal lag, and phase inverter can be strengthened as buffer The driving force of circuit.
It addition, trigger is Schmidt trigger.Schmidt trigger improves pulse width modulator output letter Number capacity of resisting disturbance, enhance the antinoise of signal and the ability of shake, and strengthen pulsewidth modulation Device driving force.
It addition, low pass filter is resistance capacitance RC wave filter.RC wave filter is by the signal of prominent high-amplitude Cut-off, by the signal that amplitude is less, and RC filter construction is simple.
It addition, reference voltage is obtained according to the first resistance and the second electric resistance partial pressure by running voltage;First electricity One end of resistance connects the negative terminal of comparator, other end ground connection;One end of second resistance connects the negative of comparator End, the other end connects running voltage.Feedback signal is obtained with electric resistance partial pressure by low-pass filter output signal Reference voltage compared by ultramagnifier, result of the comparison feeds back to carry out in pulse width modulator pulsewidth Regulation, the reference voltage that electric resistance partial pressure obtains finally determines the dutycycle after pulsewidth modulation, difference to be produced The dutycycle output signal of value size is it is necessary to adjust the magnitude of voltage of reference voltage, and the value of running voltage is solid Fixed immutable, two electric resistance partial pressures obtain a fixing reference voltage level.
It addition, the second resistance is variable resistance.By regulation variable resistance resistance size, change resistance and divide The size of the value of pressure, i.e. the magnitude of voltage size of reference voltage so that dutycycle is adjustable, so that output The dutycycle of signal can adjust needed for user, expands the range of application of the present invention.
Accompanying drawing explanation
Fig. 1 is according to a kind of pulsewidth under high-speed cmos clock buffer in background of invention Control the circuit diagram of cycling circuit;
Fig. 2 is the duty-ratio calibrating circuit realized according to a kind of totally digital circuit in background of invention Circuit diagram;
Fig. 3 is the duty-ratio calibrating circuit realized according to a kind of totally digital circuit in background of invention Signal graph;
Fig. 4 is the circuit module of a kind of clock duty cycle calibration circuit according to first embodiment of the invention Figure;
Fig. 5 is the circuit diagram of a kind of clock duty cycle calibration circuit according to first embodiment of the invention;
Fig. 6 is a kind of pulse generator signal variation diagram according to first embodiment of the invention;
Fig. 7 is the circuit structure diagram of a kind of Schmidt trigger according to first embodiment of the invention;
Fig. 8 is the reference voltage that the fixed resistance value electric resistance partial pressure method according to second embodiment of the invention obtains Circuit structure diagram;
Fig. 9 is the reference voltage that a kind of adjustable resistance dividing potential drop according to third embodiment of the invention obtains Circuit structure diagram;
Figure 10 is the connection circuit diagram of a kind of phase inverter according to four embodiment of the invention;
Figure 11 is the circuit structure diagram of a kind of trigger according to fifth embodiment of the invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this Bright each embodiment is explained in detail.But, it will be understood by those skilled in the art that In each embodiment of the present invention, propose many technology to make reader be more fully understood that the application thin Joint.But, even if there is no these ins and outs and many variations based on following embodiment and amendment, The application each claim technical scheme required for protection can also be realized.
First embodiment of the present invention relates to a kind of clock duty cycle calibration circuit.Circuit module figure such as figure Shown in 4, specifically include: pulse generator, pulse width modulator, trigger, comparator and low-pass filtering Device;Pulse generator, inputs the first clock signal clk _ in, exports second clock signal CLK_2; The dutycycle of second clock signal CLK_2 is less than 50%;Pulse width modulator, inputs second clock signal CLK_2 and feedback signal, export the 3rd clock signal;Trigger, inputs the 3rd clock signal, output Calibration clock signal;Low pass filter, inputs described calibration clock signal, exports the 4th clock signal; Comparator, anode input the 4th clock signal, negative terminal input reference voltage, output feedback signal.Wherein, Output signal calibrates signal exactly.
Specifically, by the peculiar structure within pulse generator, it is possible to achieve different functions, from And limit the characteristic of the signal of this pulse generating signal device output.Pulse generation letter in present embodiment Number for the clock signal clk _ in of any dutycycle size of input, always produce a dutycycle and be less than Clock signal clk _ 2 of 50%, and in this, as unique input signal of next device, it is ensured that appoint Input signal CLK_in of meaning dutyfactor value size for the result of this calibration circuit be do not have influential.
It is noted that the pulse generator in present embodiment, as it is shown in figure 5, specifically include: Delay unit 1 and NAND gate 3;The first input end of NAND gate 3 is the input of pulse generator, the Two inputs connect the first input end of NAND gate 3 by delay unit 1, and the outfan of NAND gate 3 is made Outfan for pulse generator;The delay time of delay unit 1 is less than the cycle of the first clock signal 1/2, and the second input of NAND gate 3 connects delay unit 1 by least one first phase inverter 2.
Wherein, it will be understood by those skilled in the art that delay unit 1 be by input signal CLK_in by The translation of time-axis direction is carried out, the signal period after time delay, frequency, duty according to certain delay time The character such as ratio, all without changing, are simply translated on time orientation.NAND gate 3 is one A kind of logic circuit of digital circuit, first carries out AND operation to the signal CKL_1 of input, then carries out NOT operation, if two inputs such as working as NAND gate 3 are all high level (representing with current potential " 1 "), Then input is low level (representing with " 0 ");If the two of input input signals at least one be low Level (0), then be output as high level (1).
Delay unit 1 is for producing less shift signal, as an input signal of NAND gate 3 CKL_1, NAND gate 3 by signal that delay cell 1 is produced and input signal CLK_in carry out with Alogical computing, the result finally given is clock signal clk _ 2 that dutycycle is less than 50%, such as figure Shown in 6, give a kind of pulse generator signal variation diagram of present embodiment.
According to the computing formula of dutycycle, it is known that dutycycle is that the signal pulse time is divided by this signal Cycle, delay unit 1 delay time less than the first clock signal cycle 1/2, i.e. through with non- A series of logical operations such as door 3 etc., the burst length, thus, produces less than 1/2 divided by cycle of this signal The raw dutycycle signal less than 50%.The version that delay unit 1 and NAND gate 3 composition are fixed, Duty cycle signals needed for generation, simple in construction, it is achieved property is good.
It addition, the second input of NAND gate 3 can be connected by a phase inverter 2 in present embodiment Delay unit 1, this phase inverter 2 can be as the buffer of circuit, the driving force of accentuator.This Outward, in actual applications, the second input of NAND gate 3 can connect time delay list by multiple phase inverters Unit, such as 2 or 3, will not enumerate at this.
It should be noted that, pulse width modulator is the instrument of a kind of controlling party pulse width, can be effectively The width of regulation square-wave signal, and then control the size of the dutyfactor value of square wave.Pulse width modulator is with arteries and veins Rush the dutycycle of the generator output end clock output signal CLK_2 less than 50% as an input, Input using a feedback signal as another, owing to the value of feedback signal is constantly updated, inputs extremely This pulse width modulator, therefore, the pulsewidth of two input signals of input is constantly compared, is adjusted Joint.
Pulse width modulator in present embodiment is pseudo-phase inverter, including: the first P-channel metal-oxide Semiconductor field effect transistor PMOS 4 and the first N-channel metal oxide semiconductor field effect transistor Pipe NMOS tube 5;The drain electrode of the first PMOS 4 connects high level, and grid connects the outfan of comparator, Source electrode connects the drain electrode of the first NMOS tube 5;The source ground of the first NMOS tube 5, grid connects pulse The outfan of generator.
Specifically, two inputs of this puppet phase inverter pulse width modulator connect pulse generator respectively Outfan and the outfan of comparator, i.e. feedback signal, owing to the signal value of feedback is continually changing, therefore This puppet phase inverter pulse width modulator can constantly carry out the modulation of pulsewidth to the two of input signal, until Till reaching dynamic poised state, the pwm value of two input signals now has also reached to approach the most State, calibration circuit obtained a higher output signal of precision.
Owing to, in actual digital display circuit, comprising substantial amounts of memory element, be triggered when control signal or The signal of person's input reaches the condition of certain threshold value, and circuit changes corresponding output signal according to input signal State, this needs trigger storage element be just called trigger.Trigger in present embodiment Input signal is the output signal of pulse width modulator, itself and pulse width modulator " end to end ".According to this Structure within trigger or control condition and input signal, produce and export clock signal accordingly, Specifically, output clock signal calibrates signal exactly.
It is noted that the trigger in present embodiment is Schmidt trigger 6, as it is shown in fig. 7, Including: three PMOS and three NMOS tube, be the second PMOS the 10, the 3rd PMOS respectively Pipe the 11, the 4th PMOS the 15, second NMOS tube the 12, the 3rd NMOS tube 13 and the 4th NMOS Pipe 14;Second PMOS the 10, the 3rd PMOS the 11, second NMOS tube 12 and the 3rd NMOS The grid of pipe 13 connects jointly, as the input of Schmidt trigger;The leakage of the second PMOS 10 The source electrode of pole and the 3rd PMOS 11 is commonly connected to the drain electrode of the 4th NMOS tube 14;2nd NMOS The drain electrode of pipe 12 and the source electrode of the 3rd NMOS tube 13 are commonly connected to the drain electrode of the 4th PMOS 15; The source ground of the 4th NMOS tube 14, the drain electrode of the 4th PMOS 15 connects high level;3rd PMOS The source electrode of pipe 11 and the drain electrode of the second NMOS tube 12, the grid and the 4th of the 4th PMOS 15 The grid of NMOS tube 14 connects jointly, as the outfan of Schmidt trigger 6.
Gate circuit has a threshold voltage, when input voltage rises to threshold voltage or from high electricity from low level Equal the state of circuit when dropping to threshold voltage will change.Schmidt trigger is a kind of special door Circuit, different from common gate circuit, Schmidt trigger has two threshold voltages, is called forward Threshold voltage (V+) and negative sense threshold voltage (V-).High level is risen to from low level in input signal And when arriving V+, output voltage state is undergone mutation;Input signal drops to low level also from high level And when being reduced to V-, output voltage state is undergone mutation.
Schmidt trigger be designed to stop input voltage that minor variations (less than a certain threshold value) occurs and The change of the output voltage caused, improves the anti-noise ability of Schmidt trigger output signal, and utilizes Positive feedback effect in Schmidt trigger state conversion process, can edge change slowly periodically Signal is transformed to the rectangular pulse signal that edge is the steepest.Output signal through pulse width modulator may be sent out Raw signal waveform distortion, the rising edge of waveform substantially slows down, or when other pulse signals are by the square that is added to During shaped pulse signal, signal will appear from the noise added, no matter occur above-mentioned in which kind of situation, all Can be by obtaining more satisfactory rectangular pulse waveform with Schmidt's inverter trigger shaping.
Low pass filter is a kind of instrument playing trap signal effect, it is allowed to less than a certain specific cutoff frequency The signal of rate passes through, but then can not pass through higher than the signal of this particular cut-off frequency.Due to low pass filter High-frequency signal there is inhibitory action, so being frequently utilized for filtering the interference signal of high frequency.In present embodiment Low pass filter connect trigger, with the output signal of trigger, namely calibrate signal, as from The input signal of body, in trigger output signal in high-frequency interferencing signal, filter, The anti-high-frequency signal interference performance of this calibration circuit can be improved.
It is noted that the low pass filter in present embodiment is resistance capacitance RC wave filter.By It is the more commonly used low pass filter in RC wave filter, and the structure of RC wave filter is very simple, Have only to use a resistance R7, a capacity cell C8, thus reduce whole calibration circuit structure Complexity, and reduce the area occupied of circuit chip.Further, RC wave filter can reduce The sawtooth waveforms of input, reduces the amplitude of input sawtooth waveforms.In actual applications, low pass filter is all right It is Butterworth filter or Chebyshev filter etc..
Two or more data can be compared by comparator, the most equal to determine their size, Or determine the magnitude relationship between them.Comparator 9 in present embodiment has two inputs, One input connects the outfan of low pass filter, believes using the output signal of low pass filter as input Number, another input one reference voltage vref of input, this reference voltage vref can be by technical staff Empirically arrange.The result of this comparator 9, as a feedback signal, inputs pulse width modulator, One of them input signal as pulse width modulator.
Present embodiment compared with prior art, main is improved and effect is, pulse width modulator, touches Send out device, RC low pass filter and comparator the most end to end, together constitute the ring of a Guan Bi Road, in loop, each output signal is using as the input signal of next components and parts or one of them input Signal.When the circuit technology that exists between each components and parts in Guan Bi circuit, temperature, voltage etc. affect one Sample, owing to closing this special structure of circuit, determine the anti-integrated circuit work of its whole circuit Skill, temperature, the impact of change in voltage are improved.And the structure comparison closing circuit is stable, firm Gu, it is not easy to disturbed by factors such as extraneous signals, thus there is stronger robustness.Guan Bi circuit Feedback signal, by contrast clock signal and the signal of reference, is constantly input to pulse-width modulator by comparator In be adjusted, until establishing poised state, the pwm input signal under poised state is closest to instead Feedback signal, is ensured that the precision of circuit is constantly improved.
Second embodiment of the present invention relates to a kind of clock duty cycle calibration circuit, and the second embodiment is The improvement done on the first embodiment, it mainly thes improvement is that: in this second embodiment, Reference voltage vref is obtained according to the first resistance 16 and the second resistance 17 dividing potential drop by running voltage;First electricity One end of resistance 16 connects the negative terminal of comparator, other end ground connection;One end of second resistance 17 connects and compares The negative terminal of device, the other end connects running voltage;First resistance 16 and the second resistance 17 are fixed resistance value Resistance, the most as shown in Figure 8.
Specifically, present embodiment is obtained with electric resistance partial pressure by the filtered output signal of low pass filter To reference voltage vref compare in a comparator.Result of the comparison feeds back in pulse-width modulation circuit Carrying out pulse-width regulated, therefore, the dutycycle after final pulsewidth modulation is the reference electricity obtained by electric resistance partial pressure Pressure vref determines, and reference voltage vref can be by running voltage VDD according to the first resistance R116 With the second resistance R217 dividing potential drops obtain, and the reference voltage vref obtained is according to the first resistance R116 and Two resistance R2The resistance pro rate of 17 gets.Such as, dutycycle to be obtained be 25% clock signal defeated Go out, then can use R1=40K Ω, R2=120K Ω, can obtain R1/(R1+R2) =40K/ (40K+120K)=0.25, the dutycycle that may finally obtain output signal is 25%.
According to the output signal that dutycycle to be obtained is different, the electricity of different resistance can be selected accordingly Resistance, thus obtain any dutycycle and be worth signal.
Third embodiment of the invention relates to a kind of clock duty cycle calibration circuit, and the 3rd embodiment is right The optimization of the second embodiment, is in place of main optimization: in third embodiment of the invention, reference Voltage vref is according to the 4th resistance R418 and the 3rd resistance R3The dividing potential drop of 19 obtains, as it is shown in figure 9, the Four resistance R4One end of 18 connects the negative terminal of comparator, other end ground connection;3rd resistance R3One end of 19 Connecting the negative terminal of comparator, the other end connects running voltage;3rd resistance R319 is variable resistance.
Specifically, present embodiment passes through the 4th resistance R418 and the 3rd resistance R319 dividing potential drops obtain ginseng Examining voltage vref and be input to the input negative terminal of comparator components and parts, this reference voltage level vref will determine Dutycycle after final output pwm clock signal modulation.Such as, our dutycycle to be realized is 50% (1:2) clock signal output, then we can use R3=40K Ω, R4=40K Ω, can obtain To R4/(R3+R4)=40K/ (40K+40K)=0.5, then reference voltage vref is 1/2VDD, then filter Sawtooth waveforms and 1/2VDD after ripple compare, square-wave signal putting down by the filtered sawtooth waveforms of RC Average is Vav=VDD* dutycycle, is so constantly compared by closed-loop and approaches so that filter Mean voltage Vav after ripple is constantly close to 1/2VDD, finally when VDD* dutycycle=1/2VDD Equilibrium establishment state so that the dutycycle of output signal is 50%.Equally, if we want to realize duty Ratio is 75% (3:4), and so I can use R3=40K/3, R4=40K, i.e. R4/(R3+R4) =40K/ (40K/3+40K)=0.75, repeats the Signal approximation of closed-loop, may finally be exported The dutycycle of signal is 75%.
Due to the 3rd resistance R319 is variable resistance, can be by regulation variable resistance R3, the i.e. the 3rd electricity The size of resistance 19, and the resistance replacing different resistance size that need not be manual so that change electric resistance partial pressure Value R4/(R3+R4) size, thus obtain any dutycycle calibration output signal, accounting for of output signal Empty ratio can expand the range of application of the present invention according to adjusting needed for user.
Four embodiment of the invention relates to a kind of clock duty cycle calibration circuit, the 4th embodiment be The improvement done on first embodiment, mainly thes improvement is that: in four embodiment of the invention, The second phase inverter 20 is connected between pulse generator and pulse width modulator, and between trigger and wave filter Connect the 3rd phase inverter 21, as shown in Figure 10:
Specifically, phase inverter joins between pulse generator and pulse width modulator and trigger and filtering Between device, not do not change original attribute of clock signal, such can by the buffer as circuit, The driving force of accentuator.
It is noted that in actual applications, except the both connections second mentioned in present embodiment are anti- Phase device 20, connects again the 3rd phase inverter 21, it is also possible to be only connected the 3rd between trigger with wave filter anti- Phase device 21;Or between pulse generator and pulse width modulator, only connect the second phase inverter 20.
Fifth embodiment of the invention relates to a kind of clock duty cycle calibration circuit, the 5th embodiment and the One embodiment is roughly the same, is in place of the main distinction: in fifth embodiment of the invention, triggers The structure of device is different with the structure of trigger in the first embodiment, as shown in figure 11, including a voltage Source 22, a comparator 23, one the 5th resistance 24 and the 6th resistance 25.
Specifically, voltage source 22 produces the magnitude of voltage V of fixed sizeI, and this constant voltage values VI It is input to comparator 23 input negative terminal, the 5th resistance R624 and the 6th resistance R525 pairs of comparators 23 Output end voltage carry out dividing potential drop, wherein the 6th resistance R5The branch pressure voltage value of 25 will be as feedback voltage level Returning to the input anode of comparator 23, feedback voltage computing formula is [R5/(R5+R6)]*Vo.Thus, Comparator has 1 magnitude of voltage VIThreshold restriction, if feedback voltage level is more than fixed size magnitude of voltage VI, Then output current potential is " 1 ";If feedback voltage level is less than fixed size magnitude of voltage VI, then output current potential is “0”.Thus, it is possible to realize the output of rectangular pulse waveform, and reduce and produce because of signal disturbing Wrong square wave output.
It is noted that in actual applications, trigger except using the structure in the first embodiment, With the structure in present embodiment, it is also possible to use the Schmidt trigger of other structures, the most another at this One enumerates.
It will be understood by those skilled in the art that the respective embodiments described above are realize the present invention concrete Embodiment, and in actual applications, can to it, various changes can be made in the form and details, and the most inclined From the spirit and scope of the present invention.

Claims (10)

1. a clock duty cycle calibration circuit, it is characterised in that including: pulse generator, pulsewidth Manipulator, trigger, comparator and low pass filter;
Described pulse generator, inputs the first clock signal, exports second clock signal;When described second The dutycycle of clock signal is less than 50%;
Described pulse width modulator, inputs described second clock signal and feedback signal, output the 3rd clock letter Number;
Described trigger, inputs described 3rd clock signal, output calibration clock signal;
Described low pass filter, inputs described calibration clock signal, exports the 4th clock signal;
Described comparator, anode inputs described 4th clock signal, negative terminal input reference voltage, exports institute State feedback signal.
Clock duty cycle calibration circuit the most according to claim 1, it is characterised in that described arteries and veins Rush in generator, specifically include: delay unit and NAND gate;
The first input end of described NAND gate is the input of described pulse generator, and the second input passes through Described delay unit connects the first input end of described NAND gate, and the outfan of described NAND gate is as described The outfan of pulse generator;
The delay time of described delay unit is less than the 1/2 of the cycle of described first clock signal.
Clock duty cycle calibration circuit the most according to claim 2, it is characterised in that described with Second input of not gate connects described delay unit by least one first phase inverter.
Clock duty cycle calibration circuit the most according to claim 1, it is characterised in that described arteries and veins Wide manipulator is pseudo-phase inverter.
Clock duty cycle calibration circuit the most according to claim 4, it is characterised in that described arteries and veins Wide manipulator specifically includes: the first P-channel metal-oxide-semiconductor field-effect transistor PMOS With the first n channel metal oxide semiconductor field effect transistor NMOS tube;
The drain electrode of described first PMOS connects high level, and grid connects the outfan of described comparator, source Pole connects the drain electrode of described first NMOS tube;The source ground of described first NMOS tube, grid meets institute State the outfan of pulse generator.
Clock duty cycle calibration circuit the most according to claim 1, it is characterised in that described tactile Sending out device is Schmidt trigger.
Clock duty cycle calibration circuit the most according to claim 6, it is characterised in that described in execute Schmitt trigger specifically includes: three PMOS and three NMOS tube, be the 2nd PMOS respectively Pipe, the 3rd PMOS, the 4th PMOS, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube;
Described second PMOS, the 3rd PMOS, the second NMOS tube and the 3rd NMOS tube Grid connects jointly, as the input of described Schmidt trigger;
The drain electrode of described second PMOS and the source electrode of the 3rd PMOS are commonly connected to the described 4th The drain electrode of NMOS tube;The drain electrode of described second NMOS tube and the source electrode of the 3rd NMOS tube connect jointly It is connected to the drain electrode of described 4th PMOS;The source ground of described 4th NMOS tube, the described 4th The drain electrode of PMOS connects high level;
The source electrode of described 3rd PMOS and the drain electrode of described second NMOS tube, described 4th PMOS The grid of pipe and the grid of described 4th NMOS tube connect, jointly as described Schmidt trigger Outfan.
Clock duty cycle calibration circuit the most according to claim 1, it is characterised in that described low Bandpass filter is resistance capacitance RC wave filter.
Clock duty cycle calibration circuit the most as claimed in any of claims 1 to 8, it is special Levying and be, described reference voltage is obtained according to the first resistance and the second electric resistance partial pressure by running voltage;
One end of described first resistance connects the negative terminal of described comparator, other end ground connection;
One end of described second resistance connects the negative terminal of described comparator, and the other end connects running voltage.
Clock duty cycle calibration circuit the most according to claim 9, it is characterised in that described Two resistance are variable resistance.
CN201610388948.8A 2016-06-02 2016-06-02 Clock duty ratio calibration circuit Pending CN105958971A (en)

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CN109039312A (en) * 2018-08-01 2018-12-18 电子科技大学 Mixed type digital pulse-width modulator with delay chain optimization function
CN109039312B (en) * 2018-08-01 2020-03-17 电子科技大学 Hybrid digital pulse width modulator with delay chain optimization function
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Application publication date: 20160921