CN107395166A - Clock duty cycle stabilizing circuit based on delay lock phase - Google Patents

Clock duty cycle stabilizing circuit based on delay lock phase Download PDF

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Publication number
CN107395166A
CN107395166A CN201710587389.8A CN201710587389A CN107395166A CN 107395166 A CN107395166 A CN 107395166A CN 201710587389 A CN201710587389 A CN 201710587389A CN 107395166 A CN107395166 A CN 107395166A
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China
Prior art keywords
input
nmos tube
output
grid
delay
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CN201710587389.8A
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CN107395166B (en
Inventor
郭亮
雷郎成
苏晨
刘凡
曾涛
刘伦才
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CETC 24 Research Institute
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CETC 24 Research Institute
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter

Abstract

The present invention provides a kind of clock duty cycle stabilizing circuit based on delay lock phase, including:Delay cell, it is connected with clock signal input terminal, for carrying out phase delay to clock input signal;The output end connection of ALU, its input and delay cell, for carrying out phase-detection to the signal of phase delay;The output end connection of charge pump, its input and ALU, for producing the voltage signal associated with phase difference;Voltage controlled delay line unit, for adjusting phase;Output buffer, its input is connected with the output end of voltage controlled delay line unit, for exporting clock signal;Circuit structure of the present invention is simple, has the advantages that simple in construction, clock signal jitter is small, it is fast to establish speed and balanced duty, meets the needs of products such as high speed data converter, solves the problems, such as to influence dynamic property in the case that clock signal is second-rate.

Description

Clock duty cycle stabilizing circuit based on delay lock phase
Technical field
The present invention relates to IC design field, more particularly to a kind of stable electricity of clock duty cycle based on delay lock phase Road.
Background technology
For the state in decision logic unit when more clock signal (Clock Signal) is the basis of sequential logic, Newly, it is to have fixed cycle and the semaphore unrelated with operation, with high speed data converter and nanoscale SOC development, urgently High-frequency, the clock of low jitter are needed, because one of the key modular unit of clock as system, greatly constrains entirety The raising of performance, in order to ensure that system has sufficient settling time and retention time, while reduce the factors pair such as phase noise The influence of system is, it is necessary to use clock duty cycle stabilizing circuit to produce dutycycle as 50% clock signal.
At present, the conventional art of clock duty cycle stabilizing circuit is realized, mainly includes continuous time Integral Technology and lock phase Loop technique, the two is to adjust phase by backfeed loop, realizes low-jitter clock signal.But all there is this in prior art Deficiency, wherein clock signal phase precision depends critically upon caused by the Clock duty cycle stabilizer based on continuous time Integral Technology Integrator, flow-route and temperature deviation can directly affect clock performance, and the usual phase of Clock duty cycle stabilizer based on PHASE-LOCKED LOOP PLL TECHNIQUE Position noise is larger, and settling time is slow, therefore, it is necessary to study a kind of new clock duty cycle stabilizing circuit, it is existing to overcome The problem of clock signal jitter is big, dutycycle is unstable and settling time is slow.
The content of the invention
In view of the above the shortcomings that prior art, it is stable that the present invention provides a kind of clock duty cycle based on delay lock phase Circuit, to solve above-mentioned technical problem.
Clock duty cycle stabilizing circuit provided by the invention based on delay lock phase, including:
Delay cell, it is connected with clock signal input terminal, for carrying out phase delay to clock input signal;
The output end connection of ALU, its input and delay cell, for the signal progress to phase delay Phase-detection;
The output end connection of charge pump, its input and ALU, for producing the voltage associated with phase difference Signal;
Voltage controlled delay line unit, for adjusting phase;
Output buffer, the output end connection of its input voltage controlled delay line unit, for exporting clock signal.
Further, filter circuit, for filtering out the high-frequency signal in the voltage signal;
Biasing circuit, for providing bias voltage for charge pump and voltage controlled delay line unit.
Further, the delay cell includes the first delay cell and the second delay cell, the ALU bag Include the first ALU, the second ALU and the 3rd ALU, first ALU and Second ALU is and logic unit, and the 3rd ALU is or logic unit;
The input of first delay cell and the second delay cell input are connected with clock signal input terminal respectively, The output end of first delay cell is connected with the second input of the first ALU, the output end of the second delay cell with The second input connection of second ALU, the first input end of first ALU and the second logic are transported The first input end connection of unit is calculated, the output end of the first ALU connects with the first input end of voltage controlled delay line unit Connect, the output end of the second ALU is connected with the first input end of the 3rd ALU, the 3rd logical operation list The output end of member is connected with the first input end of charge pump unit and the input of output buffer respectively.
Further, the input of the output end of the charge pump unit and filter unit connects, the output end of filter unit It is connected with the second input of voltage controlled delay line unit, the first output end of bigoted circuit and the 3rd input of voltage controlled delay line Connection, the second output port of biasing circuit and the second input of charge pump unit connect.
Further, first delay cell carries out odd-times phase delay, second delay cell to clock signal Even-times phase delay is carried out to clock signal,.
Further, the voltage controlled delay line unit includes the voltage controlled delay line subelement of even number cascade, in voltage Control is lower to carry out phase delay, the voltage controlled delay line subelement include the first phase inverter, the first NMOS tube, the second NMOS tube, 3rd NMOS tube and the first PMOS, the input of first phase inverter are the input of voltage controlled delay line, and described first is anti- The output end of phase device is connected with the grid of PMOS and the grid of the first NMOS tube respectively, the source electrode and power line of the first PMOS Connection, the drain electrode of the first PMOS is with the drain electrode connection of the first NMOS tube and as the output port of voltage controlled delay line, and second The source electrode of the drain electrode of NMOS tube and the drain electrode of the 3rd NMOS tube respectively with the first NMOS tube is connected, the grid of the second NMOS tube and filter Wave circuit is connected, and the grid of the 3rd NMOS tube is connected with the output end of biasing circuit first, the source electrode of the second NMOS tube and the 3rd The source electrode of NMOS tube is connected with ground wire respectively;By controlling the grid voltage of the second NMOS tube and the 3rd metal-oxide-semiconductor, regulation input letter Number rising and falling time.
Further, the charge pump includes the second phase inverter, the 3rd phase inverter, operational amplifier, the 4th NMOS tube, second PMOS, the first transmission gate, the second transmission gate, the 3rd transmission gate, the 4th transmission gate and the 5th transmission gate, the 3rd logic fortune The output end for calculating unit is connected with the input of the second phase inverter, and the output end of the second phase inverter is defeated with the 3rd phase inverter respectively Enter end to connect with the input of the first transmission gate, the output end of the 3rd phase inverter respectively the grid negative terminal mouth with the second transmission gate, The positive port of grid, the positive port of grid of the 4th transmission gate of 3rd transmission gate connect with the grid negative terminal of the 5th transmission gate, and first The output end of the transmission gate positive port of grid with the second transmission gate, grid negative terminal mouth, the 4th transmission gate of the 3rd transmission gate respectively Grid negative terminal mouth, the connection of the grid of the 5th transmission gate positive port, the grid negative terminal mouth of first transmission gate is connected with ground wire, The positive port of grid of first transmission gate is connected with power line, the second transmission gate input respectively with the input of the 4th transmission gate and The drain electrode connection of second PMOS, the output end of the second transmission gate input with the 3rd transmission gate, operational amplifier respectively Output end connects with the input negative terminal mouth of operational amplifier, the output end input with the 5th transmission gate respectively of the 4th transmission gate End, the input positive terminal of operational amplifier are connected with filter circuit input, and the output end of the 3rd transmission gate is transmitted with the 5th respectively The drain electrode of the output end and the 4th NMOS tube of door connects, and the source electrode of the second PMOS connects power line, and the source electrode of the 4th NMOS tube connects The grid of ground wire, the grid of the second PMOS and the 4th NMOS tube is connected with biasing circuit respectively.
Further, the operational amplifier includes the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 3rd PMOS With the 4th PMOS, the drain electrode of the source electrode of the 5th NMOS tube respectively with the source electrode and the 7th NMOS tube of the 6th NMOS tube is connected, and The grid of five NMOS tubes is the positive port of operational amplifier, and the grid of the 6th NMOS tube is the negative terminal mouth of operational amplifier, the 5th The drain electrode of NMOS tube is connected with the grid of the 3rd PMOS and drain electrode, the grid of the 4th PMOS respectively, the leakage of the 6th NMOS tube Pole is connected with the drain electrode of the 4th PMOS, and the source electrode of the 3rd PMOS is connected with power line respectively with the source electrode of the 4th PMOS, The source electrode connection ground wire of 7th NMOS tube, the grid of the 7th NMOS tube are connected with biasing circuit.
Further, the biasing circuit includes the first current source, the second current source, the 3rd current source, the 4th current source, the Eight NMOS tubes, the 9th NMOS tube, the tenth NMOS tube and the 5th PMOS, the positive port of the first current source respectively with the 5th PMOS Grid and drain electrode connect, and provide bias voltage for charge pump, the negative terminal mouth of the first current source is grounded, the 5th PMOS Source electrode connects power line, and the positive port of the second current source is connected with power line, the negative terminal mouth of the second current source respectively with the 8th NMOS The grid of pipe and drain electrode connect, and provide bias voltage for charge pump, and the source electrode of the 8th NMOS tube is connected with ground wire, the 3rd electricity The positive port in stream source is connected with power line, and the negative terminal mouth of the 3rd current source connects with the grid of the 9th NMOS tube and drain electrode respectively, And bias voltage is provided for the amplifier in charge pump, the source electrode of the 9th NMOS tube is connected with ground wire, the positive port of the 4th current source It is connected with power line, the negative terminal mouth of the 4th current source connects with the grid of the tenth NMOS tube and drain electrode respectively, and is voltage-controlled delay Line unit provides bias voltage, and the source electrode of the tenth NMOS tube is connected with ground wire.
Further, the output buffer includes the phase inverter of even number cascade.
Further, the filter circuit is low-pass filter circuit, the low pass circuit include the first electric capacity, the second electric capacity and Resistance, the controversial issue mouth of first electric capacity as filter circuit input port and be connected with the positive port of resistance, the first electric capacity Negative terminal mouth be connected with the negative terminal mouth of the second electric capacity and be connected respectively with ground wire, the negative terminal mouth of the second electric capacity is as the defeated of filter circuit Exit port is simultaneously connected with the negative terminal mouth of resistance.
Beneficial effects of the present invention:The clock duty cycle stabilizing circuit based on delay lock phase in the present invention, in of the invention Circuit structure is simple, directly produces phase difference using delay cell and by arithmetic logic, delay lock phase velocity is fast;Through oversampling clock Stable duty ratio circuit clock signal duty cycle automatic equalization regulation, the present invention have it is simple in construction, clock signal jitter is small, The advantages that establishing fast speed and balanced duty, meets the needs of products such as high speed data converter, solves clock signal matter Measure it is poor in the case of the problem of being influenceed on dynamic property, ensure that chip is worked with optimal stable performance, at a high speed The development of data converter and nanoscale SOC provides the foundation.
Brief description of the drawings
Fig. 1 is the structural representation of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention.
Fig. 2 is the knot of the first delay cell of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Structure schematic diagram.
Fig. 3 is the second delay cell structure of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Schematic diagram.
Fig. 4 (1) is the first logical operation of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention The circuit diagram of unit.
Fig. 4 (2) is the second logical operation of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention The circuit diagram of unit.
Fig. 5 is the 3rd ALU of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Circuit diagram.
Fig. 6 is the voltage controlled delay line unit of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Circuit diagram.
Fig. 7 is the voltage controlled delay line subelement of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Circuit diagram.
Fig. 8 is the charge pump construction signal of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Figure.
Fig. 9 be the embodiment of the present invention based on delay lock phase clock duty cycle stabilizing circuit charge pump in operation amplifier The circuit diagram of device
Figure 10 is the filter circuit schematic diagram of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention.
Figure 11 is the biasing circuit schematic diagram of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention.
Figure 12 is the output buffer signal of the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention Figure.
Figure 13 is that the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention is smaller in clock duty cycle At present clock input/output signal waveform diagram.
Figure 14 is that the clock duty cycle stabilizing circuit based on delay lock phase of the embodiment of the present invention is larger in clock duty cycle At present clock input/output signal waveform diagram.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where not conflicting, following examples and implementation Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way Think, only show the component relevant with the present invention in schema then rather than according to component count, shape and the size during actual implement Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel It is likely more complexity.
As shown in figure 1, the clock duty cycle stabilizing circuit based on delay lock phase in the present embodiment, including:
Delay cell, it is connected with clock signal input terminal, for carrying out phase delay to clock input signal;
The output end connection of ALU, its input and delay cell, for the signal progress to phase delay Phase-detection;
The output end connection of charge pump 700, its input and ALU, for producing the electricity associated with phase difference Press signal;
Voltage controlled delay line unit 600, for adjusting phase;
Output buffer 1000, the output end connection of its input voltage controlled delay line unit, for exporting clock signal.
Filter circuit 800, for filtering out the high-frequency signal in the voltage signal;
Biasing circuit 900, for providing bias voltage for charge pump and voltage controlled delay line unit.
In the present embodiment, delay cell includes the first delay cell DCA100 and the second delay cell DCB200, logic Arithmetic element includes the first ALU BCA300, the second ALU BCB400 and the 3rd ALU BCC500, the first ALU BCA300 and the second ALU BCB400 are and logic unit, the 3rd logic are transported Calculating unit B CC500 is or logic unit;
The clock input signal CLKIN of clock duty cycle stabilizing circuit realizes phase by delay cell DCA100 and DCB200 Position delay, after ALU BCA300, BCB400 and BCC500 realize phase-detection, is produced and phase by charge pump 700 The relevant voltage signal of potential difference, voltage signal filter out high-frequency voltage signal by filter circuit 800 by NUM7, then controlled by NUM8 Voltage controlled delay line processed adjusts phase, finally realizes balanced duty and exports clock signal by output buffer 1000 CLKOUT。
In the present embodiment, the first delay cell DCA100 input and the second delay cell DCB200 input point It is not connected with clock signal input terminal CLKIN, the first delay cell DCA100 output end and the first ALU BCA300 the second input connection, the of the second delay cell DCB200 output end and the second ALU BCB400 Two inputs connect, the first input end of the first ALU BCA300 and the second ALU BCB400's First input end connects, the first ALU BCA300 output end and the first input end of voltage controlled delay line unit 600 Connection, the second ALU BCB400 output end are connected with the 3rd ALU BCC500 first input end, 3rd ALU BCC500 output end is defeated with the first input end of charge pump 700 and output buffer 1000 respectively Enter end connection.
In the present embodiment, input clock line CLKIN and delay cell DCA100 input ports, delay cell DCB200 are defeated First input port of inbound port, ALU BCA300 first input port and ALU BCB400 It is connected, delay cell DCA100 output ports are connected with ALU BCA300 second input port by NUM1 Connecing, delay cell DCB200 output ports are connected with ALU BCB400 second input port by NUM2, ALU BCA300 output ports are connected with first input port of voltage controlled delay line 600 by NUM3, logic Arithmetic element BCB400 output ports are connected with ALU BCC500 first input port by NUM4, logic Arithmetic element BCC500 output ports and first input port, the input port of output buffer 1000 of charge pump 700 pass through NUM6 is connected, and the output port of charge pump 700 is connected with the input port of low-pass filter circuit 800 by NUM7, LPF The output port of circuit 800 is connected with second input port of voltage controlled delay line 600 by NUM8, and the of biasing circuit 900 One output port is connected with the 3rd input port of voltage controlled delay line 600 by NUM9, second group of biasing circuit 900 Output port is connected with second input port of charge pump 700 by NUM10, the output of the output port of output buffer 1000 Stable clock signal clk OUT.
As shown in Fig. 2 the first delay cell DCA100 in the present embodiment, including x phase inverter INVn1, INVn2,,, INVnx, x electric capacity Cn1, Cn2,,, Cnx, wherein x be odd number, circuit is formed by x phase inverter cascade, Each inverter output mouth connects an electric capacity, and first phase inverter INVn1 input port meets clock line CLKIN, finally One phase inverter INVnx output port is connected to NUM1, DCA100 pairs of delay cell with last electric capacity Cnx by node nx Clock signal clk IN realizes odd-times phase delay function.
As shown in figure 3, the second delay cell DCB200 in the present embodiment, including y phase inverter INVm1, INVm2,,, INVmy, y electric capacity Cm1, Cm2,,, Cmy, wherein y be even number, circuit is formed by y phase inverter cascade, Each inverter output mouth connects an electric capacity, and first phase inverter INVm1 input port meets clock line CLKIN, finally One phase inverter INVmy output port is connected to NUM2, DCB200 pairs of delay cell with last electric capacity Cmy by node my Clock signal clk IN realizes even-times phase delay function.
As shown in Fig. 4 (1), (2), 5, the first ALU BCA300 and the second ALU BCB400 difference By being formed with door AND2A and with door AND2B, realization and logical operation, the 3rd ALU BCC500 is by OR gate OR2C structures Into realization or logical operation.
As shown in fig. 6, voltage controlled delay line unit 600 is even number including z voltage controlled delay line unit VCDLz, wherein z.Pressure Control delay line 600 realizes phase delay under voltage control, voltage controlled delay line 600 by z voltage controlled delay line unit VCDL1, VCDL2,,, CVDLz cascade form, input port is connected by NUM3 with ALU BCA300, LPF Circuit 800 is connected to each voltage-controlled delay unit by NUM8, and biasing circuit 900 is that each voltage-controlled delay unit carries by NUM9 For offset signal, the output port of voltage controlled delay line 600 is connected to ALU BCC500 by NUM5, and formation is fed back to Road.
As shown in fig. 7, voltage controlled delay line subelement includes the first phase inverter INVCDL1, the first NMOS tube NVCDL1, second NMOS tube NVCDL2, the 3rd NMOS tube NVCDL3, the first PMOS PVCDL1.First reverser INVCDL1 input port is made For voltage controlled delay line unit VCDLz input port, the output port of reverser and the first PMOS PVCDL1 grid and One NMOS tube NVCDL1 grid is connected with each other, and the first PMOS PVCDL1 source electrode is connected with power line AVDD, and first PMOS PVCDL1 drain electrode is connected and as the output end of voltage controlled delay line 600 with the first NMOS tube NVCDL1 drain electrode Mouthful, the second NMOS tube NVCDL2 and the 3rd NMOS tube NVCDL3 drain electrode are connected with each other with the first NMOS tube NVCDL1 source electrodes, the Two NMOS tube NVCDL2 grid is connected with low-pass filter circuit 800, the 3rd NMOS tube NVCDL3 grid and biasing circuit 900 first output port NUM9 are connected, the second NMOS tube NVCDL2 and the 3rd NMOS tube NVCDL3 source electrode and ground wire AGND is connected, and input port is can adjust by the grid voltage for changing the second NMOS tube NCVDL2 and the 3rd metal-oxide-semiconductor NCVDL3 The rising and falling time of ndz-1 signals.
As shown in figure 8, charge pump 700 includes the second phase inverter INVCP1 and the 3rd phase inverter INVCP2, five transmission gates TRGCP1~TRGCP5, amplifier OPCP1, the 4th NMOS tube NCP1, second a PMOS PCP1.Charge pump 700 is used to realize Phase is to the conversion of voltage signal, and by voltage signal feedback control voltage controlled delay line 600, ALU BCC500 is defeated Exit port is connected with the second phase inverter INVCP1 input ports by NUM6, the second phase inverter INVCP1 output port and Three phase inverter INVCP2 input port, the first transmission gate TRGCP1 input ports are connected with each other, the 3rd phase inverter INVCP2's Output port and the second transmission gate TRGCP2 grid negative terminals mouth, the positive port of the 3rd transmission gate TRGCP3 grids, the 4th transmission gate The positive port of TRGCP4 grids, the 5th transmission gate TRGCP5 grid negative terminal mouths are connected with each other by CLKP, the first transmission gate TRGCP1 Output port and the positive port of the second transmission gate TRGCP2 grids, the 3rd transmission gate TRGCP3 grid negative terminals mouth, the 4th transmission gate TRGCP4 grid negative terminals mouth, the 5th positive port of transmission gate TRGCP5 grids are connected with each other by CLKN, the first transmission gate TRGCP1 Grid negative terminal mouth is connected with ground wire AGND, and the first positive port of transmission gate TRGCP1 grids is connected with power line AVDD, and second Transmission gate TRGCP1 input ports and the 4th transmission gate TRGCP4 input ports, the second PMOS PCP1 drain electrodes are connected with each other, the Two transmission gate TRGCP2 output ports and the 3rd transmission gate TRGCP3 input ports, amplifier OPCP1 output ports, amplifier OPCP1 Input negative terminal mouth is connected with each other by NUM7N, the 4th transmission gate TRGCP4 output ports and the 5th transmission gate TRGCP5 inputs Mouth, amplifier OPCP1 input positive terminals mouth, the input port of filter circuit 800 are connected with each other by NUM7, and the 3rd transmission gate TRGCP3 is defeated Exit port and the 5th transmission gate TRGCP5 output ports, NMOS tube NCP1 drain electrode are connected with each other, and PMOS PCP1 source electrode connects Power line AVDD, NMOS tube NCP1 source ground line AGND, PMOS PCP1 and NMOS tube NCP1 grid pass through respectively NUM10<0>And NUM10<1>It is connected with biasing circuit 900.
As shown in figure 9, in the present embodiment, amplifier OPCP1701 includes the 5th NMOS tube NOP1, the 6th in charge pump 700 NMOS tube NOP2, the 7th NMOS tube NOP3, the 3rd PMOS POP1 and the 4th PMOS POP2.Amplifier OPCP1701 is used for stable Voltage in charge pump 700 on NUM7 and NUM7N, NMOS tube NOP1 source electrode and NMOS tube NOP2 source electrode, NMOS tube NOP3 drain electrode is connected with each other, and NMOS tube NOP1 grid is the positive port VIP of amplifier, and NMOS tube NOP2 grid is born for amplifier Port VIN, NMOS tube NOP1 drain electrode are connected with each other with PMOS POP1 grid and drain electrode, PMOS POP2 grid, NMOS tube NOP2 drain electrode is connected with PMOS POP2 drain electrode, and PMOS POP1 source electrode connects with PMOS POP2 source electrode Power line AVDD is connected to, NMOS tube NOP3 source electrode is connected to ground wire AGND, and NMOS tube NOP3 grid and biasing circuit 900 is logical Cross NUM10<2>It is connected.
As shown in Figure 10, filter circuit 800 is low-pass filter circuit, including the first electric capacity CLP1, the second electric capacity CLP2 and One resistance RLP1.Filter circuit 800 is used to filter out the high-frequency voltage signal in the output voltage signal of charge pump 700, the first electricity The positive port for holding CLP1 is connected as the input port of low-pass filter circuit 800 by NUM7 with resistance RLP1 positive port, First electric capacity CLP1 negative terminal mouth and the second electric capacity CLP2 negative terminal mouth are connected to ground wire AGND, the second electric capacity CLP2 negative terminal mouth Output port as low-pass filter circuit 800 is connected by NUM8 with resistance RLP1 negative terminal mouth.
As shown in figure 11, biasing circuit 900 includes four current sources IB1~IB4, the 8th NMOS tube NBP1, the 9th NMOS Pipe NBP2, the tenth NMOS tube NBP3, the 5th PMOS PBP1, the first positive ports of current source IB1 and PMOS PBP1 grid and Drain electrode passes through NUM10<0>It is connected with each other, and bias voltage, the first current source IB1 negative terminals mouth ground wire is provided for charge pump 700 AGND, PMOS PBP1 source electrode are connected to power line AVDD.The second positive ports of current source IB2 are connected with power line AVDD, Second current source IB2 negative terminals mouth passes through NUM10 with NMOS tube NBP1 grid and drain electrode<1>It is connected, and is carried for charge pump 700 For bias voltage, NMOS tube NBP1 source electrode is connected with ground wire AGND.The 3rd positive ports of current source IB3 and power line AVDD phases Connection, the 3rd current source IB3 negative terminals mouth pass through NUM10 with NMOS tube NBP2 grid and drain electrode<2>It is connected, and is charge pump Amplifier OPCP1 in 700 provides bias voltage, and NMOS tube NBP2 source electrode is connected to the ground, the 4th positive ports of current source IB4 with Power line AVDD is connected, and the 4th current source IB4 negative terminals mouth is connected with the 3rd NMOS tube NBP3 grid and drain electrode by NUM9 Connect, and bias voltage is provided for voltage controlled delay line 600, the 3rd NMOS tube NBP3 source electrode is connected with ground wire AGND.
As shown in figure 12, output buffer 1000 includes k phase inverter INVB1~INVBk, and wherein k is even number.Output is slow Rush device 1000 be used for improve output clock signal clk OUT driving forces, output buffer 1000 by k phase inverter INVB1~ INVBk cascades form, and first phase inverter INVB1 input port is connected to the 3rd ALU 500 and electricity by NUM6 Lotus pump 700.
As shown in figure 13, the clock duty cycle stabilizing circuit clock duty cycle based on delay lock phase in the present embodiment is smaller When, when the course of work is t0, clock duty cycle stabilizing circuit input duty cycle < 50% clock signal clk IN, as tn, warp Delay lock phase feedback regulation is crossed, when the feedback voltage of pilot delay line is stable, circuit starts that output duty cycle is stable, it is small to shake Clock signal clk OUT.
As shown in figure 14, the clock duty cycle stabilizing circuit clock duty cycle based on delay lock phase in embodiment is larger When, when its course of work is t0, clock duty cycle stabilizing circuit input duty cycle > 50% clock signal clk IN, as tn, Phase feedback regulation is locked by delay, when the feedback voltage of pilot delay line is stable, circuit starts that output duty cycle is stable, it is small to shake Clock signal clk OUT.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as Into all equivalent modifications or change, should by the present invention claim be covered.

Claims (11)

  1. A kind of 1. clock duty cycle stabilizing circuit based on delay lock phase, it is characterised in that including:
    Delay cell, it is connected with clock signal input terminal, for carrying out phase delay to clock input signal;
    The output end connection of ALU, its input and delay cell, for carrying out phase to the signal of phase delay Detection;
    The output end connection of charge pump, its input and ALU, for producing the voltage signal associated with phase difference;
    Voltage controlled delay line unit, for adjusting phase;
    Output buffer, its input is connected with the output end of voltage controlled delay line unit, for exporting clock signal.
  2. 2. the clock duty cycle stabilizing circuit according to claim 1 based on delay lock phase, it is characterised in that also include:
    Filter circuit, for filtering out the high-frequency signal in the voltage signal;
    Biasing circuit, for providing bias voltage for charge pump and voltage controlled delay line unit.
  3. 3. the clock duty cycle stabilizing circuit according to claim 2 based on delay lock phase, it is characterised in that:The delay Unit includes the first delay cell and the second delay cell, and the ALU includes the first ALU, second ALU and the 3rd ALU, first ALU and the second ALU are and logic Unit, the 3rd ALU are or logic unit;
    The input of first delay cell and the second delay cell input are connected with clock signal input terminal respectively, and first The output end of delay cell is connected with the second input of the first ALU, the output end of the second delay cell and second The second input connection of ALU, the first input end of first ALU and the second logical operation list The first input end connection of member, the output end of the first ALU are connected with the first input end of voltage controlled delay line unit, The output end of second ALU is connected with the first input end of the 3rd ALU, the 3rd ALU Output end is connected with the first input end of charge pump unit and the input of output buffer respectively.
  4. 4. the clock duty cycle stabilizing circuit according to claim 3 based on delay lock phase, it is characterised in that:The electric charge The input of the output end of pump unit and filter unit connects, the output end of filter unit and the second of voltage controlled delay line unit defeated Enter end connection, the first output end of biasing circuit and the 3rd input of voltage controlled delay line connect, the second output of biasing circuit Second input of port and charge pump unit connects.
  5. 5. the clock duty cycle stabilizing circuit according to claim 4 based on delay lock phase, it is characterised in that:Described first Delay cell carries out odd-times phase delay to clock signal, and second delay cell carries out even-times phase to clock signal Delay,.
  6. 6. the clock duty cycle stabilizing circuit according to claim 4 based on delay lock phase, it is characterised in that:It is described voltage-controlled Delay line includes the voltage controlled delay line subelement of even number cascade, described for carrying out phase delay in the case where voltage controls Voltage controlled delay line subelement includes the first phase inverter, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the first PMOS, The input of first phase inverter is the input of voltage controlled delay line, the output end of first phase inverter respectively with PMOS Grid and the first NMOS tube grid connection, the source electrode of the first PMOS is connected with power line, the drain electrode of the first PMOS and The drain electrode connection of first NMOS tube simultaneously drains and the 3rd NMOS tube as the output port of voltage controlled delay line, the second NMOS tube The source electrode respectively with the first NMOS tube that drains is connected, and the grid of the second NMOS tube is connected with filter circuit, the grid of the 3rd NMOS tube Pole is connected with the output end of biasing circuit first, and the source electrode of the source electrode of the second NMOS tube and the 3rd NMOS tube is connected with ground wire respectively; By controlling the grid voltage of the second NMOS tube and the 3rd metal-oxide-semiconductor, the rising and falling time of input signal is adjusted.
  7. 7. the clock duty cycle stabilizing circuit according to claim 4 based on delay lock phase, it is characterised in that:The electric charge Pump includes the second phase inverter, the 3rd phase inverter, operational amplifier, the 4th NMOS tube, the second PMOS, the first transmission gate, second Transmission gate, the 3rd transmission gate, the 4th transmission gate and the 5th transmission gate, the output end of the 3rd ALU and second anti- The input connection of phase device, the output end input with the input and the first transmission gate of the 3rd phase inverter respectively of the second phase inverter End connection, the output end of the 3rd phase inverter respectively the grid negative terminal mouth with the second transmission gate, the 3rd transmission gate the positive port of grid, The positive port of grid of 4th transmission gate connects with the grid negative terminal of the 5th transmission gate, and the output end of the first transmission gate is respectively with second The positive port of grid of transmission gate, the grid negative terminal mouth of the 3rd transmission gate, the grid negative terminal mouth of the 4th transmission gate, the 5th transmission gate The connection of grid positive port, the grid negative terminal mouth of first transmission gate are connected with ground wire, the positive port of grid of the first transmission gate and Power line is connected, and drain electrode of the second transmission gate input respectively with the input and the second PMOS of the 4th transmission gate is connected, the The input with the 3rd transmission gate, the output end of operational amplifier and the input of operational amplifier respectively of the output end of two transmission gates Negative terminal mouth connects, the output end of the 4th transmission gate respectively the input with the 5th transmission gate, operational amplifier input positive terminal and Filter circuit input connects, the output end leakage with the output end and the 4th NMOS tube of the 5th transmission gate respectively of the 3rd transmission gate Pole connects, and the source electrode of the second PMOS connects power line, the source ground line of the 4th NMOS tube, the grid of the second PMOS and the 4th The grid of NMOS tube is connected with biasing circuit respectively.
  8. 8. the clock duty cycle stabilizing circuit according to claim 7 based on delay lock phase, it is characterised in that:The computing Amplifier includes the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 3rd PMOS and the 4th PMOS, the 5th NMOS tube Drain electrode of the source electrode respectively with the source electrode and the 7th NMOS tube of the 6th NMOS tube be connected, the grid of the 5th NMOS tube is operation amplifier The positive port of device, the grid of the 6th NMOS tube are the negative terminal mouth of operational amplifier, and the drain electrode of the 5th NMOS tube is respectively with the 3rd The grid of PMOS connects with the grid of drain electrode, the 4th PMOS, and the drain electrode of the 6th NMOS tube connects with the drain electrode of the 4th PMOS Connect, the source electrode of the 3rd PMOS is connected with power line respectively with the source electrode of the 4th PMOS, the source electrode connection ground of the 7th NMOS tube Line, the grid of the 7th NMOS tube are connected with biasing circuit.
  9. 9. the clock duty cycle stabilizing circuit according to claim 2 based on delay lock phase, it is characterised in that:The biasing Circuit includes the first current source, the second current source, the 3rd current source, the 4th current source, the 8th NMOS tube, the 9th NMOS tube, the Ten NMOS tubes and the 5th PMOS, the positive port of the first current source connects with the grid of the 5th PMOS and drain electrode respectively, and is Charge pump provides bias voltage, the negative terminal mouth ground wire of the first current source, and the source electrode of the 5th PMOS connects power line, the second electric current The positive port in source is connected with power line, and the negative terminal mouth of the second current source connects with the grid of the 8th NMOS tube and drain electrode respectively, and Bias voltage is provided for charge pump, the source electrode of the 8th NMOS tube is connected with ground wire, the positive port of the 3rd current source and power line Connection, the negative terminal mouth of the 3rd current source connects with the grid of the 9th NMOS tube and drain electrode respectively, and is carried for the amplifier in charge pump For bias voltage, the source electrode of the 9th NMOS tube is connected with ground wire, and the positive port of the 4th current source is connected with power line, the 4th electric current The negative terminal mouth in source connects with the grid of the tenth NMOS tube and drain electrode respectively, and provides bias voltage for voltage controlled delay line unit, the The source electrode of ten NMOS tubes is connected with ground wire.
  10. 10. the clock duty cycle stabilizing circuit according to claim 1 based on delay lock phase, it is characterised in that:It is described defeated Going out buffer includes the phase inverter of even number cascade.
  11. 11. the clock duty cycle stabilizing circuit according to claim 2 based on delay lock phase, it is characterised in that:The filter Wave circuit is low-pass filter circuit, and the low pass circuit includes the first electric capacity, the second electric capacity and resistance, and first electric capacity is striven Port as filter circuit input port and be connected with the positive port of resistance, the negative terminal mouth of the first electric capacity and the second electric capacity it is negative Port connection is connected with ground wire respectively, the negative terminal mouth of the second electric capacity as filter circuit output port and with the negative terminal mouth of resistance Connection.
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