CN105406829A - Variable gain amplifier with continuously adjustable gain - Google Patents
Variable gain amplifier with continuously adjustable gain Download PDFInfo
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- CN105406829A CN105406829A CN201510882746.4A CN201510882746A CN105406829A CN 105406829 A CN105406829 A CN 105406829A CN 201510882746 A CN201510882746 A CN 201510882746A CN 105406829 A CN105406829 A CN 105406829A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
- H03G3/301—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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Abstract
The invention discloses a variable gain amplifier with continuously adjustable gain. The variable gain amplifier with continuously adjustable gain comprises an operation transconductance amplifier used for converting an input signal into a current signal; a switching capacitive load connected to the output end of the operation transconductance amplifier and used for converting the current signal output by the operation transconductance amplifier into a voltage signal and amplifying the voltage signal, wherein the amplification time of the voltage signal depends on an equivalent impedance of the switching capacitive load; and an impedance control oscillator used for generating a control clock signal for controlling the size of the equivalent impedance of the switching capacitive load. The control clock signal can be adjusted by an off-chip adjustable resistor which is connected to the impedance control oscillator. A VGA (Variable Gain Amplifier) circuit can realize frequency adjustment of the impedance control oscillator just by using one off-chip adjustable resistor; and a continuous adjusting function for the VGA gain can be realized by using the impedance control oscillator to adjust the switching capacitive load. At the same time, the VGA circuit does not comprise a big resistor and a big capacitor, so that the area of the silicon wafer of the VGA circuit is saved.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of switching capacity variable gain amplifier, it has integrated in gain continuously adjustabe, full sheet and consumes the advantages such as silicon area is little.
Background technology
At small-signal (as bioelectrical signals detection, current detecting and inertial sensor etc.) detection field, usual employing casacade multi-amplifier amplifies faint measured signal, and possess adjustable gain joint and the adjustable function of bandwidth, to adapt to the testing requirement of different frequency and amplitude range, as shown in Figure 1.Wherein the function of adjustable gain joint, generally adopts variable gain amplifier (VariableGainAmplifier, VGA) to realize; The adjustable function of bandwidth, the general low pass filter that adopts realizes.In traditional VGA realizing circuit, the mode of usual digital programmable realizes, and as shown in Figure 2, if the gain of amplifier is infinitely great, so the gain expressions of VGA can be expressed as R
f/ R
p, wherein R
pfor input resistance, feedback resistance R
f=S
1* R
f1+ S
2* R
f2+ ... + S
(N-1)* R
f (N-1)+ R
fNif, S
idisconnect, then S
i=1, on the contrary S
i=0 (i=1,2 ... N-1).Feedback resistance R can be controlled by control switch S1 ~ S (N-1)
fsize, thus the gain of control VGA.
The shortcoming of this structure is, can only regulate discrete, limited yield value, if will increase the number of yield value, must increase the quantity of control switch.But the conducting resistance of actual control switch is not 0, and not exclusively equal, the feedback resistance size on amplifier OP both sides will be caused unequal, i.e. mismatch.If the quantity of control switch increases, the mismatch of feedback resistance will be more serious.The problem that resistance mismatch is brought is that the common-mode rejection ratio of VGA declines, the linearity reduces.Meanwhile, due to R
fto the load effect of OP, in order to ensure R
fthe open-loop gain of OP itself can not be reduced, R
fbe greater than the output resistance of OP.Therefore R
fnumerical value usually all in M Ω magnitude, in Application of integrated circuit, especially in multi-channel detection circuit, if each passage needs a VGA, a large amount of chip areas will be taken.
Summary of the invention
The invention provides the continuously adjustable variable gain amplifier of a kind of gain, it adopts switched-capacitor circuit as the load of amplifier, by a resistance controlled oscillator (ResistorControlledOscillator, RCO) the continuously adjustable square-wave signal of frequency is produced, switch capacitive load is controlled, realizes the continuous adjustment of VGA gain.
According to the present invention, which provide the continuously adjustable variable gain amplifier of a kind of gain, comprising:
Operation transconductance amplifier, for being converted to current signal by input signal;
Switching capacity load, be connected to the output of described operation transconductance amplifier, current signal for being exported by described operation transconductance amplifier is converted to voltage signal and amplifies, and wherein, the multiplication factor of described voltage signal depends on the equiva lent impedance of described switching capacity load;
Resistance controlled oscillator, for generation of the control clock signal controlling described switching capacity load equivalent impedance magnitude; Described control clock signal regulates by the outer adjustable resistance of sheet being connected to described resistance controlled oscillator.
Switching capacity variable gain amplifier (VGA) circuit disclosed by the invention, only can realize the frequency adjustment to resistance controlled oscillator with the outer adjustable resistance of a sheet, resistance controlled oscillator regulates switch capacitive load, can realize the continuous regulatory function to VGA gain.Do not comprise large resistance and bulky capacitor in VGA circuit simultaneously, save the silicon area of VGA circuit.
Accompanying drawing explanation
Fig. 1 is the multistage structure for amplifying schematic diagram of Detection of Weak Signals path;
Fig. 2 is traditional variable gain amplifier (VGA) electrical block diagram;
Fig. 3 is switching capacity VGA electrical block diagram of the present invention;
Fig. 4 is Fig. 3 breaker in middle capacitive load 201 electrical block diagram;
Fig. 5 is the input-output characteristic schematic diagram of non-overlapping clock generator in Fig. 4;
Fig. 6 is the electrical block diagram hindering controlled oscillator 202 in Fig. 3;
Fig. 7 is the waveform schematic diagram of the key event of circuit shown in Fig. 6;
Fig. 8 is the electrical block diagram of constant time lag circuit 420 in Fig. 6;
Fig. 9 is the gain of switching capacity VGA circuit of the present invention and the simulation curve schematic diagram of the outer adjustable resistance of sheet;
Figure 10 is the transfer function of switching capacity VGA circuit of the present invention and the simulation curve schematic diagram of the outer adjustable resistance of sheet.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
As shown in Figure 3, the present invention proposes the continuously adjustable variable gain amplifier of a kind of gain (VGA) 200, it comprises an operation transconductance amplifier (OperationalTransconductanceAmplifier, OTA), a switching capacity load 201 and a resistance controlled oscillator 202.
Operation transconductance amplifier, for by input voltage signal (V
iPwith V
iNthe difference of voltage) be converted into current signal.The feature of operation transconductance amplifier is that the output impedance of self is very large, ideally infinitely great.
Switching capacity load, is positioned over the output of operation transconductance amplifier, for the output current signal of operation transconductance amplifier is converted to voltage signal.The equiva lent impedance of switching capacity load much smaller than the output impedance of operation transconductance amplifier self, so the output current of operation transconductance amplifier will all flow to switching capacity load.Therefore switching capacity load is placed in the output of operation transconductance amplifier, can realizes input voltage signal (V
iPwith V
iNthe difference of voltage) amplify, become output voltage signal (V
oPwith V
oNdifference).Meanwhile, the equiva lent impedance of switching capacity load and the frequency (f of control clock
sc) inversely, namely by controlling the equiva lent impedance of the size adjustment switching capacity load of clock, and then the multiplication factor between the output voltage of operation transconductance amplifier and input voltage can be regulated.
Resistance controlled oscillator, for generation of the control clock signal of described switching capacity load, its feature is the clock signal frequency that namely can be adjusted output by the outer adjustable resistance of a slice.
In sum, by operation transconductance amplifier, switching capacity load and the synergy hindering controlled oscillator, the continuously adjustable function of gain being realized variable gain amplifier by the outer adjustable resistance of a slice namely can be realized.
The reversed-phase output of operation transconductance amplifier OTA, the first input end N1 of switching capacity load 201 are connected, as the reversed-phase output V of VGA
oN.The in-phase output end of OTA, the second input N2 of switching capacity load 201 are connected, as the in-phase output end V of VGA
oP.First output N of resistance controlled oscillator 202
cadjustable resistance R outer with sheet
oSCone end be connected, resistance controlled oscillator 202 input V
refwith the output V of reference voltage source on sheet
bGbe connected, resistance the second output clk_sc of controlled oscillator 202 is connected with the 3rd input clk_in of switching capacity load 201.The outer adjustable resistance R of sheet
oSCother end ground connection.The in-phase input end of OTA and inverting input are respectively as the in-phase input end V of VGA
iPwith inverting input V
iN.
As shown in Figure 3, described switching capacity load 201 comprises a non-overlapping clock generator 301, two switch (S
n1, S
n2), an electric capacity C
0.The input of non-overlapping clock generator 301 as the 3rd input clk_in of switching capacity load 201, for receiving the control clock signal that resistance controlled oscillator exports.The output clk of non-overlapping clock generator 301 and the first switch (S
n1) control end ph1 be connected.The output clk_b of non-overlapping clock generator 301 and second switch (S
n2) control end ph2 be connected.First switch (S
n1) one end as the first input end N1 of switching capacity load 201, for receiving the current signal that operation transconductance amplifier OTA reversed-phase output exports, second switch (S
n2) one end as the second input N2 of switching capacity load 201, for receiving the current signal that operation transconductance amplifier OTA in-phase output end exports.First switch (S
n1) the other end, second switch (S
n2) the other end and the first electric capacity (C
0) top crown be connected.First electric capacity (C
0) bottom crown ground connection.
Described non-overlapping clock generator 301 has following input-output characteristic: input signal clk_in and two output signal clk and clk_b of non-overlapping clock generator 301 is square-wave signal, and frequency is identical.Described clk signal and described clk_in signal homophase, described clk_b signal and described clk_in signal inversion.The rising edge of described clk signal postpones T than the trailing edge of described clk_b signal
dthe time interval, the rising edge of described clk_b signal postpones T than the trailing edge of clk signal
dthe time interval, as shown in Figure 5.Described time interval T
deffect be guarantee first switch (S
n1) and second switch (S
n2) can not conducting simultaneously.T
dsize design ratio first switch (S
n1) and second switch (S
n2) and the first electric capacity (C
0) the large twice of time constant more than.
As shown in Figure 4, described resistance controlled oscillator 202 is made up of resistance control delay circuit 410, constant time lag circuit 420 and a d type flip flop 430.Resistance controls delay circuit 410 by an operational amplifier (OP), a comparator 411,3 PMOS (PM1, PM2, PM3), 2 NMOS tube (NM1, NM2), an electric capacity (C
oSC) composition.
The annexation of described resistance controlled oscillator 202 is: the in-phase input end of operational amplifier OP is connected with the inverting input of comparator, and as hindering the V of controlled oscillator 202
refinput.The inverting input of operational amplifier OP is connected with the source electrode of the first NMOS tube (NM1), and as hindering the first output N of controlled oscillator 202
c.The output of operational amplifier OP is connected with the grid of the first NMOS tube (NM1).The grid of the first PMOS (PM1) is with the drain electrode of drain electrode, the first NMOS tube (NM1), be connected with the grid of the second PMOS (PM2).The drain electrode of the second PMOS (PM2) is connected with the source electrode of the 3rd PMOS (PM3).The drain electrode of the 3rd PMOS (PM3), the drain electrode of the second NMOS tube (NM2), the second electric capacity C
oSCtop crown be connected with the inverting input of comparator 411.The output V of comparator 411
comwith the input V of constant time lag circuit 420
d1be connected.The output V of constant time lag circuit 420
d2, the second PMOS (PM2) grid be connected with the input end of clock clk of d type flip flop 430 with the grid of the 3rd PMOS (PM3).The data input pin D of d type flip flop 430 is connected with reversed-phase output Qb.The in-phase output end Q of d type flip flop 430, as the second output clk_sc of resistance controlled oscillator 202, is the square-wave signal of 50% for output duty cycle, namely controls clock signal.
As shown in Figure 8, described constant time lag circuit 420 is become by the individual identical inverter stage joint group of n, and n is even number.The input of the first inverter (Inv1) is as constant time lag circuit 420 input V
d1, the output of the first inverter (Inv1) is connected with the input of the second inverter (Inv2), and the output of the second inverter (Inv2) is connected with the input of the 3rd inverter (Inv3).By that analogy, until the n-th inverter (Invn).The output of the n-th inverter (Invn) is as constant time lag circuit 420 output V
d2.The time delay of described constant time lag circuit 420 is n times of inverter time delay.
As shown in Figure 3, OTA described in the present invention is the higher amplifier of a kind of output impedance, and possesses comparatively constant transconductance value, and its output resistance and transconductance value are respectively R
outand G
m.The input port N1 of switching capacity load 201 and the equivalent resistance at N2 two ends are R
sC, R
sCvalue be subject to hindering the control of controlled oscillator 202, its value is much smaller than R
out, so the gain expressions of VGA is:
A
VGA＝G
m(R
out||R
SC)≈G
mR
SC(1)
Switching capacity load 201 is the switching capacity resistance controlled by two-phase non-overlapping clock clk and clk_b, as shown in Figure 4.Wherein clk and clk_b is the non-overlapping square-wave signal of cycle T, and input signal clk_in and two output signal clk and clk_b is square-wave signal, and frequency is identical.Its signal waveform as shown in Figure 5, clk signal and clk_in signal homophase, clk_b signal and clk_in signal inversion.The rising edge of clk signal postpones T than the trailing edge of described clk_b signal
dthe time interval, the rising edge of clk_b signal postpones T than the trailing edge of clk signal
dthe time interval.
As Fig. 5, during clk_b phase (i.e. clk=0, clk_b=1), S
n1disconnect, S
n2closed, C
0top crown voltage is V
n2, C
0on electric charge be Q
2=C
0v
n2.During clk phase (i.e. clk=1, clk_b=0), N1 terminal voltage is to C
0charge to V
n1, now C
0on electric charge be Q
i=C
0v
n1.In this cycle T, the average current flowing into switching capacity load 201 from N1 end is I
avg=(Q
1-Q
2)/T.So equivalent resistance R of switching capacity load 201
sCexpression formula be
Wherein f
sCbe the frequency of the output clock clk_sc of resistance controlled oscillator 202, (2) formula is substituted into (1) formula can be obtained:
A
VGA＝G
m/(f
SCC
0)(3)
If can control f
sCsize, just can the gain of control VGA.The structure of resistance controlled oscillator 202 as shown in Figure 6, is made up of resistance control delay circuit 410, constant time lag circuit 420 and d type flip flop 430.In resistance control delay circuit, the negative feedback of operational amplifier (OP1), makes its in-phase end voltage approximate end of oppisite phase, i.e. N
cterminal voltage approximates reference voltage V
ref.As shown in Figure 3, N
cend adjustable resistance R outer with sheet
oSCone end be connected, R
oSCother end ground connection, thus the electric current flowing through PM1 and NM1 is I
1=V
ref/ R
oSC.Because PM1 and PM2 forms current-mirror structure, and the ratio of size is 1: k, and the electric current flowing through PM2 is:
I
2＝kV
ref/R
OSC(4)
As shown in Figure 7, its oscillatory work principle is as described below for the waveform schematic diagram of resistance controlled oscillator 202:
A () is as the output voltage V of constant time lag circuit 420
d2from 0 saltus step to supply voltage V
dDtime, the grid voltage V of PM3 and NM2
c1also from 0 saltus step to V
dD, thus PM3 cut-off, NM2 conducting, voltage C
oSCelectric charge released rapidly by NM2, the in-phase end voltage jump of comparator 411 is 0, and end of oppisite phase voltage is V
ref, comparator 411 output voltage is from V
dDsaltus step is 0.
B () is through the time delay T of constant time lag circuit 420
dFafterwards, V
d2also from saltus step be 0.Thus PM3 conducting, NM2 ends, the electric current I of PM2
2start C
oSCcharging, V
c2voltage rise gradually, work as V
c2voltage is greater than the end of oppisite phase voltage V of comparator 411
reftime, the output voltage of comparator 411 is from 0 saltus step to V
dD, through the time delay T of constant time lag circuit 420
dFafterwards, V
d2from 0 saltus step to V
dD.Repeat step (a), namely oscillator can work.The data input pin of d type flip flop 430 is connected with reversed-phase output Qb, forms the structure of two-divider, and its effect makes the output clock duty ratio hindering controlled oscillator 202 be 50%.
Constant time lag circuit 420 as shown in Figure 8, is formed by n inverter cascade, and the time delay of each inverter is T
iNV, so time delay T of constant time lag circuit 420
dF=nT
iNV.Meanwhile, n is even number, ensures V
d1and V
d2same phase behaviour, i.e. V
d2waveform in time domain is by V
d1postpone T
dFtime obtain.
In the process of vibration, the time delay that resistance control delay circuit 410 is contributed is T
dR, its expression formula is:
T
DR＝V
refC
OSC/I
2(5)
Comprehensive the above, and combine (4) formula and (5) formula, the frequency that can obtain hindering controlled oscillator is:
Thus (3) formula can be changed into:
As can be seen from (6) and (7) formula, at circuit parameter C
oSC, k and T
dFwhen all fixing, the frequency f of resistance controlled oscillator
sCwith the gain A of VGA
vGAall can by the outer adjustable resistance R of sheet
oSCcontrol, and A
vGAwith R
oSCfor the linear relationship of direct ratio.The outer adjustable resistance R of sheet
oSCcan regulate continuously, therefore A
vGAalso achieve the function regulated continuously.
In addition, the above-mentioned definition to constant time lag circuit 420 is not limited in structure shown in Fig. 8, and the delay circuit of other kind of structure can be adopted to realize, as long as ensure V
d1and V
d2same phase behaviour.
(1) be illustrated the beneficial effect of circuit shown in Fig. 3 below in conjunction with simulation waveform, circuit simulation model is 0.18 μm of standard CMOS process storehouse.The G of the OTA that emulation adopts
mapproximate 7.8 μ S, C
0be about 140fF, C
oSCbe about 40fF, k=1, T
dFbe about 232ns.Regulate R
oSCchange from 1M Ω to 51M Ω, obtain the DC current gain A as Fig. 9
vGAwith R
oSCrelation.Can find out, the VGA circuit shown in Fig. 3 can realize continuously adjustable function, can be adjusted to 117.5 times from 13.8 times.Figure 10 is transfer function and R
oSCrelation, can find out along with R
oSClinear growth, the also linear growth of the gain in passband.
(2) because circuit shown in Fig. 3 does not adopt a large amount of feedback resistance of circuit as shown in Figure 2, only have employed the C compared with low-capacitance
0and C
oSCrealize enlarging function, substantially reduce the silicon area that integrated circuit adopts.If in multi-channel circuit, when there being multiple VGA circuit, only needing a resistance controlled oscillator 202 can realize regulating the gain of the VGA of multiple passage, further reducing silicon area.Meanwhile, only have switching capacity load 201 two switches in circuit, number of switches greatly reduces, and eliminates in Fig. 2 because switch does not mate the problem of the linearity decline brought.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the continuously adjustable variable gain amplifier of gain, comprising:
Operation transconductance amplifier, for being converted to current signal by input signal;
Switching capacity load, be connected to the output of described operation transconductance amplifier, current signal for being exported by described operation transconductance amplifier is converted to voltage signal and amplifies, and wherein, the multiplication factor of described voltage signal depends on the equiva lent impedance of described switching capacity load;
Resistance controlled oscillator, for generation of the control clock signal controlling described switching capacity load equivalent impedance magnitude; Described control clock signal regulates by the outer adjustable resistance of sheet being connected to described resistance controlled oscillator.
2. variable gain amplifier as claimed in claim 1, wherein, the reversed-phase output of operation transconductance amplifier, the first input end of switching capacity load are connected, as the reversed-phase output of described variable gain amplifier; The in-phase output end of described operation transconductance amplifier, the second input of switching capacity load are connected, as the in-phase output end of described variable gain amplifier; First output of described resistance controlled oscillator is connected with one end of described outer adjustable resistance, the input of described resistance controlled oscillator is connected with the output of reference voltage source on sheet, and the second output of described resistance controlled oscillator is connected with the 3rd input of described switching capacity load; The other end ground connection of described outer adjustable resistance; The in-phase input end of described operation transconductance amplifier and inverting input are respectively as the in-phase input end of described variable gain amplifier and inverting input.
3. variable gain amplifier as claimed in claim 1, wherein, described switching capacity load comprises non-overlapping clock generator, first switch, second switch and the first electric capacity, the input of described non-overlapping clock generator is as the 3rd input of switching capacity load, the output of non-overlapping clock generator is connected with the control end of the first switch, the output of non-overlapping clock generator, be connected with the control end of second switch, one end of first switch is as the first input end of switching capacity load, one end of second switch is as the second input of switching capacity load, the other end of the first switch, the other end of second switch is connected with the top crown of the first electric capacity, the bottom crown ground connection of the first electric capacity.
4. variable gain amplifier as claimed in claim 3, wherein, input signal and its first output signal, second output signal of described non-overlapping clock generator are square-wave signal, and frequency is identical, described input signal and described first outputs signal homophase, described second output signal is anti-phase with described input signal, the rising edge of described first output signal postpones the first predetermined time interval than the trailing edge of described second output signal, and the rising edge of described second output signal postpones the first predetermined time interval than the trailing edge of the first output signal.
5. variable gain amplifier as claimed in claim 1, wherein, described resistance controlled oscillator comprises resistance control delay circuit, constant time lag circuit and d type flip flop, wherein, described resistance control delay circuit comprises operational amplifier, comparator, the first PMOS, the second PMOS, the 3rd PMOS, the first NMOS tube, the second NMOS tube and the second electric capacity, wherein, the in-phase input end of operational amplifier is connected with the inverting input of comparator, and as hindering the input of controlled oscillator, the inverting input of operational amplifier is connected with the source electrode of the first NMOS tube, and as hindering the first output of controlled oscillator 202, the output of operational amplifier is connected with the grid of the first NMOS tube, the grid of the first PMOS and drain electrode, the drain electrode of the first NMOS tube, be connected with the grid of the second PMOS, the drain electrode of the second PMOS is connected with the source electrode of the 3rd PMOS, the drain electrode of the 3rd PMOS, the drain electrode of the second NMOS tube, the top crown of the second electric capacity is connected with the inverting input of comparator, the output of comparator is connected with the input of constant time lag circuit, the output of constant time lag circuit, the grid of the second PMOS is connected with the input end of clock of d type flip flop with the grid of the 3rd PMOS, the data input pin of d type flip flop is connected with reversed-phase output, the in-phase output end of d type flip flop is as the second output hindering controlled oscillator.
6. variable gain amplifier as claimed in claim 5, wherein, described constant time lag circuit is become by the individual identical inverter stage joint group of n, and n is even number; Wherein, the input of the first inverter in n identical inverter is as constant time lag circuit input end, and the output of the n-th inverter is as constant time lag circuit output end, and the time delay of described constant time lag circuit is n times of inverter time delay.
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