CN203630657U - Voltage stabilizing circuit - Google Patents

Voltage stabilizing circuit Download PDF

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Publication number
CN203630657U
CN203630657U CN201320830722.0U CN201320830722U CN203630657U CN 203630657 U CN203630657 U CN 203630657U CN 201320830722 U CN201320830722 U CN 201320830722U CN 203630657 U CN203630657 U CN 203630657U
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China
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voltage
output
circuit
signal
line
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CN201320830722.0U
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Chinese (zh)
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陆虹
王佳宁
孙轶君
景欣
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CETC 4 Research Institute
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CETC 4 Research Institute
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Abstract

The utility model discloses a voltage stabilizing circuit. The voltage stabilizing circuit comprises a control unit, a clock generation unit and an output unit, wherein the control unit comprises a digital filter circuit and an analog comparator circuit, an output voltage sample of the voltage stabilizing circuit is compared with a reference voltage through the analog comparator circuit, the control unit outputs a control signal according to the comparison result, the clock generation unit outputs a corresponding clock signal according to the control signal output by the analog comparator circuit, the output unit comprises driving transistors and a charge pump, the driving transistors are used for outputting working voltages, and the charge pump is used for driving grid electrodes of the driving transistors. When the output voltage is lower than the reference voltage, the charge pump carries out boosting on the grid electrodes of output transistors according to the clock signal; when the output voltage is higher than the reference voltage, charge distribution is carried out on capacitors of the charge pump and the grid electrodes of the output transistors according to the clock signal so that the output voltage can be reduced. The voltage stabilizing circuit carries out moderate adjustment on the internal power voltage under the control of an out-phase clock, no large compensation capacitors are needed, and the voltage stabilizing circuit has the advantages of being high in response speed, good in power supply noise resistance and easy to integrate.

Description

Mu balanced circuit
Technical field
The utility model relates to power circuit.More specifically, the utility model relates to when supply voltage is unstable or the mu balanced circuit of output voltage stably during by noise.
Background technology
The applied environment of modern integrated circuits becomes increasingly complex.Very violent when current-jump, there are a lot of frequency device effects, energy is during to external radiation, and circuit there will be noise failure.Electric current sharply changes and causes mains voltage variations, can make to share the circuit fluctuation of service of same power supply.In addition, complicated along with electronic system, relates to multiple power sources in circuit, and the power supply in the work being produced by external power source is because the noise of inside circuit has fluctuation equally.This problem is along with signal speed is more and more faster, and the more and more less of the supply voltage of integrated circuit (IC) chip becomes even more serious.In addition, no matter electronic equipment is to be powered after overcommutation (or AC adapter) by electric main, or is powered by battery pack, and the supply voltage in the course of work all will in very large range change.For example, voltage when monomer lithium ion battery full charge is 4.2V, and the voltage after being discharged is 2.3V, and amplitude of variation is very large.It is particularly outstanding that this problem seems in to the circuit of supply voltage sensitivity.Therefore, in designing the circuit of power supply sensitivity, need to take some measures to remove to greatest extent power supply noise and power-supply fluctuation.
Existing method is that employing low pressure difference linear voltage regulator (LDO) circuit structure is accurate electronic equipment power supply, thereby LDO regulates the VD that provides stable to output voltage by its backfeed loop.This structure needs large shunt capacitance to be integrated in inside circuit conventionally, and this is more difficult, and therefore its noise response speed for inside circuit is slower.
Utility model content
In order to overcome the shortcoming that existing mu balanced circuit is slow to noise response speed, building-out capacitor is large, one of the purpose of this utility model is the mu balanced circuit that provides novel, and this circuit can be made rapid reaction and not need large building-out capacitor power supply noise.
According to an aspect of the present utility model, the mu balanced circuit providing comprises: control module, comprise digital filter circuit and analog comparator, output voltage sampling and the reference voltage of described mu balanced circuit compare in described analog comparator, and described analog comparator is according to the result output control signal of described comparison; Clock phase generation unit, exports corresponding clock signal according to the control signal of comparer output; With driving grid pump and driving circuit, export corresponding voltage according to described clock signal, wherein, when described output voltage is during lower than reference voltage, described charge pump drives described output transistor that output voltage is boosted according to described clock signal; When described output voltage is during higher than reference voltage, the electric capacity of described charge pump carries out electric charge distribution according to described clock signal and output transistor gates, with by described output voltage step-down.
In some embodiments, described analog comparator has output voltage sampled signal input end and reference voltage input, and the output terminal of described comparer is respectively by output digit signals after Sheffer stroke gate, phase inverter and trigger.
In some embodiments, also comprise selector circuit, described digital signal is connected in the output voltage sampling input end of described analog comparator by described selector circuit.
In some embodiments, described charge pump is two PMOS charge pumps, and described electric capacity is made up of metal-oxide-semiconductor.
Described driving grid pump also comprises that with driving circuit the metal-oxide-semiconductor as electric capacity of multiple parallel connections is connected the switch of the described metal-oxide-semiconductor as electric capacity with selectivity.
In some embodiments, digital filter circuit can adopt d type flip flop, the output of described analog comparator inputs to d type flip flop, described d type flip flop receives the clock signal from described clock generating unit, only at the edge of this clock signal, the output of described analog comparator is sampled, to export control signal.Described analog comparator and described digital filter circuit are integrated in individual digit comparer.
According on the other hand of the present utility model, a kind of method for stabilizing voltage of power circuit is provided, described power circuit comprises Voltage-output transistor and charge pump circuit, described method comprises: by the sampling of the Voltage-output of power circuit and reference voltage comparison, according to the result of described comparison, the electric charge of the electric capacity by Voltage-output transistor gate described in clock signal control and charge pump distributes, to regulate the Voltage-output of described power circuit.
In some embodiments, electric charge between described charge pump and electric capacity distributes and comprises: when the voltage of described sampling is during higher than reference voltage, the electric charge of described Voltage-output transistor gate discharges to reduce output voltage to the electric capacity in described charge pump under described clock signal control, with when described sampled voltage is during lower than reference voltage, described electric capacity discharges electric charge to described Voltage-output transistor gate under described clock signal control, with boosted output voltages.
In some embodiments, also comprise, efficiently sampling is carried out in the output of the voltage signal by clock control signal control to described sampling and the comparative result of reference voltage, with only in the edge of described clock control signal output control signal.
According to above-mentioned aspect, for the ease of integrated and guarantee precision, the utility model adopts the digital filter that is operated in domain digital signal to replace the analog filter that is fully operational in simulating signal territory, the digital signal obtaining via the conversion of sampling device liking simulating signal of its processing.The signal that digital filter obtains, by control circuit regulating and controlling circuit, when builtin voltage is lower than target voltage (reference voltage), improves NMOS grid with one-level or more multistage charge pump and drives; When builtin voltage is higher than target voltage (reference voltage), NMOS gate charge is delivered to electric capacity, reduce NMOS gate drive voltage.
In order to eliminate the impact of noise in sheet, the utility model does not adopt NMOS or the PMOS driving tube structure of common amplifier control, but adopted the NMOS of digital control logic control to drive, because any low current amplifier is all difficult to the big ups and downs of opposing from power supply.When exceeding reference voltage, voltage reduces NMOS driving grid voltage, otherwise by high the grid voltage pump of NMOS driving tube.In the time that load strengthens, the gate source voltage of NMOS (VGS) strengthens automatically, can react rapidly and not rely on amplifier band width.
According to some embodiments, can add selector circuit at the sampled voltage input end of comparer, the digital signal of described control module output is connected in the output voltage sampling input end of described comparer by described selector circuit.Make control circuit can reduce the number of starts.For example, when the voltage of VDD is between 2.1v~2.3v, when the voltage of dividing point is near reference voltage, charge pump does not move; When the voltage of VDD is lower than 2.1v, when the voltage of dividing point is lower than reference voltage, grid charge pump improves driving tube grid voltage; When the voltage of VDD is higher than 2.3v, the transistorized grid capacitance of output voltage will be carried out electric charge reallocation to reduce the transistorized grid voltage of output voltage with an electric capacity.
Loop filtering circuit is to guarantee system stability.For the requirement of high speed peak values of ac electric current (AC peak current), gate source voltage strengthens the effect that has self feed back.Its beneficial effect is, faster than the LDO structural response speed that relies on loop amplifier, and building-out capacitor that need not be large, anti-power supply noise better effects if.
The charge pump that clock generating unit is voltage follower circuit provides phase place not overlapping clock.In some embodiments, circuit adopts feedback link to produce clock.
Output unit in present embodiment can be by the grid voltage of NMOS driving tube from default VDD1.2v~1.8v pump to 2.2v+Vtn, and controls through digital filter circuit and analog comparator in control module.
In some embodiments, in circuit, charge pump adopts two PMOS structures (also the size of output voltage is selected more multistage charge pump as required), unanimous between the higher and lower levels by the step that voltage rising/electric charge is distributed as the transistorized selection of electric capacity,, make the time of higher voltage return desired value and the time of voltage return desired value on the low side basically identical.Thus, also can make the comparatively balance of duty of circuit.
According to the utility model, in the time that output voltage V DD is too high, the transistorized gate charge of output voltage can be shared with the electric capacity in charge pump, and drags down driving tube grid potential realization adjusting.
Accompanying drawing explanation
Fig. 1 is according to the theory diagram of the mu balanced circuit of the utility model one embodiment;
Fig. 2 is the control module schematic diagram using in the mu balanced circuit shown in Fig. 1;
Fig. 3 is the clock generation circuit schematic diagram using in the mu balanced circuit shown in Fig. 1;
Fig. 4 is the output unit circuit theory diagrams that use in the mu balanced circuit shown in Fig. 1;
Fig. 5 is the key signal simulation waveform of the control module of the utility model embodiment;
Fig. 6 is the clock generation circuit simulation waveform of embodiment of the present utility model;
Fig. 7 is the simulation waveform of the key signal of the mu balanced circuit work of embodiment of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.
Simulation waveform figure when Fig. 1~6 have schematically shown according to the mu balanced circuit of a kind of embodiment of the present utility model and work thereof.
As shown in Figure 1, comprise control module 10 according to the mu balanced circuit of a kind of embodiment of the present utility model, it contains digital filter and comparer, clock generating unit 20, and output unit 30, the charge pump that it contains driving grid and for export regulate after the driving transistors circuit of voltage.Output unit 30 is offered the operating voltage VDD of external circuit work by line 130 outputs, the comparer that the signal of this operating voltage VDD sampling is inputed to control module 10 by line 100 is processed, as mentioned below.
The basic functional principle of the mu balanced circuit of this embodiment is: the operating voltage of exporting from line 130 voltage (inputing to the comparer of control module 10 by Fig. 2 center line 100) obtaining of sampling, with the reference voltage (shown in Fig. 2 center line 201) of input comparator relatively.When sampled voltage during higher than reference voltage output digit signals 120 effective, and when sampled voltage during lower than reference voltage output digit signals 110 effective.Under the control of output digit signals 110 and 120, produce corresponding clock signal 111,112,121 and the 122(digital signal controlled by clock generation circuit 20), the driving transistors circuit of four control clock signal control output units 30 produces and offers external circuit by line 130 output services voltage VDD and uses.
Figure 2 shows that the circuit theory diagrams of the control module 10 using in the mu balanced circuit shown in Fig. 1.As shown in the figure, this control module 10 comprises digital comparator COM21.INV22, INV25, INV26, INV210~INV214, INV218 are phase inverters, NAND23, NAND24, NAND215, NAND219 are two input nand gates, NAND216, NAND217 are three input nand gates, and DFF27, DFF28, DFF29, DFF220~DFF227 are d type flip flops.
As shown in Figure 2, M228, M229 are nmos devices, form the selection circuit in control module 10.In illustrated embodiment, the grid of nmos device M228, M229 is the signal (INV210 is anti-phase by phase inverter) of input inversion respectively, can select thus sampled signal via line 100 input comparators.Although the M228 that the input line of sampled signal shown in figure 100 connects, source electrode separately, the drain electrode of M229 are connected respectively, thereby do not play selection effect.But it will be understood by those skilled in the art that and sampled signal input line 100 can be made as to two, input to digital comparator COM21 via nmos device M228, M229 respectively.Nmos device M228, M229 connect respectively different supply voltage sampled points (as shown in the figure, the grid of nmos device M228, M229 is connected with input end and the output terminal of phase inverter INV210 respectively, thereby obtain the signal of single spin-echo), under suitable steering logic control, can reach circuit attonity within the scope of certain supply voltage.Can make like this circuit start can be very not frequent.
For example, make the turnover voltage that nmos device M228, M229 are corresponding different.For example, steering logic being set is that the corresponding turnover voltage of nmos device M228 is greater than the turnover voltage that nmos device M229 is corresponding.In the time that supply voltage is lower, effectively, in the time that nmos device M228 sampled voltage equals reference voltage (being that supply voltage equals the turnover voltage that nmos device M228 is corresponding), nmos device M229 sampling effectively in nmos device M228 sampling.But because the corresponding turnover voltage of nmos device M228 is greater than the turnover voltage that nmos device M229 is corresponding, until supply voltage drops to the turnover voltage that nmos device M229 is corresponding, circuit just judges that supply voltage is higher, wherein has one period of idle stage of circuit, and vice versa.
The sampled signal warp 100 of the operating voltage VDD of mu balanced circuit output compares by digital comparator COM21 with the reference voltage that warp 201 is inputted, and judges that operating voltage is higher or on the low side.In the time that supply voltage is higher, the 202 line output low levels of digital comparator COM21,203 line output high level; In the time that supply voltage is on the low side, the 202 line output high level of digital comparator COM21,203 line output low levels.
In figure the 304,305, the 306th, clock cable, from clock generation circuit 20.In the utility model, digital comparator COM21 inside comprises simulation rating unit and two parts of digital filtering.Simulation rating unit compares the size of sampled voltage and reference voltage.The output of the simulation rating unit of digital comparator COM21 enters by signal wire 305,306 and samples (being the digital filtering part in COM21) as the d type flip flop of clock, produces the signal on 202,203 lines.Specifically, this partial design only becomes the edge at 305,306 line clocks to carry out efficiently sampling to the output of simulation rating unit to export control signal, and the output of simulating At All Other Times rating unit is invalid.Thereby avoid transient pulse that the output of simulation part causes with interference and frequent fluctuation, mu balanced circuit work is more stable.
The signal warp 202 that digital comparator COM21 produces is exported effective digital signal to line 110 with the signal warp 205 that d type flip flop DFF29 produces by Sheffer stroke gate NAND23, phase inverter INV25 and d type flip flop DFF27.The waveform basically identical (referring to Fig. 5) of signal on line 110 and line 202.Digital comparator COM21 produce online 203 on signal and d type flip flop DFF29 generation online 206 on signal export effective digital signal to line 120 by Sheffer stroke gate NAND24, phase inverter INV26 and d type flip flop DFF28.When only signal is high on online 203, clock signal just on line 120.The out-of-phase signal producing by d type flip flop DFF29 for the signal on line 204 on line 205,206, is equivalent to the sampling to signal on line 204, the waveform similarity of signal on the signal waveform of line 205,206 and line 204, the just single spin-echo between line 205,206.Can form thus the sampling comparison that is subject to clock control on line 304.Signal on line 204 is for to produce by other combinational logics, so that only when signal on line 203 is that Gao Shicai has clock signal output.Wherein main signal line 202,203,204,304,110,120 waveforms are shown in Fig. 5.
Figure 3 shows that the schematic diagram of the clock generation circuit 20 using in the mu balanced circuit shown in Fig. 1.Wherein INV31, INV34~INV39, INV310~INV319, INV327, INV328, INV329 are phase inverters, NOR32, NOR33, NOR323, NOR326 are two input rejection gates, and NAND320, NAND321, NAND322, NAND324, NAND325 are two input nand gates.M330~M333, M336, M337 are PMOS transistors, and wherein M330, M331 use as electric capacity.M334, M335, M338, M339 are nmos pass transistors.310 represent clock input, obtain staggered inversion clock signal by the trigger structure being made up of NOR32, NOR33, INV34~INV39, INV310~INV319, M330, M331.The output signal of line 110,120 output digital filters 10, the digital controlled signal of line 111,112,121,122 output voltage regulation circuits.Line 310 is clock input signal, line 303,304 output out-phase clocks, line 305,306 output out-phase clocks.Between phase inverter INV312~316 and INV313~319, also can be connected as required output line, export similarly the clock of out-phase.
When sampled voltage is higher than reference voltage, only control signal wire 121,122 has signal output.When sampled voltage is during lower than reference voltage, each control signal wire 111,112,121,122 has signal output simultaneously.As shown in Figure 6, line 112 is consistent with 111 for the waveform of its center line 110,120,111,121, and line 122 and 121 output signals are anti-phase.
When line 110 is while being high, line 111,112 will be exported in-phase clock.Under rejection gate NOR326, phase inverter INV327 effect, as long as line 110 and 120 has high level signal, line 302 is just exported high level, line 301 and 302 signal inversion.Under online 301,302 the control of line 305,306, output signal to line 121,122.Line 121 is online 302 clock signals effectively time only.
Figure 4 shows that the schematic diagram of the output unit 30 using in the mu balanced circuit shown in Fig. 1, wherein R41, R42 represent resistance, M43, M45, M46, M47, M48 are PMOS devices, M44, M413, M414, M415 are nmos pass transistors, M49, M410, M411, M412, M424 are the PMOS transistors of electric capacity usage, and K416~K423 is optional switch.Whether optional switch major function is to select to need to connect according to the demand of circuit.In figure, optional switch has that line passes through for connecting, as K417, without line for disconnecting, as K416.This part, for mu balanced circuit provides electric capacity, can connect electric capacity according to the actual needs selection of circuit.Line 111,112,121,122 output clocks produce the control signal that circuit 20 provides.In figure, 401 represent external power source input, the supply voltage using in line 130 transmission circuits output, and 402 represent the other power supply output for some application of external circuit.
The following describes the processing mode of sampled voltage and reference voltage above-mentioned mu balanced circuit when inconsistent.
(1) when sampled voltage is during higher than reference voltage, the grid of nmos pass transistor M413, M414, M415 drives electric charge to reallocate with the electric charge of electric capacity PMOS pipe M46, as described below, make grid drive electric charge to reduce to reach the effect that reduces voltage in circuit.Wherein wired 121,122 signal functions only, it is high that line 111,112 is always.As PMOS pipe M46 one end 405 ground connection all the time of capacitance applications.
When line 121 be low, 122 for high, PMOS pipe M48 opens, metal-oxide-semiconductor M47 closes.Like this, the electric charge of PMOS pipe M46 can be released in circuit by M48, and the upper electric charge of metal-oxide-semiconductor M46 is reduced to some extent; When line 121 is that height, 122 is for low, metal-oxide-semiconductor M48 closes, metal-oxide-semiconductor M47 opens, because the charge discharging resisting of metal-oxide-semiconductor M46 cannot maintain initial line 410 voltages, the grid electric charge of metal-oxide-semiconductor M413 can be reallocated with the electric charge of metal-oxide-semiconductor M46, thereby reduce the grid driving voltage of M413, reduce the operating voltage VDD of 130 line outputs.
(2), when sampled voltage is during lower than reference voltage, the two PMOS charge pump work being made up of metal-oxide-semiconductor M43, M44, M46, M48 is to improve metal-oxide-semiconductor M413, the M414 on line 410, the gate drive voltage of M415.PMOS pipe M46 is as capacitance applications.
Specifically, when the sampled voltage on line 100 is during lower than reference voltage, line 111,112,122 output in-phase clocks, the clock out-phase of exporting with line 121.When line 111,112,122 is output as height, line 121 is output as when low, and PMOS pipe M43, M47 close, and NMOS pipe M44, M48 open, electric capacity (M46) charging; When line 111,112,122 is output as lowly, 121 are output as when high, and PMOS pipe M43, M47 open, and NMOS pipe M44, M48 close, and electric capacity (M46) electric charge is released nowhere, and both end voltage is poor to remain unchanged.Voltage on line 405 becomes VDD from 0, and the voltage on line 404 is high by pump, is transferred to the gate line 410 of driving tube M413, M414, M415 by metal-oxide-semiconductor M47, drives thereby strengthen, and improves the operating voltage VDD on 130 lines.
As shown in Figure 7, the embodiment of mu balanced circuit according to the above description, the principle of work of the mu balanced circuit in conjunction with simulation waveform to the above-mentioned embodiment of the utility model is described further.
When the sampled voltage on line 100 is during lower than reference voltage on line 201 (referring to region A), the line 110 in control circuit 10 is exported high level, line 120 output low levels, line 111, line 112, line 121 outputting charge pump clocks.Its center line 111 and line 112 homophases, line 111 and line 121 out-phase, the two PMOS charge pumps that consist of clock control transistor M43, M48 are by shown in line 404(Fig. 4) voltage pump is high.The transistor M47(that line 404 is controlled by clock output line 122 (shown in Fig. 4) is as switching tube) driving transistors M413 and M414.Because the grid voltage of transistor M413 and M414 uprises, directly improve the voltage that circuit voltage VDD(is line 130).The common connecting system power supply of its center line 401.
When the sampled voltage on line 100 is during higher than reference voltage on line 201 (referring to the region B in Fig. 7), line 110 output low levels of control module 10, line 120 output clocks.Line 111, line 112 are exported high level, export without clock.Now, the metal-oxide-semiconductor M46 using as electric capacity can maintain electric charge in the time there is no discharge path.
Line 122 is exported out-phase clock with line 121.When line 121 is low, line 122 when high, transistor M48 opens, M47 closes, and the electric charge of the transistor M46 of electric capacity usage is released to external circuit by line 130, and the electric charge on transistor M46 reduces simultaneously; When line 121 is that height, line 122 are for low, transistor M48 closes, M47 opens, due to the minimizing of the upper electric charge of the transistor M46 as electric capacity, the gate capacitance electric charge of metal-oxide-semiconductor M413, M414, M415 is to the upper reallocation of PMOS pipe M46 as electric capacity, thereby directly reduce the voltage on line 404, be the grid driving of nmos pass transistor thereby reduce line 410() voltage, and reduce thus the operating voltage of exporting.
Reach the stable of output services voltage by continuous execution said process.
Above-described is only embodiments more of the present utility model.For the person of ordinary skill of the art, without departing from the concept of the premise utility, can also make some distortion and improvement, these all belong to protection domain of the present utility model.

Claims (7)

1. mu balanced circuit, comprising:
Control module, comprises digital filter circuit and analog comparator, and the output voltage of described mu balanced circuit is sampled by described analog comparator and reference voltage comparison, and described control module is according to the result output control signal of described comparison;
Clock generating unit, exports corresponding clock signal according to described control signal; With
Output unit, comprises the output transistor of output services voltage and the charge pump of the described output transistor gates of driving,
Wherein, when described output voltage is during lower than reference voltage, described charge pump boosts to the grid of output transistor according to described clock signal; When described output voltage is during higher than reference voltage, the electric capacity of described charge pump carries out electric charge distribution according to described clock signal and output transistor gates, with by described output voltage step-down.
2. mu balanced circuit according to claim 1, wherein said analog comparator has output voltage sampled signal input end and reference voltage input, and the output terminal of described analog comparator is respectively by output digit signals after Sheffer stroke gate, phase inverter and trigger.
3. mu balanced circuit according to claim 2, also comprises selector circuit, and described digital signal is connected in the output voltage sampling input end of described comparer by described selector circuit.
4. mu balanced circuit according to claim 3, wherein said charge pump is two PMOS charge pumps, described electric capacity is made up of metal-oxide-semiconductor.
5. mu balanced circuit according to claim 4, wherein said output unit also comprises that the metal-oxide-semiconductor as electric capacity of multiple parallel connections is connected the switch of the described metal-oxide-semiconductor as electric capacity with selectivity.
6. according to the mu balanced circuit described in claim 1-5 any one, wherein said digital filter circuit comprises d type flip flop, the output of described analog comparator inputs to d type flip flop, described d type flip flop receives the clock signal from described clock generating unit, only at the edge of this clock signal, the output of described analog comparator is sampled, to export control signal.
7. mu balanced circuit according to claim 6, wherein said analog comparator and described digital filter circuit are integrated in individual digit comparer.
CN201320830722.0U 2013-12-12 2013-12-12 Voltage stabilizing circuit Withdrawn - After Issue CN203630657U (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103631304A (en) * 2013-12-12 2014-03-12 中国电子科技集团公司第四十七研究所 Voltage stabilization circuit
CZ305848B6 (en) * 2015-05-20 2016-04-06 AŽD Praha s.r.o. Apparatus for safe comparison of two computer systems
CN105786072A (en) * 2015-01-14 2016-07-20 旺宏电子股份有限公司 Low dropout regulator, regulation device and driving method thereof
CN106406408A (en) * 2016-11-18 2017-02-15 佛山科学技术学院 LDO (Low Dropout Regulator) circuit
CN108508958A (en) * 2018-05-10 2018-09-07 南方科技大学 A kind of pseudo- digital low pressure difference linear voltage regulator and power management chip
US10566892B1 (en) 2019-02-06 2020-02-18 Dialog Semiconductor (Uk) Limited Power stage overdrive extender for area optimization and operation at low supply voltage

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103631304A (en) * 2013-12-12 2014-03-12 中国电子科技集团公司第四十七研究所 Voltage stabilization circuit
CN103631304B (en) * 2013-12-12 2016-03-23 中国电子科技集团公司第四十七研究所 Mu balanced circuit
CN105786072A (en) * 2015-01-14 2016-07-20 旺宏电子股份有限公司 Low dropout regulator, regulation device and driving method thereof
CZ305848B6 (en) * 2015-05-20 2016-04-06 AŽD Praha s.r.o. Apparatus for safe comparison of two computer systems
CN106406408A (en) * 2016-11-18 2017-02-15 佛山科学技术学院 LDO (Low Dropout Regulator) circuit
CN108508958A (en) * 2018-05-10 2018-09-07 南方科技大学 A kind of pseudo- digital low pressure difference linear voltage regulator and power management chip
CN108508958B (en) * 2018-05-10 2020-02-07 南方科技大学 Pseudo-digital low dropout linear regulator and power management chip
US10566892B1 (en) 2019-02-06 2020-02-18 Dialog Semiconductor (Uk) Limited Power stage overdrive extender for area optimization and operation at low supply voltage

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