CN102290974B - DAC (Digital-to-Analog Converter) technology based novel soft start circuit and soft start method thereof - Google Patents
DAC (Digital-to-Analog Converter) technology based novel soft start circuit and soft start method thereof Download PDFInfo
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Abstract
The invention disclosed a DAC (Digital-to-Analog Converter) technology based novel soft start circuit and a soft start method thereof. The novel soft start circuit comprises a clock generation module, a digital signal generator, a binary switch, an R-2R trapezoidal resistance network and a soft start end control module. According to the novel soft start circuit disclosed by the invention, a soft start voltage with a rising trend from gentle to steep and then from steep to gentle is generated by adopting the clock generation module on the basis of the DAC technology; a quiescent current of a numerical part circuit is zero, and integral power consumption is controlled within 2n W, and therefore, energy is greatly saved and the requirements of development are met; the electrifying overshoot of an inductive current is inhibited within 1.3 A in the process of soft start, and therefore the requirements of a system are met; the rising process of an output voltage is stable, and therefore, oscillation is prevented from appearing and needed voltage values are fast and stably reached; the response time of a power management IC (Integrated Circuit) in a start stage is furthest shortened and controlled at about 200 microseconds; and the response speed of the integral system is greatly increased, and therefore a circuit is more suitable for a high-speed work environment.
Description
Technical field:
The invention belongs to field of switch power, the present invention relates to a kind of employing DAC (digital-to-analogue conversion) technology, provide the circuit of soft start function for the DC-DC Switching Power Supply.
Background technology:
Soft start circuit module is the important module of DC-DC switching power source chip.If there is no soft-start module, switching power circuit is in the process powered on, and surge current larger in inductance can directly be circulated in output capacitance, causes the overshoot of switch power source output voltage.The major function of soft starting circuit is exactly to make the DC-DC switching power source chip when powering on, and has avoided the output voltage overshoot, has caused the damage of chip components and parts.Early stage method is the soft start voltage by with current source, large capacitor charging being obtained rising on slope, the startup stage replace reference voltage by soft start voltage, thereby make the output voltage of chip finally reach stationary value along with soft start voltage rises gradually, make switch power supply system stably enter normal operating conditions, thereby reach the purpose of soft start.Although this method is simple and easy to use, need a soft start capacitor to control soft-start time, this electric capacity is often very large, can not be integrated on chip, and this will increase application area and application cost.The method of another kind of soft start is called current limiting method, by detecting the electric current on the switching tube in the DC-DC Switching Power Supply and being carried out the electric current of limit switch pipe by current comparison circuit, eliminates surge.Because current limit value generally is greater than the maximum of operating current, circuit start cause at the very start the overshoot of output with current limit value work meeting, the method that therefore generally by notch cuttype, increases current limit value realizes the soft start of circuit.But the shortcoming of this method is to increase current detecting and current comparison circuit, is not suitable for not having the switching power circuit of current limit function, and the switching of current limit value is not often very steady.Document Lu Jing, Wu Xiaobo, Shen Xuzhen, Qin Lin, " On-Chip Soft-start Cell for DC-DC Converter. " Proceedings of the International MultiConference of Engineers and Computer Scientists 2010 Vol II, IMECS 2010, March 17-19, 2010, Hong Kong. and document: Luo Peng. the design [D] of the BOOST type DC-DC transducer that adopts Peak Current Mode PWM to control. Xi'an: Xian Electronics Science and Technology University, 2010. in proposed two kinds based on DAC technology soft starting circuit, its basic principle is at first with frequency divider, the clock signal of input to be carried out to frequency division, obtain different digital controlled signal of a series of cycles, by DAC, these digital signals are changed into again to the reference voltage of simulation, thereby make to rise on the linear slope of reference voltage in the DC-DC Switching Power Supply, rise to the required voltage value through 128 steps by 0V, finally by one, start end signal soft start voltage is switched to the reference voltage in sheet, can effectively suppress the inductive current overshoot produced in DC-DC Switching Power Supply start-up course and can allow output voltage stabilization rise to load voltage value.The advantage of this method is to avoid using large external soft start capacitor, saved the I/O port of chip, reduced integrated circuit PCB area, and reduced cost, again owing to not needing current limit module and current comparator module, also be applicable to not have the switching power circuit of current limit function simultaneously.But, this soft starting circuit based on the DAC technology only provides a linear soft start reference voltage risen, and the time of rising is long, approximately that 1.5ms is to 2ms, thereby it is slow to cause the DC-DC switching power source chip to start, and can find out from actual emulation, in soft start-up process, output voltage waveforms is not also followed the ascendant trend rising of soft start voltage fully, but rise to again certain value fair even some decline always afterwards, this process can continue the long time, then output voltage continues to rise until the required voltage value again, output voltage maintain an equal level or the process of some decline in, the mean value of inductive current can be smaller, make inductive current that the phenomenon of zero passage be arranged, now whole DC-DC Switching Power Supply is operated under interrupting time conduction mode (DCM), can cause the drain terminal voltage of power tube to produce concussion, thereby reduced the efficiency of whole circuit in the soft start stage, cause the loss of energy.Defect for fear of this soft start, need to be analyzed soft start voltage ascendant trend and waveform, the primary study soft starting circuit starts the impact of waveform on output voltage rising waveform and inductive current, thereby need that invention is a kind of can be beneficial to the soft start stage of DC-DC Switching Power Supply by fast and stable most and enter the soft start voltage circuit of normal operating conditions, it can at utmost suppress the inductive current overshoot, controls output voltage stabilization and shorten start-up time, and very significantly saves circuit power consumption.
Summary of the invention:
For fear of using large external soft start capacitor and avoiding the application of soft starting circuit to be limited to the switching power circuit with current limit function, need to adopt the soft starting circuit based on the DAC technology, for fear of the soft starting circuit based on the DAC technology of aforementioned conventional, exist simultaneously drawback---soft-start time is long, the increase of soft start voltage linearity causes output voltage to rise to the operating voltage needed by fast and stable, in the soft start uphill process, the inductive current zero passage makes circuit working cause energy loss under the DCM pattern, need on traditional circuit base, be improved, by adopting a kind of clock generating module, the different phase risen in soft start voltage is regulated the frequency of clock signal, produce different soft start voltage waveforms, study the impact of different soft start voltage waveforms on output voltage and inductive current, final definite a kind of soft start voltage waveform that can suppress well inductive current overshoot and regulated output voltage.
The present invention proposes a kind of novel soft starting circuit based on the DAC technology, and produces a kind of soft start voltage waveform of output voltage fast and stable of the voltage-mode PWM control Boost type that is beneficial to most DC-DC converter relatively.
The novel soft starting circuit based on the DAC technology that the present invention proposes comprises: clock generating module, digital signal generator, binary switch, R-2R trapezoid resistance network and soft start finishing control module.
Described clock generating module is connected with the digital signal generator, under the control of three input control signal Control1, Control2, Control3, input had to clock signal clk that frequency is certain in the different phase of start-up course, change into frequency with the startup stage different and different clock signal New-type Clock, be input to the fs1 end of digital signal generation module.
Described digital signal generator and clock generating module, binary switch, soft start finishing control module is connected, the clock signal New-typeClock that will produce from the clock generating module, the d type flip flop chain that is fs1 by 7 two divided-frequencies carries out frequency division, the digital signal (the Q output of D01～D07) that controlled binary switch needs, select three output signal (D05 of d type flip flop chain simultaneously, D06, the Q output of D07), input control signal Control1 using these three feedback signals as the clock generating module, Control2, Control3, and d type flip flop chain afterbody output signal (the Q output of D08) is input to the end signal of soft start finishing control module as whole soft start-up process.
Described binary switch (SW01～SW07) is connected with digital signal generator, R-2R trapezoid resistance network, under the control of digital signal generator output signal (the Q output of D01～D08), determine the connected mode of resistance in the R-2R trapezoid resistance network, and then determine the resistance value of R-2R trapezoid resistance network.
Described R-2R trapezoid resistance network is connected with binary switch, completes the process that digital signal is converted to analog voltage.
Described soft start finishing control module is connected with the digital signal generator, end signal using afterbody output signal in the digital signal generator (the Q output of D08) as whole soft start-up process, by soft start finishing control module, by soft start voltage V
softswitch to reference voltage V
rEF, complete soft start-up process.
Described clock generating module comprises input port CLK end, Res end, Control1 end, Control2 end, Control3 end and output port New-type Clock end.Wherein Control1 end, Control2 end, Control3 end are connected with the Q end of d type flip flop D05, D06, D07 in the digital signal generator respectively; New-type Clock end is connected with fs1 in the digital signal generator.
Described digital signal generator comprises the Q end of input port Res end and New-type Clock end and output port d type flip flop D01～D08.Wherein New-type Clock end is connected with the fs1 in the clock generating module; The Q end of D01～D07 is connected with the EN end of binary switch (SW01～SW07).The Q end of d type flip flop D08 is connected to soft start finishing control module.
Described binary switch comprises EN end, X end, the Y end of SW01～SW07.Wherein, the EN end connects the Q end of d type flip flop D01～D07 in digital signal generator, and the X end connects an end of 2R resistance in the R-2R trapezoid resistance network.
The novel soft starting circuit based on the DAC technology of the present invention design, by adopting a kind of Novel clock signal generator module, generated ascendant trend by delaying suddenly, again by steep to slow soft start voltage.The present invention stablizes, improves aspect toggle speed in energy savings, inhibition overshoot, control system, and outstanding performance is arranged.As the part in power management IC, the present invention is based on the DAC technology, by adopting a kind of clock generating module, generated ascendant trend by delaying suddenly, again by steep to slow soft start voltage.Numerical portion circuit static electric current of the present invention is zero, and overall power is controlled in 2nW, greatly saves the energy, complies with development need.The present invention's overshoot that in soft start-up process, inductive current powered on is suppressed in 1.3A, meets system requirements; The output voltage uphill process is stable, has avoided the appearance of concussion, reaches fast and stably the required voltage value; And farthest shortened power management IC the startup stage response time, it is controlled in 200 μ s.Greatly improved the response speed of whole system, made circuit more adapt to high-speed operational environment.
The accompanying drawing explanation:
Fig. 1 is novel soft starting circuit overall structure block diagram;
Wherein: 1 is the clock generating module; 2 is the digital signal generator; 3 is binary switch; 4 is the R-2R trapezoid resistance network; 5 is soft start finishing control module.
The schematic diagram that Fig. 2 is digital signal generator in Fig. 1;
The schematic diagram that Fig. 3 (a) is binary switch in Fig. 1, (b) be the circuit symbol of binary switch;
Fig. 4 is R-2R ladder network current mode DAC circuit diagram in Fig. 1;
Fig. 5 is clock generating modular circuit schematic diagram in Fig. 1;
The simulation result figure that Fig. 6 is novel soft start voltage waveform;
Fig. 7 is the simulation result figure with the DC-DC converter of novel soft starting circuit;
Fig. 8 is the novel soft start voltage oscillogram after improving;
Fig. 9 is the simulation result figure with the DC-DC converter of novel soft starting circuit after improving;
The novel soft start voltage output waveform figure that Figure 10 obtains for test;
The novel soft starting circuit that Figure 11 obtains for test provides the oscillogram of soft start function for voltage-mode Boost DC-DC converter.
Embodiment:
Below in conjunction with accompanying drawing, the present invention is described in further detail:
Shown in Figure 1, a kind of novel soft starting circuit based on the DAC technology of the present invention comprises: clock generating module, digital signal generator, binary switch, R-2R trapezoid resistance network and soft start finishing control module, described clock generating module is connected with the digital signal generator, under the control of three input control signal Control1, Control2, Control3, by input have clock signal clk that frequency is certain the startup stage different time sections in, change into frequency with the startup stage different and different clock signal New-type Clock, be input to the fs1 end of digital signal generation module, described digital signal generator and clock generating module, binary switch, soft start finishing control module is connected, the clock signal New-type Clock that will produce from the clock generating module, the d type flip flop chain that is fs1 by 7 two divided-frequencies carries out frequency division, the digital signal (the Q output of D01～D07) that controlled binary switch needs, select three output signal (D05 of d type flip flop chain simultaneously, D06, the Q output of D07) fed back, input control signal Control1 as the clock generating module, Control2, Control3, and d type flip flop chain afterbody output signal (the Q output of D08) is input to the end signal of soft start finishing control module as whole soft start-up process, described binary switch (SW01～SW07) is connected with digital signal generator, R-2R trapezoid resistance network, under the control of digital signal generator output signal (the Q output of D01～D08), determine the connected mode of resistance in the R-2R trapezoid resistance network, and then determine the resistance value of R-2R trapezoid resistance network, described R-2R trapezoid resistance network is connected with binary switch, completes the process that digital signal is converted to analog voltage, described soft start finishing control module is connected with the digital signal generator, afterbody output signal in the digital signal generator (the Q output of D08) is input to soft start finishing control module, as the end signal of whole soft start-up process, by soft start voltage V
softswitch to reference voltage V
rEF, complete soft start-up process.
Digital signal generator wherein, shown in Fig. 2, the d type flip flop D01～D07 triggered with Protection Counter Functions by rising edge forms.F
s1signal passes through d type flip flop chain D01～D07 successively to fS1 signal two divided-frequency.Obtaining the cycle at the Q of D07 output after the d type flip flop frequency division of 7 two divided-frequencies is 128/f
s1square-wave signal.After chip power, the enable signal Res of circuit is to the d type flip flop zero clearing in module.Then the f inputted
s1signal after frequency division, just can be controlled the b that needs of soft start waveform
1, b
2..., b
7seven position digital signals, b
1～b
7in the rising edge generation saltus step of each clock, order, by 0000000,0000001, finally changes to 1111111 in time.Each railway digital signal is for controlling a binary switch.Simultaneously by digital signal b
5～b
7fed back, be input to the control end of MUX in the clock generating module as control signal Control1, Control2, Control3.
The binary switch schematic diagram, as shown in Figure 3.Wherein Fig. 3 (a) is inner schematic diagram.Seven binary switchs in Fig. 1 are respectively SW01, SW02 ..., SW07, binary switch is comprised of transmission gate, inverter and NMOS pipe, under the control of Enable Pin EN, makes output Y carry out gating between X and GND.Fig. 3 (b) is the circuit symbol of the binary switch of design.
The R-2R trapezoid resistance network realizes digital signal is converted to the process of analog signal.As shown in Figure 4, the R-2R trapezoid resistance network is comprised of R and two kinds of proportional resistance of 2R.Make when electric current flows to rightmost vertical 2R resistance from the 2R resistance on the left side, often through a 2R resistor current, reduce half.Therefore the electric current that flows through these 2R resistance can be expressed as:
V in formula (1)
rEFfor reference voltage, I
1, I
2..., I
7for flowing through the electric current of each resistance branch.
Under the control of supplied with digital signal 0 and 1, switch S
1, S
2..., S
7receive respectively and V
softposition, realized like this according to numeral input and the power electric current weighting changed, thereby realized the conversion of digital to analogy.
Final soft start output voltage can be expressed as:
(2)
In formula (2), K is R-2R resistor network scale factor, K=2 in the present invention, b
1, b
2..., b
7for digital controlled signal, V
rEFfor reference voltage.
Can be drawn output analog voltage V by formula (2)
softbe proportional to the digital controlled signal of input.
Above content is between inner each module of the soft start that designs of the present invention, to connect each other and every some work mode is simply introduced.Below operation principle and the circuit of novel soft starting circuit are realized being further described.
A. novel soft starting circuit operation principle
The linear reason risen of the output voltage of the aforesaid soft starting circuit based on the DAC technology is that soft start voltage is in the uphill process of 128 steps, each walks the required time (step time) and all equates, and by adopting the soft start end signal by soft start voltage V
softbe switched to reference voltage V
rEFrealize the end functions in soft start stage.
In order to change the soft start voltage waveform, need to effectively control the step time, make under prerequisite that soft start voltage is certain at the upper up voltage of each step, the step time changes.The step time is input signal f
s1cycle T
s1.If T
s1larger, in the process of soft start, output voltage rises gently, if T
s1less, the rising of soft start output voltage is precipitous, can be by adjusting T
s1produce one-period T
s1time dependent clock signal, thus the soft start output voltage waveforms of the different rates of rise obtained.Therefore, need a clock generating module to carry out time dependent clock signal f of generation cycle
s1.
The present invention has studied three kinds of soft start voltage waveforms---parabolic type, linear pattern, the performance of concave type aspect inhibition inductive current overshoot and control output voltage stabilization, find that the parabolic type reference voltage is in soft start first half section in the time, Performance Ratio is poor, suppress current over pulse not obvious, and very good within time soft start second half section, controlled well the stability of output voltage; Concave type reference voltage is advantageous in the soft start first half section time, suppresses the overshoot successful, but relatively is short of in time soft start second half section, and output voltage stability is inadequate; Linear pattern falls between, and there is no obvious advantage.
In order to reach relatively optimum circuit performance, the present invention determines to produce a kind of novel soft start voltage waveform, the first half section time at soft start rises with concave type trend, time second half section rises with parabolic type trend, thereby performance is suppressing inductive current overshoot and the advantage of controlling output voltage stabilization.
The present invention adopts the mode that soft start-up process is carried out to segmentation, by a clock generating module, allows input clock signal in the different time periods, is varied to the different cycles, is input to the input of digital signal generator.The soft start output voltage corresponding with the clock signal of different cycles, can, within the different time periods, rise with different slopes.The circuit diagram that Fig. 5 is the Novel clock signal generator module.The simulation result that Fig. 6 is soft starting circuit.Wherein, the soft start voltage waveform presents by gradual steep, then by abrupt change slow ascendant trend, and reach stable when 150 μ s.
Novel soft starting circuit of the present invention is controlled to Boost type DC-DC converter for starting resistor mould PWM, carry out emulation, result as shown in Figure 7.Soft start voltage V from top to bottom successively
soft, inductive current I
l, output voltage V
oUTthe temporal evolution waveform.From simulation result, can find out, the inductive current overshoot has obtained suppressing relatively fully, be controlled at the 2.8A left and right, and output voltage rises also enough gently, in 320 μ s left and right, has reached stable.No matter be the inhibition to current over pulse, or, to the control of stable output, all accomplished optimization, the novel soft start voltage waveform of the present invention aforesaid linear pattern soft start voltage waveform of comparing, have very large advantage.
B. the soft start voltage waveform of optimizing
As can see from Figure 7, when aforesaid soft starting circuit is used for starting the Boost circuit, the inductive current phenomenon of zero passage has for some time appearred, during this period of time, whole DC-DC Switching Power Supply is operated under interrupting time conduction mode (DCM), can cause the drain terminal voltage of power MOS pipe to produce concussion, thereby reduce whole circuit in the efficiency in soft start stage, cause larger energy loss.In order further to reduce zero-crossing timing, need to be improved soft starting circuit, by the frequency that improves clock in soft starting circuit, the method that shortens soft-start time, realize, Fig. 8 is improved soft start voltage waveform.
Improved soft start voltage being loaded into to the DC-DC converter and carrying out emulation, obtain the simulation result as Fig. 9, is soft start voltage V from top to bottom successively
soft, inductive current I
l, output voltage V
oUTthe temporal evolution waveform.From simulation result, can find out, the zero-crossing timing of inductive current is eliminated basically, and the landing of voltage does not appear in output voltage after overshoot, but, on the basis of the magnitude of voltage of overshoot, directly starts to rise, and finally when 250 μ s, reaches stationary value.The performance of this soft start voltage waveform, reach significantly and optimize.
C. the hardware of novel soft starting circuit is realized
Novel soft starting circuit of the present invention, based on the DAC technology, is comprised of simulation part and numerical portion, and the digital controlled signal of numerical portion is realized by FPGA, and the simulation part adopts discrete device to realize.
What Figure 10 showed is the test waveform after novel soft starting circuit hardware of the present invention is realized, can find out soft start voltage V
softfirst half in soft start-up process rises with the concave type, and latter half rises with parabolic type, finally reaches stable V
rEFafter, remain unchanged.The designing requirement according to the invention of the ascendant trend of soft start voltage.
Figure 11 is that novel soft starting circuit of the present invention is used to voltage-mode Boost DC-DC switching power circuit that the test waveform of soft start function is provided.From test result, can find out, soft start voltage rises to stationary value in 150 μ s, the zero-crossing timing of inductive current is eliminated basically, and the current over pulse at the beginning of powering on is suppressed in 1.3A, the landing of one point voltage has appearred in the Boost output voltage in uphill process, but do not cause the inductive current zero passage, finally in 200 μ s left and right, reach stationary value.The performance of novel soft starting circuit of the present invention, reach largely and optimize.
Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by submitted to claims.
Claims (6)
1. the novel soft starting circuit based on the DAC technology, is characterized in that: comprise clock generating module, digital signal generator, binary switch, R-2R trapezoid resistance network and soft start finishing control module, described digital signal generator is connected with clock generating module, binary switch and soft start finishing control module, described clock generating module is connected with the digital signal generator, described binary switch is connected with digital signal generator, R-2R trapezoid resistance network, described R-2R trapezoid resistance network is connected with binary switch, described soft start finishing control module is connected with the digital signal generator, described clock generating module comprises input port CLK end, the Res end, the Control1 end, the Control2 end, Control3 end and output port New-typ e Clock end, wherein Control1 holds, the Control2 end, Control3 end respectively with the digital signal generator in d type flip flop D05, D06, the Q end of D07 is connected, New-type Clock end is connected with fs1 end in the digital signal generator, described clock generating module is connected with the digital signal generator, at three input control signal Control1, Control2, under the control of Control3, by the input the clock signal clk with certain frequency the startup stage different time sections in, change into frequency with the startup stage different and different clock signal New-type Clock, be input to the fs1 end of digital signal generation module.
2. the novel soft starting circuit based on the DAC technology as claimed in claim 1, it is characterized in that: described digital signal generator and clock generating module, binary switch, soft start finishing control module is connected, will be from the clock signal New-typeClock of clock generating module input, the d type flip flop chain that is fs1 by 7 two divided-frequencies carries out frequency division, the digital signal needed at the controlled binary switch of the Q of d type flip flop D01～D07 output, simultaneously at D05, D06, three output signals that the Q output of D07 is selected the d type flip flop chain are respectively as the input control signal Control1 of clock generating module, Control2, Control3, and the Q output output signal of d type flip flop D08 is input to soft start finishing control module, end signal as whole soft start-up process.
3. the novel soft starting circuit based on the DAC technology as claimed in claim 1, it is characterized in that: described digital signal generator comprises the Q end of input port Res end and fs1 end and output port d type flip flop D01～D08, and wherein the fs1 end is connected with the New-type Clock end in the clock generating module; The Q end of D01～D07 is connected with the EN end of binary switch, and the Q end of d type flip flop D08 is connected to soft start finishing control module.
4. the novel soft starting circuit based on the DAC technology as claimed in claim 1, it is characterized in that: the EN end that described binary switch SW01～SW07 comprises, X end, Y end, wherein, the EN end connects the Q end of d type flip flop D01～D07 in digital signal generator, and the X end connects an end of 2R resistance in the R-2R trapezoid resistance network.
5. the soft-start method based on the described circuit of claim 1 is characterized in that:
Comprise clock generating module, digital signal generator, binary switch, R-2R trapezoid resistance network and soft start finishing control module, described clock generating module is connected with the digital signal generator, under the control of three input control signal Control1, Control2, Control3, by input have clock signal clk that frequency is certain the startup stage different time sections in, change into frequency with the startup stage different and different clock signal New-type Clock, be input to the fs1 end of digital signal generation module, described digital signal generator and clock generating module, binary switch, soft start finishing control module is connected, the clock signal fs1 that will input from the clock generating module carries out frequency division by the d type flip flop chain of 7 two divided-frequencies, the digital signal that controlled binary switch needs, select the input control signal Control1 of three output signals of d type flip flop chain as the clock generating module simultaneously, Control2, Control3, and d type flip flop chain afterbody output signal is input to soft start finishing control module, end signal as whole soft start-up process, described binary switch is connected with digital signal generator, R-2R trapezoid resistance network, under the control of digital signal generator output signal, determines the connected mode of resistance in the R-2R trapezoid resistance network, and then determines the resistance value of R-2R trapezoid resistance network, described R-2R trapezoid resistance network is connected with binary switch, completes the process that digital signal is converted to analog voltage, described soft start finishing control module is connected with the digital signal generator, using afterbody output signal in the digital signal generator as the end signal of whole soft start-up process, soft start voltage Vsoft is switched to VREF, completes soft start-up process.
6. the soft-start method of circuit as claimed in claim 5 is characterized in that:
Described clock generating module is connected with the digital signal generator, under the control of three input control signal Control1, Control2, Control3, by input have clock signal clk that frequency is certain the startup stage different time sections in, change into frequency with the different and different clock signal New-type Cloc of section start-up time, be input to the fs1 end of digital signal generation module;
Described digital signal generator and clock generating module, binary switch, soft start finishing control module is connected, the clock signal fs1 that will input from the clock generating module carries out frequency division by the d type flip flop chain of 7 two divided-frequencies, the digital signal that controlled binary switch needs, select three output signals of d type flip flop chain simultaneously, input control signal Control1 as the clock generating module, Control2, Control3, and by d type flip flop chain afterbody output signal, be input to soft start finishing control module, end signal as whole soft start-up process,
Described binary switch; Be connected with digital signal generator, R-2R trapezoid resistance network, under the control of digital signal generator output signal, determine the connected mode of resistance in the R-2R trapezoid resistance network, and then determine the resistance value of R-2R trapezoid resistance network;
Described R-2R trapezoid resistance network is connected with binary switch, completes the process that digital signal is converted to analog voltage;
Described soft start finishing control module is connected with the digital signal generator, by afterbody output signal in the digital signal generator, as the end signal of whole soft start-up process, by soft start voltage V
softswitch to V
rEF, complete soft start-up process;
Described clock generating module comprises input port CLK end, Res end, Control1 end, Control2 end, Control3 end and output port New-type Clock end, and wherein Control1 end, Control2 end, Control3 end are connected with the Q end of d type flip flop D05, D06, D07 in the digital signal generator respectively; New-type Clock end is connected with fs1 end in the digital signal generator;
Described digital signal generator comprises the Q end of input port Res end and fs1 end and output port d type flip flop D01～D08, and wherein New-type Clock end is connected with the fs1 end in the digital signal generator; The Q end of D01～D07 is connected with the EN end of binary switch, and the Q end of d type flip flop D08 is connected to soft start finishing control module;
Described binary switch comprises EN end, X end, the Y end of SW01～SW07, and wherein, the EN end connects the Q end of d type flip flop D01～D07 in digital signal generator, and the X end connects an end of 2R resistance in the R-2R trapezoid resistance network.
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|---|---|---|---|---|
| CN102810978A (en) * | 2012-08-28 | 2012-12-05 | 绍兴光大芯业微电子有限公司 | Double-electrode type soft starting control circuit structure |
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