CN103001480B - Soft starting circuit applied in buck type direct current (DC)-DC switch power supply - Google Patents
Soft starting circuit applied in buck type direct current (DC)-DC switch power supply Download PDFInfo
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- CN103001480B CN103001480B CN201210559144.1A CN201210559144A CN103001480B CN 103001480 B CN103001480 B CN 103001480B CN 201210559144 A CN201210559144 A CN 201210559144A CN 103001480 B CN103001480 B CN 103001480B
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Abstract
The invention discloses a soft starting circuit applied in a buck type direct current (DC)-DC switch power supply. The soft starting circuit mainly resolves the problem that overshoot voltage and surge current exist in the existing starting circuit, and static power consumption is too large. The starting circuit comprises a frequency converter circuit, a control circuit and a current-voltage conversion circuit. The first output end of the frequency converter circuit is connected with the control circuit to output a soft starting ending signal OVER, and the second output end of the frequency converter circuit si connected with a current-voltage conversion circuit to output digital signals F1-F7. The first output end of the control circuit is connected with the frequency converter circuit to output a clearing signal clr, the second output end and the third output end of the control circuit are connected with the current-voltage conversion circuit to respectively output a digital signal F8 and a digital signal XF8, and the current-voltage conversion circuit outputs voltage signals VSS. The soft starting circuit adopts the current-voltage conversion circuit, improves output voltage stability, reduces static power consumption, shortens domain area, reduces cost and can be used for simulating an integrated circuit.
Description
Technical field
The invention belongs to electronic circuit technology field, be particularly applied to the soft starting circuit in buck DC-DC Switching Power Supply, can be used for analog integrated circuit.
Background technology
In field of switch power, buck DC-DC is simple with it, and efficiently, the advantages such as low-power consumption are particularly suitable for Switching Power Supply, but there is surge current and overshoot voltage in the circuit start stage, damage internal structure and the external circuit thereof of its place chip.
With reference to Fig. 1, soft starting circuit comprises divider circuit and D/A converting circuit, the first input end of this divider circuit is connected with the reset signal clr of its place chip, second input of this divider circuit is connected with the clock signal clk of its place chip, eight outputs of this divider circuit are connected with D/A converting circuit respectively, export 8 position digital signal D0 ~ D7 respectively; The first input end of this D/A converting circuit is connected with the reference voltage signal VREF of its place chip, and the second input of this D/A converting circuit is connected with soft start end signal SS_OVER, the output output voltage signal V of this D/A converting circuit
sS; Divider circuit controls the clock signal clk of its place chip by the reset signal clr of its place chip, export conducting and shutoff that 8 position digital signal D0 ~ D7 control 8 switching tubes in digital-to-analogue conversion circuit respectively, when soft start end signal SS_OVER works, reference voltage signal VREF and soft start output voltage signal V
sSend value identical.
The shortcoming mainly soft start output voltage V of above-mentioned soft starting circuit
sSthe reference voltage V REF of its place chip can not be greater than; the reference voltage V REF being only applicable to its place chip compares as the input of error amplifier and the feedback voltage of its place chip; the reference voltage V REF being not suitable for its place chip compares as the input of PWM comparator and oblique wave compensation voltage and current sample voltage sum; and the output of error amplifier needs high clamp circuit to carry out high clamping protection; not only increase quiescent current and power consumption, and add chip area and cost.
Summary of the invention
The object of the present invention is to provide a kind of soft starting circuit be applied in buck DC-DC Switching Power Supply, prior art quiescent current is large to solve, power consumption is large, the problem that chip area is large and cost is high, simplifies the complexity of its place chip.
For achieving the above object, the present invention includes: divider circuit 1 and control circuit 2, the first output C of divider circuit 1 is connected with the first input end E of control circuit 2, exports softly to open end signal OVER; First output G of control circuit 2 is connected with the first input end B of divider circuit 1, export reset signal clr, it is characterized in that: the second output D of divider circuit 1 and the second output H of control circuit 2, the 3rd output M are connected to current-voltage conversion circuit 3, for output voltage signal V
sS;
Described current-voltage conversion circuit 3, comprises current source circuit 31, resistor network 32 and high clamp circuit 33, wherein:
Current source circuit 31, be provided with four inputs and three outputs, its first input end is as the first input end N of current-voltage conversion circuit 3, and be connected with the current source IREF of its place chip, its second input is as the second input K of current-voltage conversion circuit 3, and be connected with digital signal F1 ~ F7 that divider circuit 1 inputs, its the 3rd input is as the 3rd input J of current-voltage conversion circuit 3, and be connected with the digital signal F8 that control circuit 2 inputs, its four-input terminal is as the four-input terminal I of current-voltage conversion circuit 3, and be connected with the digital signal XF8 that control circuit 2 inputs, its first output is connected with resistor network 32, output current signal I1 ~ I7, its second output is connected with resistor network 32, output current signal I8, its the 3rd output is connected with high clamp circuit 33, output voltage signal V2,
Resistor network 32, be provided with two inputs and an output, its output is connected with high clamp circuit 33, output voltage signal V1;
High clamp circuit 33, be provided with two inputs and an output, its output is as the output L of current-voltage conversion circuit 3, output voltage signal V
sS.
As preferably, the current source circuit 31 of above-mentioned soft starting circuit, is connected to form by a 12 PMOS MP1 ~ MP12 and 11 NMOS tube MN1 ~ MN11, wherein:
9th NMOS tube MN9, the tenth NMOS tube MN10 and the 11 NMOS tube MN11, its grid is connected respectively and forms current-mirror structure, and its source electrode is connected respectively, and is connected to ground; The drain electrode of the 9th NMOS tube MN9 as the first input end N of current-voltage conversion circuit 3, and is connected with the current source IREF of its place chip; The drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the 12 PMOS MP12;
First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7 and the 12 PMOS MP12, its grid is connected respectively and forms current-mirror structure, its source electrode is connected respectively, and is connected with the supply voltage VIN of its place chip; The drain electrode of the first PMOS MP1 is connected with the drain electrode of the first NMOS tube MN1; The drain electrode of the second PMOS MP2 is connected with the drain electrode of the second NMOS tube MN2; The drain electrode of the 3rd PMOS MP3 is connected with the drain electrode of the 3rd NMOS tube MN3; The drain electrode of the 4th PMOS MP4 is connected with the drain electrode of the 4th NMOS tube MN4; The drain electrode of the 5th PMOS MP5 is connected with the drain electrode of the 5th NMOS tube MN5; The drain electrode of the 6th PMOS MP6 is connected with the drain electrode of the 6th NMOS tube MN6; The drain electrode of the 7th PMOS MP7 is connected with the drain electrode of the 7th NMOS tube MN7;
8th PMOS MP8, the 9th PMOS MP9 and the tenth PMOS MP10, its grid is connected respectively and forms current-mirror structure, and its source electrode is connected respectively, and is connected with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS MP8 is connected with the drain electrode of the 11 NMOS tube MN11; The drain electrode of the 9th PMOS MP9 is connected with the drain electrode of the 8th NMOS tube MN8; The drain electrode of the tenth PMOS MP10 as the 3rd output of current source circuit 31, output voltage signal V2;
11 PMOS MP11, its grid as the four-input terminal I of current-voltage conversion circuit 3, and is connected with the digital signal XF8 that control circuit 2 inputs, and its drain electrode is connected with the grid of the 7th PMOS MP7; Its source electrode is connected with the supply voltage VIN of its place chip;
First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7, seven railway digital signal F1 ~ F7 that its grid inputs with divider circuit 1 are respectively connected; Its source electrode exports seven road current signal I1 ~ I7 respectively;
8th NMOS tube MN8, its grid as the 3rd input J of current-voltage conversion circuit 3, and is connected with the digital signal F8 that control circuit 2 inputs, its source electrode as the second output of current source circuit 31, output current signal I8.
As preferably, the resistor network 32 of above-mentioned soft starting circuit, is connected to form by 19 resistance R1 ~ R19, wherein:
First resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7 connect be connected across the 18 resistance R18 between one end and ground, and the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 are connected with one end of the 7th resistance R7 is corresponding with seven road current signal I1 ~ I7 that current source circuit 31 inputs respectively;
12 resistance R12 and the 15 resistance R15 connect be connected across the 3rd resistance R3 between the other end and ground;
9th resistance R9 and the 8th resistance R8 connect be connected across the 4th resistance R4 between the other end and ground;
Tenth resistance R10 and the 11 resistance R11 connect be connected across the 5th resistance R5 between the other end and ground;
13 resistance R13 and the 14 resistance R14 connect be connected across the 6th resistance R6 between the other end and ground;
16 resistance R16 and the 17 resistance R17 connect be connected across the 7th resistance R7 between the other end and ground;
One end of 18 resistance R18 as the output of resistor network 32, output voltage signal V1; Between the other end that 19 resistance R19 is connected across the 18 resistance R18 and ground.
As preferably, the high clamp circuit 33 of above-mentioned soft starting circuit, comprises triode PNP1, the 20 resistance R20 and electric capacity C1;
Described triode PNP1, its base stage as the first input end of high clamp circuit 33, and is connected with the voltage signal V1 that resistor network 32 inputs; Its emitter-base bandgap grading as the second input of high clamp circuit 33, and is connected with the voltage signal V2 that current source circuit 31 inputs; Its collector electrode is connected to ground;
Described 20 resistance R20 and electric capacity C1 connect be connected across triode PNP1 between emitter-base bandgap grading and ground, the common port of the 20 resistance R20 and electric capacity C1 is as the output L of current-voltage conversion circuit 3, output voltage signal V
sS.
As preferably, the control circuit 2 of above-mentioned soft starting circuit, comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1;
Described rest-set flip-flop RS1, its input R as the first input end E of control circuit 2, and are connected with the soft end signal OVER that opens that divider circuit 1 inputs; Its input S as the second input F of control circuit 2, and is connected with the cut-off signals SHUT of its place chip; Its output Q is connected with the input of the first inverter I1;
The output of described first inverter I1, as the first output H of control circuit 2, is connected with the input of the second inverter I2, output digit signals F8; The output of the second inverter I2 is as the second output M of control circuit 2, output digit signals XF8;
Described NOR gate N1, its first input end is connected with the output of the first inverter I1; Its second input is connected with the cut-off signals SHUT of its place chip; Its output, as the 3rd output G of control circuit 2, exports reset signal clr.
The present invention compared with prior art has the following advantages:
1. the present invention is owing to adopting current-voltage conversion circuit, reduces overshoot voltage and surge current, improves the stability of output voltage.
2. the present invention owing to being provided with high clamp circuit in current-voltage conversion circuit, reduces quiescent current and power consumption, reduce cost, simplified the complexity of its place chip.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of traditional soft start-up circuit;
Fig. 2 is the structured flowchart of soft starting circuit of the present invention;
Fig. 3 is control circuit schematic diagram in Fig. 2;
Fig. 4 is the structured flowchart of current-voltage conversion circuit in Fig. 2;
Fig. 5 is the schematic diagram of Fig. 4.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
With reference to Fig. 2, soft starting circuit of the present invention comprises: divider circuit 1, control circuit 2 and current-voltage conversion circuit 3, wherein current-voltage conversion circuit 3 block diagram as shown in Figure 4, it comprises current source circuit 31, resistor network 32 and high clamp circuit 33, the first input end of this current source circuit 31 is as the first input end N of current-voltage conversion circuit 3, and be connected with the current source IREF of its place chip, second input of this current source circuit 31 is as the second input K of current-voltage conversion circuit 3, and be connected with digital signal F1 ~ F7 that divider circuit 1 inputs, 3rd input of this current source circuit 31 is as the 3rd input J of current-voltage conversion circuit 3, and be connected with the digital signal F8 that control circuit 2 inputs, the four-input terminal of this current source circuit 31 is as the four-input terminal I of current-voltage conversion circuit 3, and be connected with the digital signal XF8 that control circuit 2 inputs, first output of this current source circuit 31 is connected with resistor network 32, output current signal I1 ~ I7, second output of this current source circuit 31 is connected with resistor network 32, output current signal I8, 3rd output of this current source circuit 31 is connected with high clamp circuit 33, output voltage signal V2, the output of this resistor network 32 is connected with high clamp circuit 33, output voltage signal V1, the output of this high clamp circuit 33 is as the output L of current-voltage conversion circuit 3, output voltage signal V
sS, first output C of this divider circuit 1 is connected with the first input end E of control circuit 2, exports softly to open end signal OVER, first output G of control circuit 2 is connected with the first input end B of divider circuit 1, exports reset signal clr.
With reference to Fig. 3, control circuit 2 of the present invention, comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1, wherein:
Rest-set flip-flop RS1, its input R as the first input end E of control circuit 2, and are connected with the soft end signal OVER that opens that divider circuit 1 inputs; Its input S as the second input F of control circuit 2, and is connected with the cut-off signals SHUT of its place chip; Its output Q is connected with the input of the first inverter I1, the soft end signal OVER initial value that opens is low level, if when the cut-off signals SHUT of its place chip is high level, reset signal clr is low level, and divider circuit 1 does not work, after System recover normally works, cut-off signals SHUT is low, the R end of rest-set flip-flop is low level, and output remains unchanged, and cut-off signals SHUT and digital signal F8 inputs NOR gate by two makes frequency divider start working; When divider circuit 1 export soft to open end signal OVER be high level time, the R end of rest-set flip-flop is high level, and the output of rest-set flip-flop is low level, and digital signal F8 becomes high level makes reset signal clr be low level, turns off divider circuit 1;
First inverter I1, its output, as the first output H of control circuit 2, is connected with the input of the second inverter I2, output digit signals F8; The output of the second inverter I2 is as the second output M of control circuit 2, and output digit signals XF8, this digital signal F8 and digital signal XF8 are a pair inversion signals, for controlling the size of current in current source circuit 31;
NOR gate N1, its first input end is connected with the output of the first inverter I1; Its second input is connected with the cut-off signals SHUT of its place chip; Its output, as the 3rd output G of control circuit 2, exports reset signal clr.
With reference to Fig. 5, the current source circuit 31 in current-voltage conversion circuit 3 of the present invention, resistor network 32 and high clamp circuit 33, its circuit structure is as follows:
Described current source circuit 31, connected to form by 12 PMOS and 11 NMOS tube, i.e. the first PMOS MP1, second PMOS MP2, 3rd PMOS MP3, 4th PMOS MP4, 5th PMOS MP5, 6th PMOS MP6, 7th PMOS MP7, 8th PMOS MP8, 9th PMOS MP9, tenth PMOS MP10, 11 PMOS MP11, 12 PMOS MP12, first NMOS tube MN1, second NMOS tube MN2, 3rd NMOS tube MN3, 4th NMOS tube MN4, 5th NMOS tube MN5, 6th NMOS tube MN6, 7th NMOS tube MN7, 8th NMOS tube MN8, 9th NMOS tube MN9, tenth NMOS tube MN10 and the 11 NMOS tube MN11, wherein:
9th NMOS tube MN9, the tenth NMOS tube MN10 and the grid of the 11 NMOS tube MN11 are connected respectively and form current-mirror structure; 9th NMOS tube MN9, the tenth NMOS tube MN10 are connected respectively with the source electrode of the 11 NMOS tube MN11, and are connected to ground; The drain electrode of the 9th NMOS tube MN9 as the first input end N of current-voltage conversion circuit 3, and is connected with the current source IREF of its place chip; The drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the 12 PMOS MP12, and the 9th NMOS tube MN9, the tenth NMOS tube MN10 and the 11 NMOS tube MN11 provide reference current signal for current source circuit 31;
First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7 and the grid of the 12 PMOS MP12 are connected respectively and form current-mirror structure; First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7 are connected respectively with the source electrode of the 12 PMOS MP12, and are connected with the supply voltage VIN of its place chip; The drain electrode of the first PMOS MP1 is connected with the drain electrode of the first NMOS tube MN1; The drain electrode of the second PMOS MP2 is connected with the drain electrode of the second NMOS tube MN2; The drain electrode of the 3rd PMOS MP3 is connected with the drain electrode of the 3rd NMOS tube MN3; The drain electrode of the 4th PMOS MP4 is connected with the drain electrode of the 4th NMOS tube MN4; The drain electrode of the 5th PMOS MP5 is connected with the drain electrode of the 5th NMOS tube MN5; The drain electrode of the 6th PMOS MP6 is connected with the drain electrode of the 6th NMOS tube MN6; The drain electrode of the 7th PMOS MP7 is connected with the drain electrode of the 7th NMOS tube MN7, and the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7 is respectively seven articles of branch roads provides image current signal;
8th PMOS MP8, the 9th PMOS MP9 and the grid of the tenth PMOS MP10 are connected respectively and form current-mirror structure, 8th PMOS MP8, the 9th PMOS MP9 are connected respectively with the source electrode of the tenth PMOS MP10, and are connected with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS MP8 is connected with the drain electrode of the 11 NMOS tube MN11; The drain electrode of the 9th PMOS MP9 is connected with the drain electrode of the 8th NMOS tube MN8; The drain electrode of the tenth PMOS MP10 as the 3rd output of current source circuit 31, output voltage signal V2;
11 PMOS MP11, its grid as the four-input terminal I of current-voltage conversion circuit 3, and is connected with the digital signal XF8 that control circuit 2 inputs, and its drain electrode is connected with the grid of the 7th PMOS MP7; Its source electrode is connected with the supply voltage VIN of its place chip, and the 11 PMOS MP11 is as switching tube, and the digital signal XF8 inputted by control circuit 2 controls its turn-on and turn-off;
Seven railway digital signal F1 ~ F7 that first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 input with divider circuit 1 respectively with the grid of the 7th NMOS tube MN7 are connected; The source electrode of the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 exports seven road current signal I1 ~ I7 respectively, first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 are as switching tube, and digital signal F1 ~ F7 that the divider circuit 1 added by its grid inputs controls conducting and the shutoff of its switching tube;
8th NMOS tube MN8, its grid is as the 3rd input J of current-voltage conversion circuit 3, and be connected with the digital signal F8 that control circuit 2 inputs, its source electrode is as the second output of current source circuit 31, output current signal I8,8th NMOS tube MN8 is as switching tube, and the digital signal F8 inputted by control circuit 2 controls its turn-on and turn-off.
Described resistor network 32, connected to form by 19 resistance R1 ~ R19, i.e. the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the 11 resistance R11, the 12 resistance R12, the 13 resistance R13, the 14 resistance R14, the 15 resistance R15, the 16 resistance R16, the 17 resistance R17 the 18 resistance R18 and the 19 resistance R19, wherein:
First resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7 connect be connected across the 18 resistance R18 between one end and ground, and the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 are connected with one end of the 7th resistance R7 is corresponding with seven road current signal I1 ~ I7 that current source circuit 31 inputs respectively;
12 resistance R12 and the 15 resistance R15 connect be connected across the 3rd resistance R3 between the other end and ground;
9th resistance R9 and the 8th resistance R8 connect be connected across the 4th resistance R4 between the other end and ground;
Tenth resistance R10 and the 11 resistance R11 connect be connected across the 5th resistance R5 between the other end and ground;
13 resistance R13 and the 14 resistance R14 connect be connected across the 6th resistance R6 between the other end and ground;
16 resistance R16 and the 17 resistance R17 connect be connected across the 7th resistance R7 between the other end and ground;
One end of 18 resistance R18 as the output of resistor network 32, output voltage signal V1; Between the other end that 19 resistance R19 is connected across the 18 resistance R18 and ground;
Just start working the stage at soft starting circuit, divider circuit 1 does not work, the 8th PMOS MP8 by current-mirror structure by the current mirror on its branch road on the tenth PMOS MP10 branch road, triode PNP1 is worked, resistance R1 ~ R19 do not have electric current, voltage signal V
sSfor the emitter voltage V of triode PNP1
e; When the cut-off signals SHUT of its place chip is low level, divider circuit 1 is started working output digit signals F1 ~ F7, and controls conducting and the shutoff of the first NMOS tube MN1 in current-voltage conversion circuit 3 ~ the 7th NMOS tube.
Described high clamp circuit 33, comprises triode PNP1, the 20 resistance R20 and electric capacity C1, wherein:
Triode PNP1, its base stage as the first input end of high clamp circuit 33, and is connected with the voltage signal V1 that resistor network 32 inputs; Its emitter-base bandgap grading as the second input of high clamp circuit 33, and is connected with the voltage signal V2 that current source circuit 31 inputs; Its collector electrode is connected to ground;
20 resistance R20 and electric capacity C1 connect be connected across triode PNP1 between emitter-base bandgap grading and ground, the common port of the 20 resistance R20 and electric capacity C1 is as the output L of current-voltage conversion circuit 3, output voltage signal V
sS, after soft start terminates, voltage signal V
sSas the high clamp signal of soft starting circuit, improve the high efficiency of soft starting circuit.
Specific works principle of the present invention is as follows:
When soft starting circuit is just started working, the reset signal clr that control circuit 2 exports is high level, 7 position digital signal F1 ~ F7 that divider circuit 1 exports and the soft end signal OVER that opens are low level, after a clock signal clk, digital signal F1 becomes high level and all the other signals are low level, digital signal F7 ~ F1 is expressed as 0000001 according to binary mode, after second clock signal clk, first position digital signal F1 becomes low level, second-order digit signal F2 becomes high level and all the other signals are low level, digital signal F7 ~ F1 is expressed as 0000010 according to binary mode, after the 3rd clock signal clk, first position digital signal F1 and second-order digit signal F2 becomes high level and all the other digital signals are low level, digital signal F7 ~ F1 is expressed as 0000011 according to binary mode, after often crossing a clock signal clk, binary number adds 1, digital signal F7 ~ F1 represents from 0000000 by binary mode and changes to 1111111, when digital signal F7 ~ F1 binary mode is expressed as 1111111, again after a clock signal clk, the end signal OVER that divider circuit 1 exports is high level, digital signal F7 ~ F1 binary mode is expressed as 0000000, digital signal F7 ~ F1 controls the voltage signal V that current-voltage conversion circuit 3 exports
sSapproximately linear rises, and softly opens the reset signal clr that end signal OVER makes control circuit 2 export and becomes low level, shutoff divider circuit 1, after divider circuit 1 recovers normal work, cut-off signals SHUT is low level, the R end of rest-set flip-flop is low level, output remains unchanged, it is high level that cut-off signals SHUT and digital signal F8 inputs by two the soft end signal OVER that opens that NOR gate makes divider circuit 1 export, and the R end of rest-set flip-flop is high level, and the output of rest-set flip-flop is low level, digital signal F8 becomes high level makes reset signal clr be low level, turns off divider circuit 1, the voltage signal V that digital signal XF8 and digital signal F8 acting in conjunction make current-voltage conversion circuit 3 export
sSstable, soft start-up process terminates.If when cut-off signals SHUT is high level at any time, reset signal clr is low level, and turn off divider circuit 1, the output of rest-set flip-flop remains unchanged, then digital signal F8 and digital signal XF8 is also constant, the voltage signal V that current-voltage conversion circuit 3 exports
sSconstant, soft start-up process terminates, voltage signal V
sScan be used as high clamp signal.
Just start working the stage at soft starting circuit, divider circuit 1 does not work, the 8th PMOS MP8 in current-voltage conversion circuit 3 by current-mirror structure by the current mirror on its branch road on the tenth PMOS MP10 branch road, triode PNP1 is worked, resistance R1 ~ R19 does not have electric current, therefore output voltage is the emitter voltage V of triode PNP1
e; When cut-off signals SHUT is low level, the digital signal F1 that divider circuit 1 exports ~ F7 controls conducting and the shutoff of NMOS tube MN1 ~ MN7 in current-voltage conversion circuit 3.The 7 road electric currents that digital signal F1 ~ F7 controls correspond to I1 ~ I7 respectively, if the resistance of resistance first resistance R1 ~ the 19 resistance R19 identical be all R, equivalent by Dai Weinan, the output voltage V of current-voltage conversion circuit 3 in soft start-up process
sSfor:
Wherein V
bEfor the voltage difference between triode PNP1 emitter-base bandgap grading and base stage.
If the value of the electric current I 1 ~ I7 on the first PMOS MP1 ~ the 7th PMOS MP7 branch road is I
iN1, on the 9th NMOS tube MN9, the tenth NMOS tube MN10 and the 11 NMOS tube MN11 branch road, electric current is I
iN2, make I
iN1=I
iN2=I, according to conducting and shutoff that digital signal F1 ~ F7 controls the first NMOS tube MN1 ~ the 8th NMOS tube MN8, makes output voltage V
sSapproximately linear ladder rises, when through 127 all after date output voltage V
sSbe reduced to:
In formula, V
bEfor the voltage difference between triode PNP1 emitter-base bandgap grading and base stage.Again after a clock signal clk, the voltage of digital signal F7 ~ F1 becomes low level from high level, and the voltage of digital signal F8 becomes high level from low level, and the voltage of digital signal XF8 becomes low level from high level.The 11 PMOS MP11 conducting controlled now is held by digital signal XF8, the grid voltage of the first PMOS MP1 ~ the 7th PMOS MP7 and the 20 PMOS MP20 is driven high, digital signal F8 controls the 8th NMOS tube MN8 conducting, 2 times of current I flows through resistor networks 32, make output voltage rise again a ladder, then the output voltage of soft start by 128 all after dates is:
V
SS=2IR+V
BE
For guaranteeing the voltage signal V that soft starting circuit exports in temperature range
sSstable, the temperature coefficient of resistance in the resistance in resistance network and its place chip reference module is consistent.
Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously under design of the present invention, different changes and improvement can be carried out to its circuit, but these are all at the row of protection of the present invention.
Claims (4)
1. one kind is applied to the soft starting circuit in buck DC-DC Switching Power Supply, comprise divider circuit (1) and control circuit (2), first output C of divider circuit (1) is connected with the first input end E of control circuit (2), exports softly to open end signal OVER; First output G of control circuit (2) is connected with the first input end B of divider circuit (1), export reset signal clr, it is characterized in that: the second output D of divider circuit (1) and the second output H of control circuit (2), the 3rd output M are connected to current-voltage conversion circuit (3), for output voltage signal V
sS;
Described current-voltage conversion circuit (3), comprises current source circuit (31), resistor network (32) and high clamp circuit (33), wherein:
Current source circuit (31), be provided with four inputs and three outputs, its first input end is as the first input end N of current-voltage conversion circuit (3), and be connected with the current source IREF of its place chip, its second input is as the second input K of current-voltage conversion circuit (3), and be connected with digital signal F1 ~ F7 that divider circuit (1) inputs, its the 3rd input is as the 3rd input J of current-voltage conversion circuit (3), and be connected with the digital signal F8 that control circuit (2) inputs, its four-input terminal is as the four-input terminal I of current-voltage conversion circuit (3), and be connected with the digital signal XF8 that control circuit (2) inputs, its first output is connected with resistor network (32), output current signal I1 ~ I7, its second output is connected with resistor network (32), output current signal I8, its the 3rd output is connected with high clamp circuit (33), output voltage signal V2,
Current source circuit (31), is connected to form by a 12 PMOS MP1 ~ MP12 and 11 NMOS tube MN1 ~ MN11, wherein:
9th NMOS tube MN9, the tenth NMOS tube MN10 and the 11 NMOS tube MN11, its grid is connected respectively and forms current-mirror structure, and its source electrode is connected respectively, and is connected to ground; The drain electrode of the 9th NMOS tube MN9 as the first input end N of current-voltage conversion circuit (3), and is connected with the current source IREF of its place chip; The drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the 12 PMOS MP12;
First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7 and the 12 PMOS MP12, its grid is connected respectively and forms current-mirror structure, its source electrode is connected respectively, and is connected with the supply voltage VIN of its place chip; The drain electrode of the first PMOS MP1 is connected with the drain electrode of the first NMOS tube MN1; The drain electrode of the second PMOS MP2 is connected with the drain electrode of the second NMOS tube MN2; The drain electrode of the 3rd PMOS MP3 is connected with the drain electrode of the 3rd NMOS tube MN3; The drain electrode of the 4th PMOS MP4 is connected with the drain electrode of the 4th NMOS tube MN4; The drain electrode of the 5th PMOS MP5 is connected with the drain electrode of the 5th NMOS tube MN5; The drain electrode of the 6th PMOS MP6 is connected with the drain electrode of the 6th NMOS tube MN6; The drain electrode of the 7th PMOS MP7 is connected with the drain electrode of the 7th NMOS tube MN7;
8th PMOS MP8, the 9th PMOS MP9 and the tenth PMOS MP10, its grid is connected respectively and forms current-mirror structure, and its source electrode is connected respectively, and is connected with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS MP8 is connected with the drain electrode of the 11 NMOS tube MN11; The drain electrode of the 9th PMOS MP9 is connected with the drain electrode of the 8th NMOS tube MN8; The drain electrode of the tenth PMOS MP10 as the 3rd output of current source circuit (31), output voltage signal V2;
11 PMOS MP11, its grid as the four-input terminal I of current-voltage conversion circuit (3), and is connected with the digital signal XF8 that control circuit (2) inputs, and its drain electrode is connected with the grid of the 7th PMOS MP7; Its source electrode is connected with the supply voltage VIN of its place chip;
First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7, seven railway digital signal F1 ~ F7 that its grid inputs with divider circuit (1) are respectively connected; Its source electrode exports seven road current signal I1 ~ I7 respectively;
8th NMOS tube MN8, its grid is as the 3rd input J of current-voltage conversion circuit (3), and be connected with the digital signal F8 that control circuit (2) inputs, its source electrode as the second output of current source circuit (31), output current signal I8;
Resistor network (32), be provided with two inputs and an output, its output is connected with high clamp circuit (33), output voltage signal V1;
High clamp circuit (33), be provided with two inputs and an output, its output is as the output L of current-voltage conversion circuit (3), output voltage signal V
sS.
2. soft starting circuit according to claim 1, is characterized in that resistor network (32), is connected to form by 19 resistance R1 ~ R19, wherein:
First resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7 connect be connected across the 18 resistance R18 between one end and ground, and the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 are connected with one end of the 7th resistance R7 is corresponding with seven road current signal I1 ~ I7 that current source circuit (31) inputs respectively;
12 resistance R12 and the 15 resistance R15 connect be connected across the 3rd resistance R3 between the other end and ground;
9th resistance R9 and the 8th resistance R8 connect be connected across the 4th resistance R4 between the other end and ground;
Tenth resistance R10 and the 11 resistance R11 connect be connected across the 5th resistance R5 between the other end and ground;
13 resistance R13 and the 14 resistance R14 connect be connected across the 6th resistance R6 between the other end and ground;
16 resistance R16 and the 17 resistance R17 connect be connected across the 7th resistance R7 between the other end and ground;
One end of 18 resistance R18 as the output of resistor network (32), output voltage signal V1; Between the other end that 19 resistance R19 is connected across the 18 resistance R18 and ground.
3. soft starting circuit according to claim 1, is characterized in that high clamp circuit (33), comprises triode PNP1, the 20 resistance R20 and electric capacity C1;
Described triode PNP1, its base stage as the first input end of high clamp circuit (33), and is connected with the voltage signal V1 that resistor network (32) inputs; Its emitter-base bandgap grading as the second input of high clamp circuit (33), and is connected with the voltage signal V2 that current source circuit (31) inputs; Its collector electrode is connected to ground;
Described 20 resistance R20 and electric capacity C1 connect be connected across triode PNP1 between emitter-base bandgap grading and ground, the common port of the 20 resistance R20 and electric capacity C1 is as the output L of current-voltage conversion circuit (3), output voltage signal V
sS.
4. soft starting circuit according to claim 1, is characterized in that control circuit (2), comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1;
Described rest-set flip-flop RS1, its input R as the first input end E of control circuit (2), and are connected with the soft end signal OVER that opens that divider circuit (1) inputs; Its input S as the second input F of control circuit (2), and is connected with the cut-off signals SHUT of its place chip; Its output Q is connected with the input of the first inverter I1;
The output of described first inverter I1, as the first output H of control circuit (2), is connected with the input of the second inverter I2, output digit signals F8; The output of the second inverter I2 is as the second output M of control circuit (2), output digit signals XF8;
Described NOR gate N1, its first input end is connected with the output of the first inverter I1; Its second input is connected with the cut-off signals SHUT of its place chip; Its output, as the 3rd output G of control circuit (2), exports reset signal clr.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210559144.1A CN103001480B (en) | 2012-12-20 | 2012-12-20 | Soft starting circuit applied in buck type direct current (DC)-DC switch power supply |
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| CN201210559144.1A CN103001480B (en) | 2012-12-20 | 2012-12-20 | Soft starting circuit applied in buck type direct current (DC)-DC switch power supply |
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| CN103001480B true CN103001480B (en) | 2015-04-08 |
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| CN108769873B (en) * | 2018-05-23 | 2020-08-25 | 歌尔股份有限公司 | Signal switching circuit and electronic equipment |
| CN113904309B (en) * | 2021-10-15 | 2022-08-12 | 无锡力芯微电子股份有限公司 | Soft start circuit capable of suppressing surge current and overshoot voltage |
| CN116566368B (en) * | 2023-05-24 | 2024-07-12 | 韬润半导体(无锡)有限公司 | Switching circuit and multiplexer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217252A (en) * | 2008-01-04 | 2008-07-09 | 华中科技大学 | A soft start circuit for PDM DC-DC switching power supply |
| CN201191806Y (en) * | 2008-05-09 | 2009-02-04 | 华中科技大学 | Soft starting circuit for impulse-width modulating DC-DC switch power supply |
| CN101662206A (en) * | 2009-09-23 | 2010-03-03 | 上海导向微电子有限公司 | Soft start circuit, method and switch power supply circuit |
| CN102290974A (en) * | 2011-08-18 | 2011-12-21 | 西安交通大学 | DAC (Digital-to-Analog Converter) technology based novel soft start circuit and soft start method thereof |
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| US20070159264A1 (en) * | 2006-01-10 | 2007-07-12 | Samsung Electronics Co., Ltd. | Phase-locked loop with adaptive bandwidth |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217252A (en) * | 2008-01-04 | 2008-07-09 | 华中科技大学 | A soft start circuit for PDM DC-DC switching power supply |
| CN201191806Y (en) * | 2008-05-09 | 2009-02-04 | 华中科技大学 | Soft starting circuit for impulse-width modulating DC-DC switch power supply |
| CN101662206A (en) * | 2009-09-23 | 2010-03-03 | 上海导向微电子有限公司 | Soft start circuit, method and switch power supply circuit |
| CN102290974A (en) * | 2011-08-18 | 2011-12-21 | 西安交通大学 | DAC (Digital-to-Analog Converter) technology based novel soft start circuit and soft start method thereof |
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