CN106257812B - A kind of power management chip based on the COT control Buck circuits of two-phase containing flow equalizing function - Google Patents

A kind of power management chip based on the COT control Buck circuits of two-phase containing flow equalizing function Download PDF

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Publication number
CN106257812B
CN106257812B CN201610687539.8A CN201610687539A CN106257812B CN 106257812 B CN106257812 B CN 106257812B CN 201610687539 A CN201610687539 A CN 201610687539A CN 106257812 B CN106257812 B CN 106257812B
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pmos tube
module
grid
voltage
drain electrode
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CN106257812A (en
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赵梦恋
张书瑜
朱波
秦政
杨艺丹
董阳涛
吴晓波
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Zhejiang University ZJU
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Zhejiang University ZJU
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H02M1/143—Arrangements for reducing ripples from dc input or output using compensating arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H02M3/1586—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel switched with a phase shift, i.e. interleaved
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses a kind of power management chips based on the COT control Buck circuits of two-phase containing flow equalizing function, are equipped with power input foot, output voltage foot, grounding leg and two switch SW feet.Switching tube in chip internal reference circuit module, comparator module, Voltage loop module, clock generation module, control logic and soft-start module, constant on-time generation module, ripple compensation module, current sampling module, current balance module, drive module and four pieces.Power management chip of the present invention can efficiently overcome a variety of unsymmetrical factors to realize current balance, and precision is higher, can be operated under higher switching frequency, and compared with the traditional method of digital control matching duty cycle, energy loss is less, footprint area smaller.

Description

A kind of power management chip based on the COT control Buck circuits of two-phase containing flow equalizing function
Technical field
The invention belongs to technical field of integrated circuits, and in particular to one kind is based on COT control two-phases containing flow equalizing function Buck The power management chip of circuit.
Background technology
Power management class chip is the chip that power consumption management is carried out to each module in system, some power management chip meetings It is used for switching power circuit.Switching power circuit is all by the use of semiconductor power device as switch from being broadly defined as, by electricity Source Morphological Transitions become another form, the circuit that when transformation is exported with closed-loop stabilization is automatically controlled and had link of protection.Switch electricity Source circuit generally comprises control chip and peripheral circuit.The common topological structure of switching power circuit has：Buck chopper (Buck), Boost chopper (Boost), inverse-excitation type, positive activation type, half-bridge and full-bridge.The control mode of wherein Buck circuits includes：Sluggishness control System, constant on-time (COT) control, voltage type PWM control and current type PWM control etc..
When load needs more high current, converter can more use heterogeneous structure, and multiple branch circuit parallel connections are come to output End provides energy.Many times, heterogeneous structure are the working methods using phase alternation, and the switching frequency of each branch keeps one It causes, but phase staggers, and the frequency of output ripple then becomes switching frequency and is multiplied by circuitry number.Heterogeneous structure can simplify at this time Into the increased phase structure of switching frequency.Thus loop bandwidth can be greatly improved in the alternate heterogeneous structure of phase sequence, and then improves wink State response speed meets the requirement of large current load.Since each branch is required for power tube and inductance, so entire converter Switch block quantity can increase.List is from the point of view of efficiency, and there is no further promoted or even can brought more for heterogeneous structure More switching losses.But the maximum current that phase structure can be provided is often limited, the reliability of work is not also high；And multiphase Load current is evenly distributed to each branch by structure, output load current ability can be significantly greatly increased, while each branch is born Electric current will not be too high, functional reliability is ensured.But heterogeneous structure needs additional current equalization circuit, it is every to make The electric current of a branch is equal.
The two-phase Buck circuit structures of conventional digital control as shown in Figure 1, it uses the matched method of duty cycle to realize, Since the analog circuit that tradition generates duty cycle is very sensitive to the unsymmetrical factors of branch, in order to reach corresponding precision, it is necessary to adopt Matched duty cycle is generated with digital module.However, digital control can inevitably introduce quantization error, so as to cause not Good limit cycle；In addition, the High-accuracy direct current converter being operated under very high switching frequency needs high-resolution and high speed Digital PWM generator and analog-digital converter so can cause the loss of energy and the waste of area again.
The content of the invention
For the above-mentioned technical problem present in the prior art, contained the present invention provides one kind based on COT controls and flow work( The power management chip of energy two-phase Buck circuits, can be operated under higher switching frequency, overcome various unsymmetrical factors, will Load current is evenly distributed to each branch, avoid each phase current it is unequal cause it is single-phase loss it is excessive in addition influence work when Sequence, and relatively traditional digital control method energy loss is relatively low, footprint area is smaller.
A kind of power management chip based on the COT control Buck circuits of two-phase containing flow equalizing function, including：
Two switching branches, the switching branches include power switch pipe Mp and Mn；Wherein, the source of power switch pipe Mp Meet the input voltage V of circuitIN, the drain terminal of power switch pipe Mp phase electricity corresponding with the drain terminal and circuit of power switch pipe Mn One end of sense is connected, the source ground connection of power switch pipe Mn, and the other end of two phase inductances is parallel with one another in circuit；
Reference circuit module, in input voltage VINTo be that reference voltage V is provided in piece during high levelBG；
Ripple compensation module, the output voltage V of sample circuitOAnd two phase inductance and corresponding switching branches tie point Voltage, so as to generate reference voltage FB and two-way offset voltage RAMP1And RAMP2；
Voltage loop module, according to reference voltage FB and reference voltage VBGIt is compared, generates burning voltage VCON；
Current sampling module is sampled in two switching branches by current mirror Cycle by Cycle and flows through power switch pipe Mp's Current peak, it is corresponding to generate the current sample voltage VCS for being positively correlated with current peak1And VCS2；
Current balance module, according to current sample voltage VCS1And VCS2It is compared, the electric current for generating a pair of of difference is equal Weigh voltage VCB1And VCB2；
Two comparator modules, the comparator module have two pairs of positive inverting inputs, and letter is compared in output terminal generation Number；The positive inverting input of a pair of a wherein comparator module meets burning voltage V respectivelyCONWith offset voltage RAMP1, another pair Positive inverting input meets current balance voltage VCB respectively1And VCB2；The positive inverting input difference of a pair of another comparator module Meet burning voltage VCONWith offset voltage RAMP2, the positive inverting input of another pair meets current balance voltage VCB respectively2And VCB1；
Two constant on-time generation modules, the constant on-time generation module is according to corresponding comparator module Comparison signal generates ON time signal；
Two control logics and soft-start module, the control logic is with soft-start module according to corresponding constant on-time The ON time signal of generation module generates drive signal by control logic；
Two drive modules, the drive module make the drive signal power amplification of corresponding control logic and soft-start module Afterwards power switch pipe Mp and Mn in corresponding switching branches to be driven to carry out switch control.
The reference voltage FB is proportional to output voltage VODC component, offset voltage RAMP1AC compounent direct ratio In the AC compounent of a wherein phase inductance electric current, offset voltage RAMP2AC compounent be proportional to the friendship of another phase inductance electric current Flow component, offset voltage RAMP1And RAMP2DC component be equal to reference voltage FB.
For the constant on-time generation module when comparison signal is low level, generation ON time signal is just high electricity Flat and the high level pulsewidths constant, other times generation ON time signal is low level.
The control logic and soft-start module when closed between signal when being high level, generation drive signal is low electricity It is flat, when closed between signal when being low level, generation drive signal is high level.
The drive module makes it correspond to power switch pipe Mp in the switching branches of driving when drive signal is low level It is open-minded, power switch pipe Mn shut-offs；When drive signal is high level, it is made to correspond to power switch pipe in the switching branches of driving Mn is open-minded, power switch pipe Mp shut-offs.
The current balance module includes the trsanscondutance amplifier GM singly exported1, dual output differential type trsanscondutance amplifier GM2, capacitance C, OR gate, eight current source I1~I8, five switch S1~S5, four PMOS tube PM1~PM4, resistance R11~R12With R21~R22, three NMOS tube NM1~NM3, two rest-set flip-flop R1~R2, two phase inverter INV1~INV2, two delayers Delay1~Delay2, dual input three digit counter CA1With the counter CA of single input2；Wherein：Trsanscondutance amplifier GM1Just Phase input terminal and inverting input meet current sample voltage VCS respectively1And VCS2, trsanscondutance amplifier GM1Output terminal and capacitance C Top crown, switch S5One end and trsanscondutance amplifier GM2Inverting input be connected, the bottom crown of capacitance C ground connection, eight Current source I1~I8Input terminal meet supply voltage, current source I6Output terminal and trsanscondutance amplifier GM2Normal phase input end, Switch S5The other end and NMOS tube NM1Drain and gate be connected, NMOS tube NM1Source electrode ground connection, current source I1~I4's Output terminal is respectively with switching S1~S4One end be connected, switch S1~S4The other end and trsanscondutance amplifier GM2Positive output end, Resistance R11One end and PMOS tube PM1Grid be connected, resistance R11The other end ground connection, current source I5Output terminal and mutual conductance Amplifier GM2Reversed-phase output, resistance R12One end and PMOS tube PM2Grid be connected, resistance R12The other end ground connection, Current source I7Output terminal and PMOS tube PM1Source electrode and PMOS tube PM2Source electrode be connected, current source I8Output terminal with PMOS tube PM3Source electrode and PMOS tube PM4Source electrode be connected, PMOS tube PM3Grid and PMOS tube PM4Grid connect respectively Current sample voltage VCS1And VCS2, PMOS tube PM1Drain electrode and PMOS tube PM3Drain electrode, resistance R21One end and NMOS tube NM2Drain electrode be connected and generate current balance voltage VCB1, PMOS tube PM2Drain electrode and PMOS tube PM4Drain electrode, resistance R22's One end and NMOS tube NM3Drain electrode be connected and generate current balance voltage VCB2, resistance R21The other end and resistance R22It is another One end, NMOS tube NM2Grid and NMOS tube NM3Grid be connected, NMOS tube NM2Source electrode and NMOS tube NM3Source electrode connect Ground；Phase inverter INV1And INV2Input terminal connect the two-way drive signal of two control logics and soft-start module generation respectively, instead Phase device INV1Output terminal and delayer Delay1Input terminal and rest-set flip-flop R1R ends, phase inverter INV2Output terminal with Delayer Delay2Input terminal and rest-set flip-flop R2R ends, delayer Delay1Output terminal and rest-set flip-flop R1S ends It is connected, delayer Delay2Output terminal and rest-set flip-flop R2S ends be connected, rest-set flip-flop R1Output terminal and three digit counters CA1First input end and the first input end of OR gate be connected, rest-set flip-flop R2Output terminal and three digit counter CA1 Second input terminal of two input terminals and OR gate is connected, three digit counter CA1Three output terminals be respectively switch S1~S3It provides Switch controlling signal, output terminal and the counter CA of OR gate2Input terminal be connected, counter CA2Output terminal for switch S4It provides Switch controlling signal.
The current source I1~I5Output current size be respectively 1uA, 2uA, 4uA, 0.5uA and 4uA.
The three digit counters CA1With counter CA2Input terminal be rising edge triggering, wherein three digit counter CA1's First input end often receives a rising edge and adds 1, and the second input terminal often receives a rising edge and subtracts 1, three digit counter CA1Meter Numerical value bound is respectively 8 and 0；Counter CA2Count value be added to 8 after persistently export high level, otherwise export low level.
The comparator module includes a bias current sources, 12 PMOS tube P1~P12With seven NMOS tube N1~N7； Wherein：PMOS tube P1~P8Source electrode meet supply voltage, PMOS tube P1Grid and PMOS tube P2Grid, PMOS tube P1Leakage Pole, PMOS tube P3Grid and the input terminals of bias current sources be connected, the output head grounding of bias current sources, PMOS tube P2's Drain electrode and PMOS tube P9Source electrode and PMOS tube P10Source electrode be connected, PMOS tube P3Drain electrode and PMOS tube P11Source electrode and PMOS tube P12Source electrode be connected, PMOS tube P4Grid and PMOS tube P5Grid, PMOS tube P4Drain electrode and NMOS tube N3's Drain electrode is connected, PMOS tube P5Drain electrode and PMOS tube P6Grid and NMOS tube N4Drain electrode be connected, PMOS tube P6Drain electrode with PMOS tube P7Grid, NMOS tube N6Grid and NMOS tube N5Drain electrode be connected, PMOS tube P7Drain electrode and PMOS tube P8's Grid, NMOS tube N7Grid and NMOS tube N6Drain electrode be connected, PMOS tube P8Drain electrode and NMOS tube N7Drain electrode be connected simultaneously Generate comparison signal, PMOS tube P10Grid and PMOS tube P9Grid correspond to respectively comparator module the positive reverse phase of a pair it is defeated Enter end, PMOS tube P12Grid and PMOS tube P11Grid correspond to the positive inverting input of another pair of comparator module respectively, PMOS tube P9Drain electrode and NMOS tube N1Grid, NMOS tube N4Grid, PMOS tube P11Drain electrode and NMOS tube N1Drain electrode It is connected, PMOS tube P10Drain electrode and NMOS tube N2Grid, NMOS tube N3Grid, NMOS tube N5Grid, PMOS tube P12's Drain electrode and NMOS tube N2Drain electrode be connected, NMOS tube N1~N7Source grounding.
The PMOS tube P10Breadth length ratio and PMOS tube P12The ratio between breadth length ratio and PMOS tube P9Breadth length ratio and PMOS Pipe P11The ratio between breadth length ratio be 1:N, N are the real number more than 1.
The advantageous effects of power management chip of the present invention are as follows：
(1) current equalization circuit in the present invention, can be operated under higher switching frequency, overcome it is various it is asymmetric because The asymmetry of plain such as offset voltage, inductance, capacitance, resistance can realize the phase sequence alternating of quarter-phase circuit, after tested reliability It is very high, it is ensured that the stability of system improves lifetime of system.
(2) power management chip in the present invention possesses soft start function, improves system job stability, reduces and is System switching loss.
Description of the drawings
Fig. 1 is conventionally employed numerically controlled two-phase Buck electrical block diagrams.
Fig. 2 is the structure diagram of two-phase Buck circuit powers managing chip of the present invention and its peripheral circuit.
Fig. 3 is the electrical block diagram of current balance module of the present invention.
Fig. 4 is the electrical block diagram of comparator module of the present invention.
Fig. 5 is the work wave schematic diagram under DCM using the digital channel of current equalization circuit of the present invention.
Specific embodiment
In order to more specifically describe the present invention, below in conjunction with the accompanying drawings and specific embodiment is to technical scheme It is described in detail.
As shown in Fig. 2, power management chip of the present invention is used for high current Buck circuit occasions, power input foot is equipped with (Vin), output voltage foot (VO), grounding leg (GND) and two switch SW feet (SW1And SW2).Chip internal has reference circuit mould Block, comparator module, Voltage loop module, clock generation module, control logic and soft-start module, constant on-time generate mould Block, ripple compensation module, current sampling module, current balance module.Switching tube Mp in drive module and four pieces1、Mp2With Mn1、Mn2。
Power input foot (Vin), modules in access chip generate the power supply electricity of modules normal work in chip Position.Grounding leg (GND), modules in access chip generate the ground reference of modules normal work in chip.Switch SW feet (SW1And SW2), power switch pipe Mp is connected on respectively1、Mn1Between and Mp2、Mn2Between, level between sampled power switching tube, Level between switching tube is inputted into ripple compensation module simultaneously.Output voltage foot (VO), also ripple compensation module in access chip.Line Ripple compensating module generates compensation ripple (RAMP1And RAMP2) negative terminal of two branch comparators is inputted respectively, while also produce Raw voltage feedback signal (FB) is input to Voltage loop negative terminal.It is input to the benchmark that circuit module generates on the basis of Voltage loop anode Level (VBG), Voltage loop generates burning voltage (VCON) anode of two branch comparator modules is input to, it is mended respectively with two Repay ripple (RAMP1And RAMP2) compare.Current balance module receives the current value that two branch current sampling modules sample (VCS1And VCS2), generate current balance voltage (VCB1And VCB2), a pair of of the input for the two branch comparators that are added to respectively is just Negative terminal.Comparator module output access constant on-time generation module, while input going back for constant on-time generation module There is the clock signal (CLK) that clock generation circuit generates, constant on-time generation module generates fixed ON time signal, It is input to control logic and soft-start module.Two control logics are separately input to simultaneously also has switching signal with soft-start module (SW1And SW2), control logic generates output signal (D with soft-start module1And D2), it is separately input to the driving moulds of two branches Block generates switching tube Mp in two pieces in each branch of drive signal driving1、Mn1And Mp2、Mn2。
As the typical case of the chip, as shown in Fig. 2, external power supply voltage is via power input foot (Vin), access core Modules in piece generate the power supply potential of modules normal work in chip.External ground potential via grounding leg (GND), Modules in access chip generate the ground reference of modules normal work in chip.
Two switch SW feet (SW1 and SW2), are connected between power switch pipe Mp1, Mn1 between Mp2, Mn2, adopt respectively Level between sample power switch pipe, while level between switching tube is inputted into ripple compensation module and control logic and soft-start module.
Output voltage foot (VO) also ripple compensation module in access chip, ripple compensation module include ripple compensation electricity Road generates two compensation ripple (RAMP1And RAMP2) negative terminal of two comparator modules is respectively connected to, while also generate electricity Pressure feedback signal (FB) is input to the negative terminal of Voltage loop module；Wherein FB is proportional to output voltage VODC component, RAMP1's AC compounent is proportional to the AC compounent of inductance L1 electric currents, RAMP2AC ripple be proportional to the AC compounents of inductance L2 electric currents, RAMP1And RAMP2DC component be equal to reference voltage FB.
Reference circuit module is according to input voltage VinTo generate reference level (V during high levelBG) it is input to Voltage loop module Anode, Voltage loop module is defeated to generate burning voltage (VCON) be input to an anode of two comparator modules, respectively with compensation Ripple (RAMP1And RAMP2) compare.
Current sampling module flows through power switch pipe Mp by the sampling of current mirror Cycle by Cycle1、Mp2Current peak, generate It is positively correlated with the current sample voltage VCS of current peak1、VCS2。
Current balance module receives the current sample voltage (VCS that two branch current sampling modules sample1With VCS2), generate current balance voltage (VCB1And VCB2), a pair of of the input positive and negative terminal for the two branch comparators that are added to respectively.Such as Shown in Fig. 3, current balance modular circuit includes two two input comparator GM in present embodiment1And GM2, input to pipe GMSWith GMF, switch S1~S5, resistance R11、R12、R21And R22, capacitance C, eight current sources, wherein five be respectively 1uA, 2uA, 4uA, 0.5uA and 4uA and three NMOS；Wherein, VCS1And VCS2Current sampling data as two-phase branch is output to GM1With GMFInput terminal, GM1Output terminal and capacitance C and GM2Inverting input be connected, GM2Positive input connection current source It is grounded simultaneously through NMOS, the grid leak end short circuit of NMOS, switchs S5Connect GM2Two input terminals, switch S1~S4It connects respectively The current source of 1uA, 2uA, 4uA and 0.5uA, this four branch circuit parallel connections, endpoint in parallel connect GM2Positive output end and GMSInput End is simultaneously through resistance R11Ground connection, GMSAnother input terminal connection GM2Negative output terminal and 4uA current source simultaneously through resistance R12 Ground connection, GMSThe drain terminal of two PMOS be grounded respectively through NMOS, the grid end of the two NMOS is connected, resistance R21、R22Respectively By GMSThe drain terminal of two PMOS is connected with NMOS grid ends, GMSIn two PMOS drain terminals and GMFIn two PMOS drain terminal difference It is connected, tie point difference extracted current signal VCB1、VCB2。
Comparator module (using four input comparators, differential difference amplifier), two pairs Forward and reverse input terminal, a pair are current balance voltage VCB1、VCB2, a pair is compensation ripple RAMP1(or RAMP2) and stablize electric Press VCON, so as to generate comparison signal ON1、ON2；As shown in figure 4, comparator module has used two groups of inputs pair in present embodiment Pipe GM1And GM2, one group of (GM1) give compensation ripple signal RAMP1(or RAMP2) and burning voltage VCONIt uses, another group of (GM2) give Current balance voltage signal VCB1And VCB2It uses, structure uses common dual-stage amplifier, wherein GM1/GM2=N/1 (N>1), It is equivalent to pipe GM2Input signal conversion to GM1Input terminal after, only original N/mono-.
Comparator module output access constant on-time generation module, while input constant on-time generation module The clock signal (CLK) that also clock generation circuit generates, constant on-time generation module generate fixed ON time letter Number, it is input to control logic and soft-start module.Two control logics are separately input to simultaneously also has switch with soft-start module Signal (SW1And SW2),
Control logic generates output signal (D with soft-start module1And D2), drive module is input to, drive signal is generated and drives Switching tube Mp1, Mn1 and Mp2, Mn2 in two pieces in each branch are moved, realizes the conversion and transmission of electric energy.Comparison signal ON1 Or ON2For low level when, the ON time signal of the constant on-time generation module generation of that corresponding phase is just high level Triggering and the pulsewidths constant of the high level, other times are low level.
The current balance module of present embodiment includes fast passage and slow channel, as shown in Figure 3.It is fast on the right side of Fig. 3 In passage, the current sampling data (VCS of two branches1And VCS2) through inputting to pipe GMFWith resistance R21、R22Difference ripple is changed into, It is directly superimposed to the input terminal of comparator.Slow channel on the left of Fig. 3 is divided into as analog channel and digital channel.Wherein, simulation is logical Road is by current sampling data (VCS1And VCS2) through comparator GM1Obtain current differential information, then through capacitance C low-pass filtering, then By comparator GM2With resistance R11、R12Transformation of scale, most afterwards through input to pipe GMSIt is together in parallel with fast passage, in resistance R21、R22Upper generation difference ripple；Digital channel is then the electric current for adjusting current array, in resistance R21、R22Upper generation difference line Ripple.The ripple that fast passage and slow channel generate is in resistance R21、R22Upper superposition obtains final difference ripple VCB1And VCB2, it is defeated Go out the input terminal to comparator.Switch S4It is in order to which the asymmetric offset voltage of comparator to be set in the centre of a gear Value.When comparator asymmetry offset voltage is zero, two branches can be open-minded simultaneously, and then only opens wherein one in the next cycle Road.In addition, switch S5A period of time can be opened when flow equalizing circuit is opened, to GM1The output of~C low-pass filters provides initial value.
For current balance mould slow channel in the block, wherein digital channel is equivalent to coarse adjustment, and analog channel is equivalent to fine tuning. If binary system has been carried out phase sequence alternating, then digital channel will not work, and analog channel then can gradually subtract The influence of few offset voltage.Because binary system generally also achieves phase sequence and staggers in when being continuously turned on state.Herein with disconnected It is introduced exemplified by continuous working condition, groundwork sequential is as shown in Figure 5：
(1) when output declines, first is mutually open-minded, and counter receives a rising pulses, exports Q [2:0] add 1, flow through R11Electric current increase, VCB1It reduces and VCB2Increase, be equivalent to and negative offset voltage is superimposed on the comparator of the first phase, second Positive offset voltage is superimposed in phase, so that the first phase is more difficult to open and the second phase is easily open-minded；
(2) if output voltage declines again, second meets open-minded, and counter receives a falling pulse, exports Q [2: 0] subtract 1, flow through R11Electric current reduce, VCB1Increase and VCB2It reduces, is equivalent to and positive imbalance is superimposed on the comparator of the first phase Voltage is superimposed negative offset voltage in the second phase so that the first phase be easier to open and the second phase be more difficult to it is open-minded；
(3) when output voltage declines again, take turns to first mutually open-minded, then be the second phase, cycle successively, it is achieved thereby that Phase sequence staggers.Finally, the Q [2 of digital channel:0] saltus step in a gear, i.e. Q0 constantly jumps to 1 from 0, then jumps to 0 from 1.
Offset voltage waveform in wherein Fig. 5 is switch S4Effect --- the asymmetric offset voltage of comparator is set In the median of a gear, when to avoid comparator asymmetry offset voltage be zero, two branches can be open-minded simultaneously, and next Cycle then only opens wherein all the way.So the present invention proposes corresponding half value modification circuit, the lower left corner of Fig. 3 is seen, if continuously Detect two branches while eight cycles, then the carry flag of counter can jump 1, switch S4It is open-minded, by two comparators Asymmetric offset voltage be arranged to the median of a gear.Next, the offset voltage adjustment of digital channel can be achieved with Normal positive and negative saltus step.If the initial asymmetric offset voltage of two comparators can realize two branch in median Road phase sequence staggers, then switch S4It is still kept off.
The above-mentioned description to embodiment is understood that for ease of those skilled in the art and using the present invention. Person skilled in the art obviously can easily make above-described embodiment various modifications, and described herein general Principle is applied in other embodiment without having to go through creative labor.Therefore, the invention is not restricted to above-described embodiment, abilities Field technique personnel announcement according to the present invention, the improvement made for the present invention and modification all should be in protection scope of the present invention Within.

Claims (10)

1. a kind of power management chip based on the COT control Buck circuits of two-phase containing flow equalizing function, which is characterized in that including：
Two switching branches, the switching branches include power switch pipe Mp and Mn；Wherein, the source of power switch pipe Mp connects electricity The input voltage V on roadIN, the drain terminal of a power switch pipe Mp phase inductance corresponding with the drain terminal and circuit of power switch pipe Mn One end is connected, the source ground connection of power switch pipe Mn, and the other end of two phase inductances is parallel with one another in circuit；
Reference circuit module, in input voltage VINTo be that reference voltage V is provided in piece during high levelBG；
Ripple compensation module, the output voltage V of sample circuitOAnd two phase inductance and corresponding switching branches tie point voltage, So as to generate reference voltage FB and two-way offset voltage RAMP1And RAMP2；
Voltage loop module, according to reference voltage FB and reference voltage VBGIt is compared, generates burning voltage VCON；
Current sampling module samples the electric current that power switch pipe Mp is flowed through in two switching branches by current mirror Cycle by Cycle Peak value, it is corresponding to generate the current sample voltage VCS for being positively correlated with current peak1And VCS2；
Current balance module, according to current sample voltage VCS1And VCS2It is compared, generates the current balance electricity of a pair of of difference Press VCB1And VCB2；
Two comparator modules, the comparator module have two pairs of positive inverting inputs, and output terminal generates comparison signal；Its In the positive inverting input of a pair of a comparator module meet burning voltage V respectivelyCONWith offset voltage RAMP1, the positive reverse phase of another pair Input terminal meets current balance voltage VCB respectively1And VCB2；The positive inverting input of a pair of another comparator module connects stabilization respectively Voltage VCONWith offset voltage RAMP2, the positive inverting input of another pair meets current balance voltage VCB respectively2And VCB1；
Two constant on-time generation modules, the constant on-time generation module is according to the comparison for corresponding to comparator module Signal generation ON time signal；
Two control logics and soft-start module, the control logic are generated with soft-start module according to corresponding constant on-time The ON time signal of module generates drive signal by control logic；
Two drive modules, the drive module are used after making the drive signal power amplification of corresponding control logic and soft-start module Switch control is carried out with power switch pipe Mp and Mn in the corresponding switching branches of driving.
2. power management chip according to claim 1, it is characterised in that：The reference voltage FB is proportional to output electricity Press VODC component, offset voltage RAMP1AC compounent be proportional to the AC compounent of a wherein phase inductance electric current, compensation electricity Press RAMP2AC compounent be proportional to the AC compounent of another phase inductance electric current, offset voltage RAMP1And RAMP2DC component It is equal to reference voltage FB.
3. power management chip according to claim 1, it is characterised in that：The constant on-time generation module when than When compared with signal being low level, generation ON time signal is just high level and the pulsewidths constant of the high level, and other times generate ON time signal is low level.
4. power management chip according to claim 1, it is characterised in that：The control logic is worked as with soft-start module to be led When logical time signal is high level, generation drive signal is low level, when closed between signal when being low level, generation driving is believed Number be high level.
5. power management chip according to claim 1, it is characterised in that：The drive module is low electricity when drive signal Usually, corresponding to it, power switch pipe Mp in switching branches of driving is open-minded, and power switch pipe Mn is turned off；When drive signal is height During level, corresponding to it, power switch pipe Mn in switching branches of driving is open-minded, and power switch pipe Mp is turned off.
6. power management chip according to claim 1, it is characterised in that：The current balance module includes single export Trsanscondutance amplifier GM1, dual output differential type trsanscondutance amplifier GM2, capacitance C, OR gate, eight current source I1~I8, five open Close S1~S5, four PMOS tube PM1~PM4, resistance R11~R12And R21~R22, three NMOS tube NM1~NM3, two rest-set flip-flops R1~R2, two phase inverter INV1~INV2, two delayer Delay1~Delay2, dual input three digit counter CA1And list The counter CA of input2；Wherein：Trsanscondutance amplifier GM1Normal phase input end and inverting input connect current sample voltage respectively VCS1And VCS2, trsanscondutance amplifier GM1Output terminal and capacitance C top crown, switch S5One end and trsanscondutance amplifier GM2's Inverting input is connected, the bottom crown ground connection of capacitance C, eight current source I1~I8Input terminal meet supply voltage, current source I6 Output terminal and trsanscondutance amplifier GM2Normal phase input end, switch S5The other end and NMOS tube NM1Drain and gate phase Even, NMOS tube NM1Source electrode ground connection, current source I1~I4Output terminal respectively with switch S1~S4One end be connected, switch S1~ S4The other end and trsanscondutance amplifier GM2Positive output end, resistance R11One end and PMOS tube PM1Grid be connected, resistance R11The other end ground connection, current source I5Output terminal and trsanscondutance amplifier GM2Reversed-phase output, resistance R12One end and PMOS tube PM2Grid be connected, resistance R12The other end ground connection, current source I7Output terminal and PMOS tube PM1Source electrode and PMOS tube PM2Source electrode be connected, current source I8Output terminal and PMOS tube PM3Source electrode and PMOS tube PM4Source electrode be connected, PMOS tube PM3Grid and PMOS tube PM4Grid meet current sample voltage VCS respectively1And VCS2, PMOS tube PM1Drain electrode with PMOS tube PM3Drain electrode, resistance R21One end and NMOS tube NM2Drain electrode be connected and generate current balance voltage VCB1, PMOS Pipe PM2Drain electrode and PMOS tube PM4Drain electrode, resistance R22One end and NMOS tube NM3Drain electrode be connected and generate current balance Voltage VCB2, resistance R21The other end and resistance R22The other end, NMOS tube NM2Grid and NMOS tube NM3Grid phase Even, NMOS tube NM2Source electrode and NMOS tube NM3Source electrode ground connection；Phase inverter INV1And INV2Input terminal connect two controls respectively The two-way drive signal of logical AND soft-start module generation, phase inverter INV1Output terminal and delayer Delay1Input terminal with And rest-set flip-flop R1R ends be connected, phase inverter INV2Output terminal and delayer Delay2Input terminal and rest-set flip-flop R2's R ends are connected, delayer Delay1Output terminal and rest-set flip-flop R1S ends be connected, delayer Delay2Output terminal and RS trigger Device R2S ends be connected, rest-set flip-flop R1Output terminal and three digit counter CA1First input end and OR gate first input End is connected, rest-set flip-flop R2Output terminal and three digit counter CA1The second input terminal and the second input terminal of OR gate be connected, Three digit counter CA1Three output terminals be respectively switch S1~S3Switch controlling signal, the output terminal and counter of OR gate are provided CA2Input terminal be connected, counter CA2Output terminal for switch S4Switch controlling signal is provided.
7. power management chip according to claim 6, it is characterised in that：The current source I1~I5Output current it is big Small is respectively 1uA, 2uA, 4uA, 0.5uA and 4uA.
8. power management chip according to claim 6, it is characterised in that：The three digit counters CA1With counter CA2 Input terminal be rising edge triggering, wherein three digit counter CA1First input end often receive a rising edge and add 1, second Input terminal often receives a rising edge and subtracts 1, three digit counter CA1Count value bound be respectively 8 and 0；Counter CA2Meter Numerical value persistently exports high level after being added to 8, otherwise export low level.
9. power management chip according to claim 1, it is characterised in that：The comparator module includes a biased electrical Liu Yuan, 12 PMOS tube P1~P12With seven NMOS tube N1~N7；Wherein：PMOS tube P1~P8Source electrode connect supply voltage, PMOS tube P1Grid and PMOS tube P2Grid, PMOS tube P1Drain electrode, PMOS tube P3Grid and bias current sources it is defeated Enter end to be connected, the output head grounding of bias current sources, PMOS tube P2Drain electrode and PMOS tube P9Source electrode and PMOS tube P10's Source electrode is connected, PMOS tube P3Drain electrode and PMOS tube P11Source electrode and PMOS tube P12Source electrode be connected, PMOS tube P4Grid With PMOS tube P5Grid, PMOS tube P4Drain electrode and NMOS tube N3Drain electrode be connected, PMOS tube P5Drain electrode and PMOS tube P6 Grid and NMOS tube N4Drain electrode be connected, PMOS tube P6Drain electrode and PMOS tube P7Grid, NMOS tube N6Grid and NMOS tube N5Drain electrode be connected, PMOS tube P7Drain electrode and PMOS tube P8Grid, NMOS tube N7Grid and NMOS tube N6's Drain electrode is connected, PMOS tube P8Drain electrode and NMOS tube N7Drain electrode be connected and generate comparison signal, PMOS tube P10Grid and PMOS tube P9Grid correspond to the positive inverting input of a pair of comparator module, PMOS tube P respectively12Grid and PMOS tube P11 Grid correspond to the positive inverting input of another pair of comparator module, PMOS tube P respectively9Drain electrode and NMOS tube N1Grid, NMOS tube N4Grid, PMOS tube P11Drain electrode and NMOS tube N1Drain electrode be connected, PMOS tube P10Drain electrode and NMOS tube N2 Grid, NMOS tube N3Grid, NMOS tube N5Grid, PMOS tube P12Drain electrode and NMOS tube N2Drain electrode be connected, NMOS Pipe N1~N7Source grounding.
10. power management chip according to claim 9, it is characterised in that：The PMOS tube P10Breadth length ratio and PMOS Pipe P12The ratio between breadth length ratio and PMOS tube P9Breadth length ratio and PMOS tube P11The ratio between breadth length ratio be 1:N, N are more than 1 Real number.
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