CN115149928A - Voltage-insensitive high-precision oscillator circuit of process thermometer - Google Patents

Voltage-insensitive high-precision oscillator circuit of process thermometer Download PDF

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Publication number
CN115149928A
CN115149928A CN202210908070.1A CN202210908070A CN115149928A CN 115149928 A CN115149928 A CN 115149928A CN 202210908070 A CN202210908070 A CN 202210908070A CN 115149928 A CN115149928 A CN 115149928A
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tube
resistor
pmos tube
output
circuit
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吴殿升
邹勇
杨勇
史春杰
袁波
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Wuxi Grand Microelectronics Technology Co ltd
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Wuxi Grand Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

Abstract

The invention relates to a voltage-insensitive high-precision oscillator circuit of a process thermometer, which comprises an oscillation signal generating circuit, a frequency-jittering oscillator power supply generating circuit and a clock coupling output circuit, wherein a feedback clock output by the clock coupling output circuit is connected with the input end of the frequency-jittering oscillator power supply generating circuit. In the high-precision oscillator circuit provided by the invention, on one hand, the oscillator power supply voltage adopted by the oscillating signal generating circuit is only controlled by the reference signal and is not influenced by PVT fluctuation, and the frequency stability of the reference clock signal OSC _ out is ensured; on the other hand, pseudo random codes with pseudo random characteristics in amplitude and time are adopted in the frequency-jittering oscillator power supply generation circuit for modulation, oscillator power supply voltage with pseudo random frequency jittering characteristics is generated, the frequency of the reference clock signal OSC _ out has the frequency jittering characteristics, and finally the output clock signal is changed into a frequency jittering clock, so that the aim of reducing EMI interference is fulfilled.

Description

Voltage-insensitive high-precision oscillator circuit of process thermometer
Technical Field
The invention relates to a high-precision oscillator circuit insensitive to process thermometer voltage, and belongs to the technical field of integrated circuits.
Background
The Pulse Width Modulation (PWM) technique is a very effective technique for controlling an analog circuit by using a digital output Pulse, and is widely used in many fields such as measurement, communication, power control and conversion. The PWM signal is a digital signal because at a certain moment, either the current or the voltage is present in an ON or OFF state. The voltage or point current is applied to the analog load by a repetitive pulse train of ON or OFF. Any analog value can be encoded using PWM as long as the bandwidth is sufficient. Therefore, the PWM control technology has wide application in various power integrated circuits and the field of high-reliability signal transmission, is a mature control mode, and has the advantages of simple structure, high output control precision and the like.
In general, in the pulse width modulation mode, the duty ratio of the system is adjusted by adjusting the conduction time of a power switch tube by keeping the switching frequency of the whole control system unchanged, so that the output power is changed. In modern power integrated circuits controlled in various PWM modes, the switching frequency is controlled by a clock oscillator signal, usually generated by an on-chip integrated oscillator circuit, and thus the clock characteristics of the oscillator circuit output have an important influence on the performance of the whole chip. The invention provides a voltage insensitive high-precision oscillator circuit of a process thermometer.
Disclosure of Invention
On the basis of the prior art, the invention provides a high-precision oscillator circuit insensitive to the process thermometer voltage, and the control precision of the controller is further improved.
The voltage insensitive high-precision oscillator circuit of the process thermometer comprises: the feedback clock CK _ fb output by the clock coupling output circuit is connected with the input end of the frequency jitter oscillator power supply generating circuit; the frequency-jittering oscillator power supply generation circuit generates an oscillator power supply voltage VCC _ OSC according to a power supply voltage VCC and a feedback clock CK _ fb and outputs the oscillator power supply voltage VCC _ OSC to an oscillation signal generation circuit, the oscillation signal generation circuit generates a reference clock signal OSC _ out according to the oscillator power supply voltage VCC _ OSC and outputs the reference clock signal OSC _ out to a clock coupling output circuit, and the clock coupling output circuit generates X circuits of output clocks CK 1-CKX and the feedback clock CK _ fb according to the power supply voltage VCC and the clock signal OSC _ out, wherein X is a positive integer.
Specifically, the oscillation signal generating circuit includes: a current source I40, a PMOS transistor M40, an NMOS transistor M41, a delay capacitor C40, a Schmitt trigger S40, an inverter Inv41, an inverter Inv42 and an output buffer Buf40; the inverter Inv40, the inverter Inv41 and the inverter Inv42 are sequentially connected to form an odd-level inverter chain, the PMOS tube M40 and the NMOS tube M41 form a delay control inverter, the source electrode of the PMOS tube M40 is connected with the current source I40, the grid electrode of the PMOS tube M40 is connected with the grid electrode of the NMOS tube M41 and serves as the input end of the delay control inverter, the drain electrode of the PMOS tube M40 is connected with the drain electrode of the NMOS tube M41 and serves as the output end of the delay control inverter, and the source electrode of the NMOS tube M41 is grounded; the output of the delay control inverter is simultaneously connected to the upper end of the delay capacitor C40 and the input end of the schmitt trigger S40, the lower end of the delay capacitor C40 is grounded, the output end of the schmitt trigger S40 is connected to the input end of the odd-numbered stage inverter chain, the output end of the odd-numbered stage inverter chain is simultaneously connected to the input end of the output buffer Buf40 and the input end of the delay control inverter, and the output end of the output buffer Buf40 is the reference clock signal OSC _ out.
Specifically, the dither-frequency oscillator power generation circuit comprises the following circuits:
the two-stage error amplifier is composed of a PMOS tube M501, a PMOS tube M502, a PMOS tube M505, a PMOS tube M506, an NMOS tube M508, an NMOS tube M509, an NMOS tube M510, a resistor R51 and a capacitor C51, wherein a first differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M505, a second differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M506, and an amplification output end of the two-stage error amplifier is connected with a drain electrode of the PMOS tube M502 and a drain electrode of the NMOS tube M510; the drain electrode of the PMOS tube M501 is connected with the source electrode of the PMOS tube M505 and the source electrode of the PMOS tube M506, the drain electrode of the PMOS tube M505 is connected with the drain electrode of the NMOS tube M508, the grid electrode of the NMOS tube M508 and the grid electrode of the NMOS tube M509, the drain electrode of the PMOS tube M506 is connected with the drain electrode of the NMOS tube M509, the upper end of a resistor R51 and the grid end of the NMOS tube M510, and the lower end of the resistor R51 is connected with the upper end of a capacitor C51;
a follower buffer composed of a PMOS tube M503, a PMOS tube M511, a resistor R53 and a capacitor C52; the signal input end of the following buffer is the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube M511 and is connected with the amplification output ends of the two stages of error amplifiers; the signal output end of the following buffer is simultaneously connected with the source electrode of the PMOS tube M511, the lower end of the resistor R53 and the ground voltage GND passing through the capacitor C52; the upper end of the resistor R53 is connected with the drain electrode of a PMOS tube M503;
a feedback clock detection circuit composed of a PMOS tube M500, a PMOS tube M521, an NMOS tube M522, a resistor R521, a resistor R522 and a capacitor C521; the input end CK _ fb of the feedback clock detection circuit is connected to the grid of the PMOS pipe M521 and the grid of the NMOS pipe M522; the output end of the feedback clock detection circuit is a clock feedback voltage Vckfb and is connected to the lower end of the resistor R521, the upper end of the resistor R522 and the source electrode of the PMOS tube M521; the drain electrode of the PMOS tube M521 is connected with the drain electrode of the NMOS tube M522 and is connected to the upper end of the capacitor C521; the upper end of the resistor R521 is connected to the drain electrode of the PMOS tube M500; the source electrode of the NMOS tube M522, the lower end of the capacitor C521 and the lower end of the resistor R522 are grounded to the ground voltage GND;
a frequency-jittering reference voltage generating circuit consisting of a PMOS tube M530, a resistor R530, N series resistors, N NMOS tubes and a pseudo-random code generating circuit; a reference voltage input end Vref of the frequency-jittering reference voltage generating circuit is a grid electrode of a PMOS tube M530, and a frequency-jittering reference voltage Vrdith output end of the frequency-jittering reference voltage generating circuit is a connection point of the lower end of a resistor R530 and the upper end of a resistor string consisting of N series resistors; the drain electrode of the PMOS tube M530 is connected to the upper end of the resistor R530, the upper end and the lower end of each resistor in the N series resistors are respectively and correspondingly connected with the drain electrodes and the source electrodes of N NMOS tubes, and the grid electrodes of the N NMOS tubes are respectively connected with pseudo random codes P1-PN output by the pseudo random code generating circuit; the grounding voltage GND of the lowest end of a resistor string consisting of N series resistors;
a jittering reference voltage Vrdith generated by the jittering reference voltage generating circuit is connected to a second differential input end of the two-stage error amplifier, a clock feedback voltage Vckfb of the feedback clock detection circuit is connected to a first differential input end of the two-stage error amplifier, an amplifying output end of the two-stage error amplifier is connected to a signal input end of the following buffer, and a signal output end of the following buffer is an oscillator power supply voltage VCC _ OSC;
the source electrode of the NMOS transistor M722, the lower end of the capacitor C721, the lower end of the resistor R722, the source electrode of the NMOS transistor M708, the source electrode of the NMOS transistor M709, the lower end of the capacitor C71, the source electrode of the NMOS transistor M710 and the drain electrode of the PMOS transistor M711 are all grounded to the voltage GND; the grid electrode of the PMOS tube M700, the grid electrode of the PMOS tube M701, the grid electrode of the PMOS tube M702 and the grid electrode of the PMOS tube M703 are all connected with bias voltage; the source electrode of the PMOS tube M730, the source electrode of the PMOS tube M700, the source electrode of the PMOS tube M701, the source electrode of the PMOS tube M702 and the source electrode of the PMOS tube M703 are all connected with a power supply VCC; n =2 K And K is any positive integer.
Specifically, the dither-frequency reference voltage Vrdith in the dither-frequency reference voltage generating circuit is obtained by dividing the voltage of a resistor string total resistor composed of a resistor R530 and N series resistors; the resistance values of any two resistors in the N series resistors are different, and the resistance values of single resistors in the N resistors are selected to adopt pseudo-random distribution, namely the specific values of any two resistors are different, so that the random characteristic of the amplitude of the frequency jitter reference voltage Vrdith is realized; n-bit pseudo-random codes P1-PN generated by the pseudo-random code generating circuit only output high level by 1-bit pseudo-random code at any moment, and the rest N-1 bits are all low level; and the time lengths of the high level output by any 1-bit pseudo random code in the N-bit pseudo random codes P1 to PN are different, so that the random characteristic of the jittering reference voltage Vrdith on time is realized.
Specifically, the pseudo random code generating circuit includes: the time delay sequence generating circuit, the pseudo-random encoding circuit and the binary system-to-thermometer encoding circuit; the delay sequence generating circuit generates 2 K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1); the pseudo-random encoding circuit will 2 K+1 -1 clocks with different time delaysSignals Q1-Q (2) K+1 -1) random encoding into K-bit binary data signals D1 to DK; the binary thermometer-to-thermometer coding circuit performs coding conversion on D1-DK to obtain 2 K Bit thermometer codes P1-P2 K ；2 K Bit thermometer codes P1-P2 K The N-bit pseudo random code is finally output by the pseudo random code generating circuit;
the delay sequence generating circuit internally comprises 2 K+1 -1 cascaded D flip-flop delay cells, an xor gate and a ring oscillator; the ring oscillator generates an initial clock signal CLK;2 K+1 -1 cascaded D flip-flop delay units generate 2 in sequence according to an initial clock signal CLK K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1); the last two clock signals Q (2) K+1 -1) and Q (2) K+1 And-2) the D flip-flop is connected to a set control end of the first D flip-flop delay unit through an exclusive-OR gate in a feedback mode.
Specifically, the clock coupling output circuit includes: a PMOS tube M81, a PMOS tube M82, an NMOS tube M83, an NMOS tube M84, a PMOS tube M85, an NMOS tube M86, a PMOS tube M87, an NMOS tube M88, an inverter Inv81, an inverter Inv82, X +1 output inverters, a capacitor C80, a resistor R80, a capacitor C81, a resistor R81, a capacitor C82 and a resistor R82, wherein X is any positive integer; the left side of the capacitor C80 is connected to an external input clock signal, and the right side of the capacitor C80 is simultaneously connected to the upper end of the resistor R80, the lower end of the capacitor C81 and the upper end of the capacitor C82; the upper end of the capacitor C81 is connected to the lower end of the resistor R81 and the grid electrode of the PMOS transistor M85, and the lower end of the capacitor C82 is connected to the upper end of the resistor R82 and the grid electrode of the NMOS transistor M86; the upper end of the resistor R81 is connected to the drain electrode of the PMOS tube M82, the lower end of the resistor R82 is connected to the drain electrode of the NMOS tube M84, and the grid electrode of the PMOS tube M82 is simultaneously connected to the drain electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81, the drain electrode of the NMOS tube M83, the grid electrode of the NMOS tube M83 and the grid electrode of the NMOS tube M84; the drain electrode of the PMOS tube M85 is connected to the drain electrode of the NMOS tube M86, and is also connected to the grid electrodes of the PMOS tube M87 and the NMOS tube M88; the drain electrode of the PMOS tube M87 is connected to the drain electrode of the NMOS tube M88 and is also connected to the input end of the inverter Inv 81; an output terminal of the inverter Inv81 is connected to an input terminal of the inverter Inv 82; the output terminal of the inverter Inv82 is simultaneously connected to the input terminals of the X +1 output inverters; the output ends of the X +1 output inverters respectively provide a feedback clock signal CK _ fb and X output clock signals CK1 CKX; the lower end of the resistor R80, the source electrode of the NMOS tube M83, the source electrode of the NMOS tube M84, the source electrode of the NMOS tube M86 and the source electrode of the NMOS tube M88 are simultaneously connected to a ground voltage GND; the source electrode of the PMOS transistor M81, the source electrode of the PMOS transistor M82, the source electrode of the PMOS transistor M85 and the source electrode of the PMOS transistor M87 are simultaneously connected to a power supply voltage VCC.
The invention has the advantages that: on one hand, the oscillator power supply voltage VCC _ OSC adopted by the oscillation signal generating circuit is only controlled by the reference signal and is not influenced by PVT fluctuation, so that the frequency stability of the reference clock signal OSC _ out is ensured; on the other hand, a pseudo random code with pseudo random characteristics in amplitude and time is adopted to modulate inside the jitter frequency oscillator power generation circuit, and VCC _ OSC with pseudo random jitter characteristics is generated, so that the frequency of the reference clock signal OSC _ out has jitter frequency characteristics, and the aim of reducing EMI interference of the DC-DC controller is fulfilled. The invention can be widely applied to various PWM modulation controller systems.
Drawings
FIG. 1 is a block diagram of a voltage insensitive high precision oscillator circuit of the process thermometer of the present invention.
Fig. 2 is a diagram of an embodiment of an oscillation signal generating circuit according to the invention.
Fig. 3 is a diagram illustrating an embodiment of a power generation circuit of a dither frequency oscillator according to the present invention.
Fig. 4 is a diagram illustrating a jitter frequency reference Vrdith generated by the present invention.
FIG. 5 is a circuit for generating pseudo random codes according to an embodiment of the present invention.
FIG. 6 is a diagram of an embodiment of a clock coupling output circuit according to the present invention.
FIG. 7 is a simulation waveform of the generation process of the oscillating signal and the dithered oscillator power supply of the present invention.
FIG. 8 is a simulation waveform of the clock coupling output process according to the present invention.
Fig. 9 is a schematic diagram of the application of the present invention in an LED driving power supply.
Fig. 10 is a schematic diagram of the application of the present invention in a DC-DC controller.
Fig. 11 is a schematic diagram of the application of the present invention in a class D power amplifier.
Fig. 12 is a schematic diagram of the application of the present invention in a motor controller.
Fig. 13 is a schematic diagram of the application of the present invention in a PWM controller.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
As shown in fig. 1, the circuit of the present invention generally comprises: the system comprises a frequency jittering oscillator power supply generating circuit 1, an oscillating signal generating circuit 2 and a clock coupling output circuit 3. The dither-oscillator power-supply generating circuit 1 generates an oscillator power-supply voltage VCC _ OSC according to a power-supply voltage VCC and a feedback clock CK _ fb, the oscillation-signal generating circuit 2 generates a reference clock signal OSC _ out according to the oscillator power-supply voltage VCC _ OSC, and the clock-coupled output circuit 3 generates X output clocks CK1 to CKX and a feedback clock CK _ fb according to the power-supply voltage VCC and the clock signal OSC _ out. The feedback clock CK _ fb is further connected to the input of the dither-oscillator power-supply generating circuit 1.
Because the output frequency of the oscillator and the clock signal in the chip is particularly easily influenced by PVT fluctuation, in order to limit the influence of the PVT fluctuation on the frequencies of the output clocks CK1 to CKX, the feedback clock CK _ fb is adopted to perform feedback control on the oscillator power supply voltage VCC _ OSC adopted by the oscillation signal generating circuit 2, so that the stability of the reference clock signal OSC _ out is kept, and the stability of the output clocks CK1 to CKX is finally kept.
Assuming that the MOS transistor current in the oscillation signal generation circuit 2 decreases due to the temperature increase, the frequency of the corresponding reference clock signal OSC _ out decreases, the feedback clock CK _ fb decreases immediately, and the frequency-jittered oscillator power generation circuit 1 adjusts the oscillator power supply voltage VCC _ OSC according to the change of the feedback clock CK _ fb, so that the oscillator power supply voltage VCC _ OSC increases, the MOS transistor current in the corresponding oscillation signal generation circuit 2 increases, and finally compensates for the influence of the temperature change on the frequencies of the output clocks CK1 CKX. When the corresponding power supply voltage VCC changes, as long as the oscillator power supply voltage VCC _ OSC controlled by the reference signal is guaranteed to be unchanged, the frequency of the reference clock signal OSC _ out will remain unchanged, and the frequencies of the output clocks CK1 to CKX will also remain unchanged.
Fig. 2 is a diagram of an embodiment of the oscillation signal generating circuit 2 according to the present invention. The oscillation signal generation circuit 2 includes: the current source I40, the PMOS transistor M40, the NMOS transistor M41, the delay capacitor C40, the schmitt trigger S40, the inverter Inv41, the inverter Inv42, and the output buffer Buf40. The inverter Inv40, the inverter Inv41 and the inverter Inv42 form an odd-level inverter chain, the PMOS transistor M40 and the NMOS transistor M41 form a delay control inverter, the output of the delay control inverter is simultaneously connected to the upper end of the delay capacitor C40 and the input end of the schmitt trigger S40, the output end of the schmitt trigger S40 is connected to the input end of the odd-level inverter chain, the output end of the odd-level inverter chain is simultaneously connected to the input end of the output buffer Buf40 and the input end of the delay control inverter, and the output end of the output buffer Buf40 is the reference clock signal OSC _ out.
In the circuit of fig. 2, the delay control inverter, the schmitt trigger S40 and the odd-numbered inverter stages are cascaded to form a ring oscillator with the total number of odd-numbered stages, and an oscillation clock signal is generated, and the frequency of the output clock of the oscillator is controlled by the delay of charging and discharging the delay capacitor C40 by the current source I40. Since the current source I40 and the oscillator power supply voltage VCC _ OSC are both generated as reference signals and generally do not vary with PVT fluctuations, a stable reference clock signal OSC _ out can be obtained.
Fig. 3 is a diagram illustrating an embodiment of a power generation circuit 1 of a frequency-jittered oscillator according to the present invention. The dither-oscillator power generating circuit 1 comprises the following parts:
1. the two-stage error amplifier comprises a PMOS tube M501, a PMOS tube M502, a PMOS tube M505, a PMOS tube M506, an NMOS tube M508, an NMOS tube M509, an NMOS tube M510, a resistor R51 and a capacitor C51, wherein a first differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M505, a second differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M506, and an amplification output end of the two-stage error amplifier is connected with a drain electrode of the PMOS tube M502 and a drain electrode of the NMOS tube M510.
2. A follower buffer composed of a PMOS tube M503, a PMOS tube M511, a resistor R53 and a capacitor C52; the signal input end of the following buffer is the grid electrode of a PMOS tube M511; the signal output end of the follower buffer is the oscillator power supply voltage VCC _ OSC, and is simultaneously connected to the source of the PMOS transistor M511, the drain of the PMOS transistor M503, and the upper end of the capacitor C52.
3. A feedback clock detection circuit composed of a PMOS tube M500, a PMOS tube M521, an NMOS tube M522, a resistor R521, a resistor R522 and a capacitor C521; the input end CK _ fb of the feedback clock detection circuit is connected to the grid of the PMOS tube M521 and the grid of the NMOS tube M522; the output end of the feedback clock detection circuit is a clock feedback voltage Vckfb and is connected to the lower end of a resistor R521, the upper end of a resistor R522, the source electrode of a PMOS (P-channel metal oxide semiconductor) tube M521 and the first differential input end of the two-stage error amplifier; the drain electrode of the PMOS tube M521 is connected with the drain electrode of the NMOS tube M522 and is connected to the upper end of the capacitor C521; the upper end of the resistor R521 is connected to the drain electrode of the PMOS tube M500; the source of the NMOS transistor M522, the lower end of the capacitor C521, and the lower end of the resistor R522 are grounded to the voltage GND.
4. The dither frequency reference voltage generating circuit is composed of a PMOS tube M530, a resistor R530, N series resistors R531-R53N, N NMOS tubes M531-M53N and a pseudo random code generating circuit 50. The reference voltage input end Vref of the frequency-jittering reference voltage generating circuit is the grid of the PMOS tube M530, the drain of the PMOS tube M530 is connected to the upper end of the resistor R530, and the frequency-jittering reference voltage Vrdith generated by the frequency-jittering reference voltage generating circuit is the connection point of the lower end of the resistor R530 and the upper end of the resistor string consisting of the N series resistors. The resistors R531-R53N are sequentially connected from top to bottom, the upper end of the resistor R531 is the upper end of the resistor string consisting of the N series resistors, and the lower end of the resistor R53N is the lower end of the resistor string consisting of the N series resistors. The drain electrode of the NMOS tube M531 is connected to the upper end of the resistor R531, and the source electrode of the NMOS tube M531 is connected to the lower end of the resistor R531; the drain electrode of the NMOS tube M532 is connected to the upper end of the resistor R532, and the source electrode of the NMOS tube M532 is connected to the lower end of the resistor R532; and by analogy, the drain electrode of the NMOS transistor M53N is connected to the upper end of the resistor R53N, and the source electrode of the NMOS transistor M53N is connected to the lower end of the resistor R53N and is grounded GND. The pseudo-random code P1 output by the pseudo-random code generating circuit 50 is connected to the grid of the NMOS transistor M531, the pseudo-random code P2 output by the pseudo-random code generating circuit 50 is connected to the grid of the NMOS transistor M532, and so on, the pseudo-random code PN output by the pseudo-random code generating circuit 50 is connected to the grid of the NMOS transistor M53N.
A jitter frequency reference voltage Vrdith generated by the jitter frequency reference voltage generation circuit is connected to a second differential input end of the two-stage error amplifier, a clock feedback voltage Vckfb of the feedback clock detection circuit is connected to a first differential input end of the two-stage error amplifier, an amplification output end of the two-stage error amplifier is connected to a signal input end of the following buffer, and a signal output end of the following buffer is an oscillator power supply voltage VCC _ OSC.
In fig. 3, the feedback clock detection circuit is composed of a PMOS transistor M500, a PMOS transistor M521, an NMOS transistor M522, a resistor R521, a resistor R522, and a capacitor C521. Under the control of the feedback clock CK _ fb, the PMOS transistor M521 and the NMOS transistor M522 charge and discharge the capacitor C521, so that the capacitor C521 forms an equivalent impedance Rc521, and the resistor after the Rc521 is connected in parallel with the R522 is divided by the R521, thereby obtaining the final clock feedback voltage Vckfb. The equivalent impedance Rc521 formed by the capacitor C521 is obviously inversely proportional to the frequency of the feedback clock CK _ fb, and if the frequency of the feedback clock CK _ fb becomes higher, the equivalent impedance Rc521 will be lower; if the frequency of the feedback clock CK _ fb decreases, the equivalent impedance Rc521 will become high. Therefore, the voltage level of the clock feedback voltage Vckfb can accurately reflect the frequency level of the feedback clock CK _ fb.
In the dither-frequency reference voltage generating circuit composed of the PMOS transistor M530, the resistor R530, the N series resistors, the N NMOS transistors, and the pseudo random code generating circuit 50 in fig. 3, the dither-frequency reference voltage Vrdith is obtained by dividing the voltage of the total resistor Rs53 of the resistor string composed of the resistor R530 and the N series resistors. The total resistance Rs53 of the resistor string consisting of N series resistors is controlled by the N-bit pseudo random code, so that the dither-frequency reference voltage Vrdith generated by the dither-frequency reference voltage generation circuit has a pseudo random characteristic. In the embodiment of the invention, the resistance values of any two resistors in the N series resistors are different, and the resistance values of the single resistor in the N resistors are distributed in a pseudo-random manner, namely the specific values of the two resistors are different. Therefore, the voltage amplitude difference values between the jittered frequency reference voltages Vrdith under the control of different pseudo-random codes can be ensured to be different, and the random characteristic of the jittered frequency reference voltages Vrdith amplitude is realized. Only 1 bit pseudo-random code outputs high level at any moment, and the rest N-1 bits are low level; and the time lengths of the high level output of any 1 bit pseudo random code in the N bit pseudo random codes P1 to PN are different. Therefore, the effective duration time of any voltage between the jittered frequency reference voltages Vrdith under the control of different pseudo-random codes can be guaranteed to be different, and the random characteristic of the jittered frequency reference voltages Vrdith in time is realized.
Fig. 4 is a schematic diagram of a frequency-jittered reference voltage Vrdith formed by the frequency-jittered reference voltage generation circuit shown in fig. 3. The figure shows the waveforms of 8 different jitter frequency reference voltages Vrdith realized by 8-bit pseudo-random code control. It can be seen that the jittered frequency reference voltage Vrdith provided by the invention has not only pseudo-random characteristics in amplitude, but also pseudo-random characteristics in time, thereby being closer to natural noise signals. And as the number of pseudorandom code bits increases, the closer the dither reference voltage Vrdith will be to the natural noise signal.
FIG. 5 shows an embodiment of the pseudo random code generating circuit 50 according to the present invention. The pseudo random code generating circuit 50 includes a delay sequence generating circuit 71, a pseudo random encoding circuit 72, and a binary to thermometer encoding circuit 73. The delay sequence generating circuit 71 generates 2 K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1); the pseudo-random encoding circuit 72 will 2 K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1) random encoding into K-bit binary data signals D1 to DK; the binary thermometer-to-thermometer coding circuit 73 performs coding conversion on K-bit binary data signals D1 to DK to obtain 2 K Bit thermometer codes P1-P2 K ；P1～P2 K I.e., the N-bit pseudo random code finally output by the pseudo random code generating circuit 50. Wherein N =2 K And K is a positive integer.
As shown in the left side of fig. 5, the delay sequence generating circuit 71 internally includes 2 K+1 -1 cascaded D flip-flop delay cells, an XOR gate XOR71 and a ring oscillator 711; the ring oscillator 711 generates an initial clock signal CLK;2 K+1 -1 cascaded D flip-flop delay units generating sequentially 2 according to an initial clock signal CLK K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1); the last two clock signals Q2 K+1 -1 and Q2 K+1 And-2 is connected to the set control end of the first D flip-flop delay unit in a feedback mode after passing through an exclusive OR gate XOR 71.
In the pseudo random code generating circuit 50 of fig. 5, a total of 8-bit pseudo random codes are generated, so that K =3, the delay sequence generating circuit 71 internally adopts a delay unit including 15 cascaded D flip-flops, and sequentially generates 15 clock signals Q1 to Q15 with different time delays. The pseudo-random encoding circuit 72 uses a total of 15 tap clock signals, each of which is not auto-correlated nor correlated between taps. And 3-bit binary pseudo-random codes DA0, DA1 and DA2 are obtained through coding. Then the 3-bit binary pseudo-random code is decoded to obtain 8-bit output thermometer pseudo-random codes P1-P8.
Fig. 6 shows an embodiment of the clock coupling output circuit 3 according to the present invention. The clock coupling output circuit 3 includes: PMOS pipe M81, PMOS pipe M82, NMOS pipe M83, NMOS pipe M84, PMOS pipe M85, NMOS pipe M86, PMOS pipe M87, NMOS pipe M88, inverter Inv81, inverter Inv82, X +1 output inverters, capacitor C80, resistor R80, capacitor C81, resistor R81, capacitor C82 and resistor R82.
Wherein, the left side of the capacitor C80 is connected to the external input clock signal IN, and the right side (point A) of the capacitor C80 is simultaneously connected to the upper end of the resistor R80, the lower end of the capacitor C81 and the upper end of the capacitor C82; the upper end (point B) of the capacitor C81 is connected to the lower end of the resistor R81 and the grid electrode of the PMOS transistor M85, and the lower end (point C) of the capacitor C82 is connected to the upper end of the resistor R82 and the grid electrode of the NMOS transistor M86; the upper end of the resistor R81 is connected to the drain electrode of the PMOS tube M82, the lower end of the resistor R82 is connected to the drain electrode of the NMOS tube M84, and the grid electrode of the PMOS tube M82 is simultaneously connected to the drain electrode and the grid electrode of the PMOS tube M81, the drain electrode and the grid electrode of the NMOS tube M83 and the grid electrode of the NMOS tube M84; the drain electrode (point D) of the PMOS tube M85 is connected to the drain electrode of the NMOS tube M86, and is also connected to the grid electrode of the PMOS tube M87 and the grid electrode of the NMOS tube M88; the drain of the PMOS transistor M87 is connected to the drain of the NMOS transistor M88, and is also connected to the input terminal of the inverter Inv 81. An output terminal of the inverter Inv81 is connected to an input terminal of the inverter Inv 82; the output end of the inverter Inv82 is simultaneously connected to the input ends of the X +1 output inverters; the output terminals of the X +1 output inverters provide a feedback clock signal CK _ fb and X output clock signals CK1 CKX, respectively. The lower end of the resistor R80, the source electrode of the NMOS tube M83, the source electrode of the NMOS tube M84, the source electrode of the NMOS tube M86 and the source electrode of the NMOS tube M88 are simultaneously connected to a ground voltage GND; the source electrode of the PMOS transistor M81, the source electrode of the PMOS transistor M82, the source electrode of the PMOS transistor M85 and the source electrode of the PMOS transistor M87 are simultaneously connected to a power supply voltage VCC.
In fig. 6, the PMOS transistor M81, the PMOS transistor M82, the NMOS transistor M83, and the NMOS transistor M84 form a self-biased circuit together, which provides a bias to the upper end of the resistor R81 and the lower end of the resistor R82; the capacitor C80 and the resistor R80 form a high-pass filter for blocking the high-low level direct current component of the input clock; the capacitor C81 and the resistor R81 form a second high-pass filter, and the capacitor C82 and the resistor R82 form a third high-pass filter; the outputs of the second high-pass filter and the third high-pass filter are respectively connected to the grid of the PMOS transistor M85 and the grid of the NMOS transistor M86. After the input clock signal is subjected to 2-stage high-pass filtering, the obtained alternating current signal passes through a push-pull amplification circuit formed by a PMOS tube M85 and an NMOS tube M86, a new clock signal after high-low level shifting is obtained at a D point, and then the new clock signal is buffered and shaped by a 3-stage phase inverter to obtain a final output clock.
IN the circuit shown IN fig. 6, an input clock IN is subjected to 2-stage high-pass filtering, and then is shaped and buffered by a cascade inverter to obtain a multi-path output clock. The function of the high-pass filter is to convert an input clock with the oscillation amplitude of VCC _ OSC into an output clock with the oscillation amplitude of VCC through capacitive coupling of the high-pass filter, so that the level conversion is realized. The power supply used by the output clock is VCC, and even a larger interference is not fed back to the input clock, thereby ensuring the stability of the input clock IN, i.e., the reference clock signal OSC _ out.
FIG. 7 is a simulation waveform of the generation process of the oscillating signal and the dithered oscillator power supply of the present invention. After the power supply voltage VCC is powered on, both the reference clock signal OSC _ out and the oscillator power supply voltage VCC _ OSC require a stabilization process, and finally, the output clock CKX with stable frequency is obtained. FIG. 8 is a simulation waveform of the clock coupling output process of the present invention, IN which the amplitude of the input clock IN is 0-1.2V, the amplitude of the A point after filtering is-0.6- +0.6V, the amplitude of the B point obtained by the secondary filtering shift is 1.0-2.2V, the amplitude of the C point obtained by the secondary filtering shift is-0.2-1.0V, and the amplitude of the D point clock finally obtained is 0-1.8V.
Fig. 9 is a schematic diagram of the application of the present invention in an LED driving power supply. The LED driving power supply chip system is a three-channel LED driving system. There are many different classification ways for LED driving chips, wherein constant current type driving is the most common and reliable driving way at present. The constant current driving means that the current of the output end is kept constant, so that the driving load generates normal illumination brightness. The constant current type drive can be divided into switch constant current drive and linear constant current drive according to the working state of the main power device, the switch constant current drive adopts a switch power supply technology, and when the current changes due to external interference, the current is adjusted to return to a preset value through sampling and feedback, so that the anti-interference capability is greatly enhanced. In addition, the LED has nonlinear I-V characteristics, so that very small voltage fluctuation can cause very large current change, the voltage fluctuation is inevitable, and the driving performance is improved by adopting a constant current type driving mode.
The circuit illustrated in fig. 9 has two dimming modes, current value dimming and PWM dimming, and the brightness of the LED is proportional to the conduction current through it. The LED dimming ratio is the ratio of the on and off time to the sum of the on time. Since LEDs are current driven devices, each LED should flow a similar current when the LEDs are connected in series. By receiving external signals, the current is changed, so that the lamp can output light with different colors. The chip can be directly applied to commercial power, and can ensure normal work of all LED loads within the whole working voltage range. The chip completes the intelligent dimming design, has the functions of overvoltage, overcurrent and overtemperature protection, and has the functions of power-on setting/power-off resetting.
The high precision oscillator circuit 00 provided by the present invention is used to provide the switching clock in fig. 9. The working process of the circuit is as follows: after the input end is electrified, stable low-voltage is output through the high-voltage reduction module and serves as a voltage source of the low-voltage module. After the power is supplied, through protection circuits such as overcurrent, overvoltage and overtemperature, when the protection circuit is not triggered, the oscillator generates a CLK clock signal with fixed frequency, PWM dimming is used as a control signal to control the reference selection circuit and output required reference voltage, meanwhile, the sawtooth wave signal generated by the oscillator circuit generates rectangular waves with different duty ratios after the reference voltage signal and the sawtooth wave signal pass through the comparator, and due to the fact that the different duty ratios drive the brightness of the three primary colors of light, the three colors of light generate different colors of light. One of the characteristics of the three-channel LED driving chip is that the brightness of three LED lamp strings of red, green and blue can be adjusted according to different scenes, so that a proper color temperature is generated, and various environmental requirements are met.
Fig. 10 is a schematic diagram of the application of the present invention in a DC-DC controller. The DC-DC controller adopts a synchronous rectification mode, and the normal working mode of the DC-DC controller is a continuous mode CCM (continuous mode CCM) and a modulation mode adopts a PWM (pulse-width modulation) mode. The high-precision oscillator 00 provided by the invention is used for generating various clock signals CLK required by a controller system. The differential amplifier DIFFAMP in fig. 10 is used to implement differential far-end sampling, and the output port of the amplifier is led out of the pin to facilitate whether the user selects the differential far-end sampling mode. And the output DRS of the differential far-end sampling is divided by sampling resistors RA and RB to obtain feedback voltage VFB, and the VFB and an internally generated 0.6V voltage reference are subjected to error amplification to obtain VEA. The inductor DCR current sampling is a lossless current sampling mode, can improve the conversion efficiency to a great extent, and is particularly applied to the application occasion of large current output. A negative temperature coefficient resistor RNTC is arranged near the inductor L for temperature sampling and is input into a temperature compensation module, and then the temperature compensation of the inductor is completed by a slope clamping circuit.
In normal operation mode, the clock signal CLK sets the RS latch to open MT and the current comparator ICMP outputs a signal PWM to reset the RS latch to close MT. The sampling threshold of the ICMP is controlled by the current ITHC, which is controlled by the output result VEA of the error amplifier in case of ILIM configuration determination, thus enabling the control of the voltage-current loop in peak current control mode. When the load becomes heavy, the output voltage VO is reduced, so that the LTHC is increased, the threshold value of the current comparator is increased, namely the on-time is prolonged, and more current is transmitted to the VO; when the load becomes light, the control process is reversed. The PWM modulation scheme can improve the conversion efficiency of the system when operating at a lower frequency, but requires a larger inductor and/or capacitor to maintain a smaller output voltage ripple. Therefore, the choice of operating frequency is a compromise between efficiency and the size and cost of the peripheral devices. The on-chip power supply module and the reference and bias module provide power supply, reference voltage, current bias and the like for normal work of the system circuit; the reverse current comparator assists in completing the functions of synchronous rectification, light-load working mode and the like; in addition, the system also integrates the functions of undervoltage and overvoltage protection, start-up enabling, soft start configuration and the like.
Fig. 11 is a schematic diagram of the application of the present invention in a class D audio power amplifier. The audio power amplifier is used for further amplifying the audio signal to obtain a larger output power to push the loudspeaker to produce sound. The class-D amplifier is a nonlinear power amplifier, which is a switching power amplifier with high working efficiency, wherein the amplified signal is not directly an input signal but a switching signal with variable pulse width after sampling conversion, when the class-D amplifier works, the on-resistance of a power switching tube is zero, no voltage drop exists, the resistance is infinite when the class-D amplifier is turned off, no current flows, the actual efficiency can reach more than 90% generally due to the limitation of receiving devices (such as switching speed, leakage current, non-zero on-resistance and the like) and the imperfection in design, so compared with the linear amplifier, the class-D amplifier has great advantages,
the PWM modulation based class D audio power amplifier system of fig. 11 has the following internal modules: and the input amplification stage adopts a fully differential structure, converts a single-end audio input signal into two paths of inverted output signals, and enables the common mode level of the two paths of inverted output signals to be biased at a VDD/2 level. An error amplifier with fully differential structure for shaping two audio input signals before comparing them with triangular carrier signal to generate an error signal V E1 And V E2 To reduce the Total Harmonic Distortion (THD) of the audio power amplifier. Ratio ofThe comparator is used for comparing the error signal V E1 、V E2 The triangular wave carrier signal and the two PWM signals are output to drive a rear-end output power switch tube, wherein V E1 And V E2 Must be smaller than the carrier signal V T Otherwise the system will be distorted. The driving circuit is used for shaping non-ideal PWM pulse signals, dead time is increased to protect a power switch tube, the phenomenon of Shoot-through of a single arm in a full-bridge switch circuit is prevented, the dead time is properly selected, the Shoot-through cannot be prevented due to too short dead time, and the circuit efficiency is reduced and the distortion degree is increased due to too long dead time. The full-bridge switch circuit is composed of two half-bridge switch circuits, and not only needs to meet the requirement of output current, but also needs the R of the power switch tube ON The power consumption of the power tube is reduced and the circuit efficiency is improved. FIG. 11 shows an oscillating circuit 00 for generating a triangular wave V according to the present invention T As carrier signal, V T Good linearity is required to generate a PWM signal to drive the power transistor. The reference source circuit provides accurate reference level and bias voltage for other modules. When the load current is larger than a limit value, the overcurrent protection circuit closes all power switch tubes, and simultaneously feeds back overcurrent information to the front-stage digital processing circuit for adjustment so as to protect the whole system. The over-temperature protection circuit is used for turning off all power tubes when the working temperature rises to a limit value, so that the system is protected. The circuit has a hysteresis design, and when the working temperature is reduced to a certain value, the state of the over-temperature protection circuit is changed, so that the system can work normally.
Fig. 12 is a schematic diagram of the application of the present invention in a motor controller, which is composed of 14 pins, from pin 1 to pin 14: nFAULT, MODE, PHASE, GND, nSLEEP, ENABLE, OUT +, SENSE, VBB, OUT-, GND, VCP, VREG, NC. Wherein, MODE, PHASE, nSLEEP, ENABLE are control signal input ports, and the level of the ports is changed to realize the control of the motor. nFAULT is the error alarm signal output port. OUT + and OUT-are H-bridge output ports that provide an output drive current of several amperes. The motor drive usually adopts the H bridge structure, and the H bridge comprises last 4N type DMOS pipes, and M1, M2 are high-side power tube, and M3, M4 are low-side power tube. VGH1 and VGH2 are high side power tube driving voltage, VGL1 and VGL2 are low side power tube driving voltage, thereby realizing the switch control of the power tube. The motor load is connected between the outputs OUT + and OUT-of the H-bridge. The working state of the motor is controlled by an H bridge. The MCU is programmed, control logics of a required forward and reverse rotation mode, a fast and slow speed reducing mode, a sleep mode and a PWM signal are preset, and then the motor is controlled to rotate forwards, rotate backwards, fast and slow speed reduce, enter a sleep state, accelerate and decelerate when required, so that the application requirements of users are met.
The specific functional modules of the motor controller shown in fig. 12 are as follows:
(1) POWER module (POWER): the module consists of a band gap reference voltage source and a self-starting high-voltage low-dropout regulator (LDO), and the power supply module provides a stable 5.5V low-voltage power supply for the rear-stage low-voltage module.
(2) Oscillator and high voltage Charge pump module (OSC/Charge pump): the high-voltage power supply comprises a high-voltage charge pump module, a power supply reference circuit, an oscillator circuit 00, a high-voltage level conversion circuit and a PSM control feedback loop, wherein the frequency of the oscillator is usually hundreds of KHz, the pump capacitor is charged and discharged by controlling the on and off of a switch to realize the lifting of the potential, the output voltage is stabilized at a voltage which is 5.5V higher than the input power supply voltage VBB through the PSM control loop, and the driving voltage is provided for the grid electrode of a high-end power MOS tube.
(3) Power tube gate drive module (Pre-driver): the power tube grid driving module comprises a grid driving circuit and a high-voltage DMOS power tube, wherein the power tube grid driving circuit is used for providing grid driving voltage and current, so that the DMOS power tube can be rapidly switched on and switched off.
(4) Mode Control module (Control): the module converts externally input logic signals MODE, PHASE, nSLEEP and ENABLE signals into 4 grid control signals through a series of digital logics to respectively control positive and negative rotation, fast and slow speed reduction, a low-power-consumption sleep MODE and PWM control of a motor.
(5) Protection module (Protect): various protection modules are integrated, including over-temperature protection, over-current protection, under-voltage locking, power-on reset and other protection modules.
Fig. 13 is a schematic diagram of the application of the present invention in a PWM controller. The switching power supply can realize the conversion between direct current and alternating current and between direct current and direct current, and convert the input voltage into output voltage with another amplitude. Switching power supplies are currently used in many fields because of their advantages such as high conversion efficiency. In these switching power supply circuits, a stable and efficient PWM controller circuit is required to control the on/off of the power devices in the converter circuit. Because the PWM controller only has one feedback loop, the PWM controller has the advantages of lower design difficulty, strong anti-noise capability, simple structure, wide modulation range and the like, thereby having wider application scenes.
The PWM controller in fig. 13 mainly includes: the device comprises a reference module, an LDO module, an under-voltage protection module, an oscillator module 00, a dead time control module, a driving module and the like.
According to the oscillator module 00 provided by the invention, the frequency of the oscillator is increased, and the oscillator is influenced by factors such as the switching tube and EMI (electro-magnetic interference), so that firstly, the conduction loss of the switching tube and the transformer loss are increased due to the frequency increase, and secondly, the difficulty of inhibiting EMI is increased.
An LDO module: inside LDO module output voltage is 5V, and this is because the inside 5V devices that adopt of chip, and this module function is for the inside module of chip provides stable voltage, need have certain electrified current ability, for reducing the influence of this voltage fluctuation to oscillator, undervoltage protection module, need be with LDO module output voltage's error range control within 1% to there is better transient response ability.
An undervoltage protection module: the performance and stability of the converter can be threatened when the circuit works at a low input voltage, the function of the undervoltage protection module is to stop the circuit from working below a design value, and the response speed and the accuracy of the module are the key points of the design.
A driving module: the driving module is divided into a synchronous rectification driving module and a half-bridge grid driving module, the power tube generally uses a VDMOS (vertical double-diffused metal oxide semiconductor), the grid-source capacitance of the VDMOS is large, the switching speed can be increased only by providing large current through the driving module, and the switching loss is reduced. When the supply voltage VCC =10V and the rise time is within 10ns, the half-bridge gate driving port can be calculated to be capable of outputting current, and a margin of 20% is reserved in consideration of the influence of wiring resistance. In addition, the source electrode of the high-side power tube of the half-bridge converter is not grounded, a level lifting circuit is needed to transfer the port of the high-side driving end to a corresponding potential, the voltage of the driving input power supply of the low-side tube is VCC in the figure, and the driving of the high-side tube is shifted to the high-voltage rail HB-HS through the level.
A dead time control module: the timing sequence between the half-bridge gate driving signal and the synchronous rectification driving signal is set by arranging an external resistor, and the dead time is usually set to be 50ns-500ns in consideration of the rising time and the falling time of a driving port when a chip works.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (6)

1. The voltage insensitive high-precision oscillator circuit of the process thermometer is characterized by comprising an oscillation signal generating circuit (2), a frequency jittering oscillator power supply generating circuit (1) and a clock coupling output circuit (3) which are sequentially connected, wherein a feedback clock CK _ fb output by the clock coupling output circuit (3) is connected with the input end of the frequency jittering oscillator power supply generating circuit (1); the frequency-jittering oscillator power supply generating circuit (1) generates an oscillator power supply voltage VCC _ OSC according to a power supply voltage VCC and a feedback clock CK _ fb and outputs the oscillator power supply voltage VCC _ OSC to an oscillating signal generating circuit (2), the oscillating signal generating circuit (2) generates a reference clock signal OSC _ out according to the oscillator power supply voltage VCC _ OSC and outputs the reference clock signal OSC _ out to a clock coupling output circuit (3), the clock coupling output circuit (3) generates X paths of output clocks CK 1-CKX and the feedback clock CK _ fb according to the power supply voltage VCC and the clock signal OSC _ out, and X is a positive integer.
2. A process thermometer voltage insensitive high precision oscillator circuit as claimed in claim 1, characterized in that the oscillation signal generating circuit (2) comprises: a current source I40, a PMOS transistor M40, an NMOS transistor M41, a delay capacitor C40, a Schmitt trigger S40, an inverter Inv41, an inverter Inv42 and an output buffer Buf40; the inverter Inv40, the inverter Inv41 and the inverter Inv42 are sequentially connected to form an odd-level inverter chain, the PMOS tube M40 and the NMOS tube M41 form a delay control inverter, the source electrode of the PMOS tube M40 is connected with the current source I40, the grid electrode of the PMOS tube M40 is connected with the grid electrode of the NMOS tube M41 and serves as the input end of the delay control inverter, the drain electrode of the PMOS tube M40 is connected with the drain electrode of the NMOS tube M41 and serves as the output end of the delay control inverter, and the source electrode of the NMOS tube M41 is grounded; the output end of the delay control inverter is simultaneously connected to the upper end of the delay capacitor C40 and the input end of the schmitt trigger S40, the lower end of the delay capacitor C40 is grounded, the output end of the schmitt trigger S40 is connected to the input end of the odd-numbered inverter chain, the output end of the odd-numbered inverter chain is simultaneously connected to the input end of the output buffer Buf40 and the input end of the delay control inverter, and the output end of the output buffer Buf40 is the reference clock signal OSC _ out.
3. A process thermometer voltage insensitive high precision oscillator circuit as claimed in claim 1, characterized in that the dither frequency oscillator power supply generating circuit (1) comprises the following parts:
the two-stage error amplifier is composed of a PMOS tube M501, a PMOS tube M502, a PMOS tube M505, a PMOS tube M506, an NMOS tube M508, an NMOS tube M509, an NMOS tube M510, a resistor R51 and a capacitor C51, wherein a first differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M505, a second differential input end of the two-stage error amplifier is a grid electrode of the PMOS tube M506, and an amplification output end of the two-stage error amplifier is connected with a drain electrode of the PMOS tube M502 and a drain electrode of the NMOS tube M510; the drain electrode of the PMOS tube M501 is connected with the source electrode of the PMOS tube M505 and the source electrode of the PMOS tube M506, the drain electrode of the PMOS tube M505 is connected with the drain electrode of the NMOS tube M508, the grid electrode of the NMOS tube M508 and the grid electrode of the NMOS tube M509, the drain electrode of the PMOS tube M506 is connected with the drain electrode of the NMOS tube M509, the upper end of a resistor R51 and the grid end of the NMOS tube M510, and the lower end of the resistor R51 is connected with the upper end of a capacitor C51;
a follower buffer composed of a PMOS tube M503, a PMOS tube M511, a resistor R53 and a capacitor C52; the signal input end of the following buffer is the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube M511 and is connected with the amplification output ends of the two stages of error amplifiers; the signal output end of the following buffer is simultaneously connected with the source electrode of the PMOS tube M511, the lower end of the resistor R53 and the ground voltage GND passing through the capacitor C52; the upper end of the resistor R53 is connected with the drain electrode of a PMOS tube M503;
a feedback clock detection circuit composed of a PMOS tube M500, a PMOS tube M521, an NMOS tube M522, a resistor R521, a resistor R522 and a capacitor C521; the input end CK _ fb of the feedback clock detection circuit is connected to the grid of the PMOS tube M521 and the grid of the NMOS tube M522; the output end of the feedback clock detection circuit is a clock feedback voltage Vckfb and is connected to the lower end of the resistor R521, the upper end of the resistor R522 and the source electrode of the PMOS tube M521; the drain electrode of the PMOS tube M521 is connected with the drain electrode of the NMOS tube M522 and is connected to the upper end of the capacitor C521; the upper end of the resistor R521 is connected to the drain electrode of the PMOS tube M500; the source electrode of the NMOS tube M522, the lower end of the capacitor C521 and the lower end of the resistor R522 are grounded to the ground voltage GND;
a frequency-jittering reference voltage generating circuit consisting of a PMOS tube M530, a resistor R530, N series resistors, N NMOS tubes and a pseudo-random code generating circuit; a reference voltage input end Vref of the frequency-jittering reference voltage generating circuit is a grid electrode of a PMOS tube M530, and a frequency-jittering reference voltage Vrdith output end of the frequency-jittering reference voltage generating circuit is a connection point of the lower end of a resistor R530 and the upper end of a resistor string consisting of N series resistors; the drain electrode of the PMOS tube M530 is connected to the upper end of the resistor R530, the upper end and the lower end of each resistor in the N series resistors are respectively and correspondingly connected with the drain electrodes and the source electrodes of N NMOS tubes, and the grid electrodes of the N NMOS tubes are respectively connected with pseudo random codes P1-PN output by the pseudo random code generating circuit; the grounding voltage GND at the lowest end of the resistor string consisting of the N series resistors;
a jittering reference voltage Vrdith generated by the jittering reference voltage generating circuit is connected to a second differential input end of the two-stage error amplifier, a clock feedback voltage Vckfb of the feedback clock detection circuit is connected to a first differential input end of the two-stage error amplifier, an amplifying output end of the two-stage error amplifier is connected to a signal input end of the following buffer, and a signal output end of the following buffer is an oscillator power supply voltage VCC _ OSC;
the source electrode of the NMOS transistor M722, the lower end of the capacitor C721, the lower end of the resistor R722, the source electrode of the NMOS transistor M708, the source electrode of the NMOS transistor M709, the lower end of the capacitor C71, the source electrode of the NMOS transistor M710 and the drain electrode of the PMOS transistor M711 are grounded at the voltage GND; the grid electrode of the PMOS tube M700, the grid electrode of the PMOS tube M701, the grid electrode of the PMOS tube M702 and the grid electrode of the PMOS tube M703 are all connected with bias voltage; the source electrode of the PMOS tube M730, the source electrode of the PMOS tube M700, the source electrode of the PMOS tube M701, the source electrode of the PMOS tube M702 and the source electrode of the PMOS tube M703 are all connected with a power supply VCC; n =2 K And K is any positive integer.
4. The voltage-insensitive high-precision oscillator circuit of a process thermometer as claimed in claim 3, wherein the frequency-jittering reference voltage Vrdith in the frequency-jittering reference voltage generating circuit is obtained by dividing the total resistance of a resistor string consisting of a resistor R530 and N series resistors; the resistance values of any two resistors in the N series resistors are different, and the resistance values of the single resistor in the N resistors are selected to adopt pseudo-random distribution, namely the specific values of the two resistors are different, so that the random characteristic of the amplitude of the frequency-jittering reference voltage Vrdith is realized; n bit pseudo-random codes P1-PN generated by the pseudo-random code generating circuit only output high level by 1 bit pseudo-random code at any moment, and the rest N-1 bits are all low level; and the time lengths of the high level output by any 1-bit pseudo random code in the N-bit pseudo random codes P1 to PN are different, so that the random characteristic of the jittering reference voltage Vrdith on time is realized.
5. The process thermometer voltage insensitive high precision oscillator circuit of claim 3 wherein the pseudo random code generating circuit comprises: a time delay sequence generating circuit (71), a pseudo-random encoding circuit (72) and a binary-to-thermometer encoding circuit (73); the delay sequence generating circuit (71) generates 2 K+1 -1 clock signals Q1-Q (2) with different time delays K +1 -1); the pseudo-random encoding circuit (72) will 2 K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1) random encoding into K-bit binary data signals D1 to DK; the binary thermometer-to-thermometer coding circuit (73) performs coding conversion on D1-DK to obtain 2 K Potential thermometerCodes P1 to P2 K ；2 K Bit thermometer codes P1-P2 K The N-bit pseudo random code is finally output by the pseudo random code generating circuit;
the delay sequence generating circuit (71) internally comprises 2 K+1 -1 cascaded D flip-flop delay cells, an xor gate and a ring oscillator; the ring oscillator generates an initial clock signal CLK;2 K+1 -1 cascaded D flip-flop delay units generate 2 in sequence according to an initial clock signal CLK K+1 -1 clock signals Q1-Q (2) with different time delays K+1 -1); the last two clock signals Q (2) K+1 -1) and Q (2) K+1 And-2) the D flip-flop is connected to a set control end of the first D flip-flop delay unit through an exclusive-OR gate in a feedback mode.
6. A process thermometer voltage insensitive high precision oscillator circuit as claimed in claim 1, characterized in that the clock coupled output circuit (3) comprises: a PMOS tube M81, a PMOS tube M82, an NMOS tube M83, an NMOS tube M84, a PMOS tube M85, an NMOS tube M86, a PMOS tube M87, an NMOS tube M88, an inverter Inv81, an inverter Inv82, X +1 output inverters, a capacitor C80, a resistor R80, a capacitor C81, a resistor R81, a capacitor C82 and a resistor R82, wherein X is any positive integer;
the left side of the capacitor C80 is connected to an external input clock signal, and the right side of the capacitor C80 is simultaneously connected to the upper end of the resistor R80, the lower end of the capacitor C81 and the upper end of the capacitor C82; the upper end of the capacitor C81 is connected to the lower end of the resistor R81 and the grid electrode of the PMOS transistor M85, and the lower end of the capacitor C82 is connected to the upper end of the resistor R82 and the grid electrode of the NMOS transistor M86; the upper end of the resistor R81 is connected to the drain electrode of the PMOS tube M82, the lower end of the resistor R82 is connected to the drain electrode of the NMOS tube M84, and the grid electrode of the PMOS tube M82 is simultaneously connected to the drain electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81, the drain electrode of the NMOS tube M83, the grid electrode of the NMOS tube M83 and the grid electrode of the NMOS tube M84; the drain electrode of the PMOS tube M85 is connected to the drain electrode of the NMOS tube M86, and is also connected to the grid electrodes of the PMOS tube M87 and the NMOS tube M88; the drain electrode of the PMOS tube M87 is connected to the drain electrode of the NMOS tube M88 and is also connected to the input end of the inverter Inv 81; an output terminal of the inverter Inv81 is connected to an input terminal of the inverter Inv 82; the output terminal of the inverter Inv82 is simultaneously connected to the input terminals of the X +1 output inverters; the output ends of the X +1 output inverters respectively provide a feedback clock signal CK _ fb and X output clock signals CK1 CKX; the lower end of the resistor R80, the source electrode of the NMOS tube M83, the source electrode of the NMOS tube M84, the source electrode of the NMOS tube M86 and the source electrode of the NMOS tube M88 are simultaneously connected to a ground voltage GND; the source electrode of the PMOS transistor M81, the source electrode of the PMOS transistor M82, the source electrode of the PMOS transistor M85, and the source electrode of the PMOS transistor M87 are simultaneously connected to a power supply voltage VCC.
CN202210908070.1A 2022-07-29 2022-07-29 Voltage-insensitive high-precision oscillator circuit of process thermometer Pending CN115149928A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116647210A (en) * 2023-07-25 2023-08-25 深圳飞骧科技股份有限公司 Clock signal control module and RF front-end module
CN116961623A (en) * 2023-09-20 2023-10-27 江苏帝奥微电子股份有限公司 High-precision duty ratio control circuit and control method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116647210A (en) * 2023-07-25 2023-08-25 深圳飞骧科技股份有限公司 Clock signal control module and RF front-end module
CN116961623A (en) * 2023-09-20 2023-10-27 江苏帝奥微电子股份有限公司 High-precision duty ratio control circuit and control method thereof
CN116961623B (en) * 2023-09-20 2023-12-08 江苏帝奥微电子股份有限公司 High-precision duty ratio control circuit and control method thereof

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