CN102270008A - Band-gap reference voltage source with wide input belt point curvature compensation - Google Patents

Abstract

The invention discloses a wide input bandgap reference voltage source with curvature temperature compensation, which mainly solves the problems of low power supply suppression ratio and poor temperature stability in the prior art. It includes a pre-bias circuit (1), a positive and negative temperature coefficient current generation circuit (3), a voltage/current conversion circuit (4) and a reference voltage generation circuit (5). The pre-bias circuit (1) outputs the voltage V _BIAS to the positive and negative temperature coefficient current generation circuit (3), the voltage/current conversion circuit (4) and the reference voltage generation circuit (5) respectively, and simultaneously outputs the generated current I _BIAS to Positive and negative temperature coefficient current generation circuit (3); the positive and negative temperature coefficient current generation circuit (3) generates currents I ₁ and I ₂ to output to the reference voltage generation circuit (5), and simultaneously converts the generated voltage V _BE through voltage/current conversion The circuit (4) converts the current _I3 and outputs it to the reference voltage generation circuit (5), and the reference voltage generation circuit (5) outputs the reference voltage V _REF . The invention has high suppression ratio and good temperature stability, and can be applied to integrated circuits with wide input and high precision.

Description

Wide Input Bandgap Voltage Reference with Curvature Compensation

technical field

The invention belongs to the field of microelectronics and relates to a voltage reference circuit of an integrated circuit, in particular to a bandgap reference voltage source with wide input band curvature temperature compensation. the

Background technique

The reference voltage source is an indispensable unit in many analog circuits and digital-analog hybrid integrated circuits. The normal operation and stable performance of the circuit system are inseparable from the stable reference voltage independent of temperature and power supply changes. With the increase of the complexity of the circuit system and the enhancement of the chip function, the requirements for some performance indicators of the reference voltage source are also increased. In some integrated circuit chips, it is often required to change the input power supply voltage range from a few volts to tens of volts, such as power MOSFETs that convert direct current to alternating current, IGBT driver chips, power factor correction chips for improving power utilization, and chargers , The constant voltage constant current control chip in the adapter. the

The currently recognized voltage reference technology is a bandgap voltage reference. The design principle of the traditional bandgap reference voltage source is to obtain the zero temperature coefficient by linearly combining two voltages with opposite temperature coefficients according to the characteristic that the bandgap voltage of the silicon material is independent of the power supply and temperature, and the negative temperature coefficient voltage is Produced by the BE junction of bipolar transistors, the positive temperature coefficient is produced by the difference ΔV _BE of the BE junction voltages of two bipolar transistors operating at different current densities. On the one hand, due to the limitations of technology and circuit structure, the input range of traditional bandgap reference voltage sources is usually narrow. On the other hand, since the change of ΔVBE with temperature is linear and the change of VBE with temperature is non-linear, there is an error in the traditional first-order temperature compensation. In 2008, Chinese patent application 200810231711.4 proposed a "wide-input CMOS bandgap reference circuit structure". The power supply rejection of the bias current mirror is relatively poor, and the noise on the power supply will affect the reference output voltage. At the same time, compared with low-voltage MOS tubes, in order to meet the requirements of high withstand voltage, this kind of high-voltage MOS tubes not only has a more complicated process, but also has poor output reference voltage accuracy.

Contents of the invention

The purpose of the present invention is to avoid the deficiencies of the above-mentioned prior art, and provide a wide input bandgap reference voltage source with curvature temperature compensation to improve the power supply rejection ratio and temperature stability of the reference, thereby improving the accuracy of the reference voltage and meeting the requirements of integration circuit development requirements. the

The technical key to realize the present invention is to design a pre-bias circuit, which improves the power supply rejection ratio of the reference while ensuring wide input, and designs a curvature temperature compensation circuit to offset the BJT tube working in the linear region. The non-linear characteristic of V _BE changing with temperature improves the temperature stability of the reference.

To achieve the above object, the present invention includes:

A pre-bias circuit for providing a bias voltage V _BIAS and a bias current I _BIAS for the curvature temperature compensation circuit;

The curvature temperature compensation circuit is used to generate the reference output voltage V _REF with curvature temperature compensation.

In the bandgap reference voltage source with wide input and curvature temperature compensation mentioned above, the pre-bias circuit includes six high-voltage PMOS transistors HM1-HM6, two high-voltage NMOS transistors HM7-HM8, and two voltage-stabilizing capacitors C1-HM6. C2, four NPN transistors Q1~Q4, resistor R1 and Zener diode ZD1; the six high-voltage PMOS transistors HM1~HM6 and two high-voltage NMOS transistors HM7~HM8 form a self-biased current mirror with source negative feedback, high voltage The transconductance of the PMOS transistor HM1 is greater than that of HM3, so that the pre-bias circuit can transition from the startup state to the normal working state; the resistor R1 is connected across the drain and source of the first high-voltage NMOS transistor HM7, and it is connected to The first NPN transistor Q1 and the second NPN transistor Q2 form a start-up circuit, which makes the circuit get rid of the degeneracy point; the two voltage stabilizing capacitors C1~C2 are respectively connected between the gates of the two high-voltage NMOS transistors HM7~HM8 and the ground, so that The gate voltage is stable; the Zener diode ZD1 forms a voltage stabilizing circuit with the third NPN transistor Q3 and the fourth NPN transistor Q4, and the emitter of the Q4 outputs a bias voltage signal V _BIAS to the curvature temperature compensation circuit.

The above-mentioned bandgap reference voltage source, wherein the curvature temperature compensation circuit includes a positive and negative temperature coefficient current generation circuit, a voltage/current conversion circuit and a reference voltage generation circuit, and the positive and negative temperature coefficient generated by the positive and negative temperature coefficient current generation circuit The temperature coefficient currents I ₁ , I ₂ and the bipolar transistor BE junction voltage V _BE are respectively output to the reference voltage generation circuit and the voltage/current conversion circuit; the voltage/current conversion circuit converts the bipolar transistor BE junction voltage V _BE Converted into current I ₃ , and output to the reference voltage generation circuit, through the reference voltage generation circuit, to generate the reference voltage V _REF .

The above-mentioned curvature temperature compensation circuit, wherein the positive and negative temperature coefficient current generation circuit includes twelve low-voltage PMOS transistors M1-M8 and M11-M14, six bipolar transistors Q5-Q10 and two resistors R2-R3 The collector of the fifth NPN transistor Q5 is connected with the bias current I _BIAS output by the pre-bias circuit to obtain a DC bias; the ratio of the emitter area of the fifth NPN transistor Q5 to the sixth NPN transistor Q6 is 8:1, The emitter area ratio of the seventh NPN transistor Q7 and the eighth NPN transistor Q8 is 1:8, and the fifth NPN transistor Q5, the sixth NPN transistor Q6, the seventh NPN transistor Q7 and the eighth NPN transistor Q8 form a translinear circuit , the translinear circuit and resistor R2 generate a positive temperature coefficient current I ₁ ; the base of the fifth NPN transistor Q5 is connected to the base of the NPN transistor Q10 to provide a voltage bias for said Q10, and the Q10 is connected to the resistor R3 Generate a negative temperature coefficient current I ₂ ; the low-voltage PMOS transistors M1-M4 constitute the first cascode current mirror, the low-voltage PMOS transistors M5-M8 constitute the second cascode current mirror, and the drains of the low-voltage PMOS transistor M4 are respectively connected to the low-voltage The emitters of the PMOS transistor M6 and the PNP transistor Q9 are connected, and the first and second cascode current mirrors form a current addition circuit, which is used to add the positive temperature coefficient current _I1 and the negative temperature coefficient current _I2 to form the first Nine PNP transistors Q9 provide DC bias, and the voltage V _BE generated by the BE junction of Q9 is output to the voltage/current conversion circuit; low-voltage PMOS transistors M7, M8, M11 and M12 form the third cascode current mirror, and are controlled by the low-voltage The drain of the PMOS transistor M12 outputs a negative temperature coefficient current I ₂ to the reference voltage generating circuit; the low-voltage PMOS transistors M1, M2, M13 and M14 constitute the fourth cascode current mirror, and the drain of the low-voltage PMOS transistor M14 outputs a positive Temperature coefficient current I ₁ to the reference voltage generating circuit.

The above-mentioned curvature temperature compensation circuit, wherein the voltage/current conversion circuit includes an operational transconductance amplifier OTA, two low-voltage PMOS transistors M9-M10 and a resistor R4; terminal and the output terminal are respectively connected to resistor R4, the voltage V _BE generated by the positive and negative temperature coefficient current generating circuit, and the gate of the low-voltage PMOS transistor M9, and the operational amplifier OTA, the low-voltage PMOS transistor M9 and the resistor R4 form a current series negative feedback circuit. To convert the voltage V _BE into a current I ₃ ; the low-voltage PMOS transistors M9 and M10 form a first current mirror circuit for outputting the current I ₃ to the reference voltage generating circuit.

The above-mentioned curvature temperature compensation circuit, wherein the reference voltage generating circuit includes two low-voltage NMOS transistors M15-M16 and two resistors R5-R6; the low-voltage NMOS transistors M15 and M16 form a second current mirror circuit for converting the positive The current I ₂ generated by the negative temperature coefficient current generation circuit is subtracted from the current I ₃ generated by the voltage/current conversion circuit, and the subtracted current generates a negative temperature coefficient voltage V ₁ through resistors R5 and R6; resistor R6 passes the positive and negative temperature coefficient The current I ₁ generated by the current generating circuit generates a positive temperature coefficient voltage V ₂ ; the sum of the voltages across the resistors R5 and R6 constitutes the reference voltage V _REF , that is, V _REF =V ₁ +V ₂ .

In the above pre-bias circuit, the transconductance of the high-voltage PMOS transistor HM1 is greater than that of HM3. the

In the aforementioned positive and negative temperature coefficient current generating circuit, the ratio of the emitter area of the fifth NPN transistor Q5 to the sixth NPN transistor Q6 is 8:1, and the ratio of the emitter area of the seventh NPN transistor Q7 to the eighth NPN transistor Q8 is 1. : 8. the

The advantages of the present invention are:

(1) Compared with the traditional bandgap reference, the present invention expands the range of the input power supply voltage by adding a pre-bias circuit in the bandgap reference circuit. the

(2) Compared with other wide input bandgap references, the present invention effectively improves the power supply rejection ratio due to the use of a self-bias current mirror with source negative feedback and a cascode current mirror. the

(3) The present invention has designed a V _BE linearized curvature temperature compensation circuit, compared with the traditional first-order temperature compensation, this method reduces the temperature coefficient of the bandgap reference and improves temperature stability.

The simulation results show that the bandgap reference voltage source with wide input band curvature temperature compensation provided by the present invention improves the power supply rejection ratio and temperature stability of the bandgap reference while ensuring the reference wide power supply voltage range, thus improving the bandgap The accuracy of the benchmark. the

Description of drawings

Fig. 1 is the block diagram of the bandgap reference voltage source of wide input band curvature temperature compensation provided by the present invention;

Fig. 2 is the circuit schematic diagram of the bandgap reference voltage source of wide input band curvature temperature compensation provided by the present invention;

Fig. 3 is the simulation graph that output reference voltage of the present invention changes with power supply voltage;

Fig. 4 is the temperature characteristic simulation graph of output reference voltage of the present invention;

Fig. 5 is a simulation curve diagram of the power supply rejection ratio characteristic of the output reference voltage of the present invention. the

Detailed ways

The present invention will be described in further detail below with reference to the accompanying drawings. the

Referring to FIG. 1 , the present invention includes a pre-bias circuit 1 and a curvature temperature compensation circuit 2 . Wherein: the curvature temperature compensation circuit 2 is mainly composed of a positive and negative temperature coefficient current generation circuit 3 , a voltage/current conversion circuit 4 and a reference voltage generation circuit 5 . The positive and negative temperature coefficient current generating circuit 3 includes one voltage input terminal, one current input terminal, one voltage output terminal V _BE and two current output terminals I ₁ , I ₂ ; the voltage/current conversion circuit 4 includes two voltage input terminals and One current output terminal I ₃ ; the reference voltage generating circuit 5 includes one voltage input terminal, three current input terminals and one voltage output terminal V _REF . The voltage input terminal and the current input terminal of the positive and negative temperature coefficient current generation circuit 3 are respectively connected to the output voltage V _BIAS and the output current I _BIAS of the pre-bias circuit 1, and its one-way voltage output V _BE is connected to the voltage/current conversion circuit 4 The other two current outputs I ₁ and I ₂ are connected to the two current input terminals of the reference voltage generation circuit 5; the other voltage input terminal of the voltage/current conversion circuit 4 is connected to the output voltage of the pre-bias circuit 1 V _BIAS is connected, its current output I ₃ is connected to the current input terminal of the reference voltage generating circuit 5; the voltage input terminal of the reference voltage generating circuit 5 is connected to the voltage output V _BIAS of the pre-bias circuit 1, and the output voltage V _REF .

The pre-bias circuit 1 provides the bias voltage V _BIAS for the positive and negative temperature coefficient current generation circuit 3, the voltage/current conversion circuit 4 and the reference voltage generation circuit 5, and simultaneously provides the bias current I _BIAS for the positive and negative temperature coefficient current generation circuit 3 ; The voltage V _BE generated by the positive and negative temperature coefficient current generation circuit 3 is converted into a current I ₃ by the voltage/current conversion circuit 4 and output to the reference voltage generation circuit 5, and the positive and negative temperature coefficient currents I ₁ , I ₂ is directly output to the reference voltage generation circuit 5; the reference voltage generation circuit 5 outputs the reference voltage V _REF .

With reference to Fig. 2, the structure and principle of each unit circuit of the present invention are described as follows:

Pre-bias circuit 1, including but not limited to six high-voltage PMOS transistors HM1~HM6, two high-voltage NMOS transistors HM7~HM8, two voltage stabilizing capacitors C1~C2, four NPN transistors Q1~Q4, resistor R1 and Zener Diode ZD1; the six high-voltage PMOS transistors HM1-HM6 and two high-voltage NMOS transistors HM7-HM8 form a self-biased current mirror with source negative feedback, and the transconductance of the high-voltage PMOS transistor HM1 is greater than that of HM3, so that the The pre-bias circuit can transition from the startup state to the normal working state; the source of the high-voltage NMOS transistor HM7 is connected to the resistor R1 and the collector and emitter of the two NPN transistors Q1 and Q3 respectively, and the drain of the high-voltage PMOS transistor HM6 outputs The bias current signal I _BIAS is sent to the positive and negative temperature coefficient current generation circuit 3; the resistor R1 is connected across the drain and source of the high-voltage NMOS transistor HM7, and it forms a startup circuit with the series-connected NPN transistor Q1 and NPN transistor Q2, so that the circuit is free from Degenerate points; two voltage stabilizing capacitors C1~C2 are respectively connected between the gates of the two high-voltage NMOS transistors HM7~HM8 and the ground to stabilize the gate voltage; the positive and negative terminals of the Zener diode ZD1 are respectively connected to the ground and The emitter of the NPN tube Q2 is connected to form a voltage stabilizing circuit with the series connected NPN tube Q3 and NPN tube Q4. The emitter of the Q4 outputs the bias voltage signal V _BIAS to the positive and negative temperature coefficient current generation circuit 3. Voltage/current conversion circuit 4 and the reference voltage generating circuit 5.

Positive and negative temperature coefficient current generation circuit 3, including but not limited to twelve low-voltage PMOS transistors M1-M8 and M11-M14, six bipolar transistors Q5-Q10 and two resistors R2-R3; the fifth NPN transistor Q5 The collector, the base and the emitter are respectively connected to the bias current I _BIAS output by the pre-bias circuit and the collectors of the NPN transistors Q5 and Q7; the collector and the emitter of the sixth NPN transistor Q6 are respectively connected to the low-voltage PMOS transistor M2 The drain is connected to the collector of the NPN transistor Q8; the base and emitter of the seventh NPN transistor Q7 are respectively connected to the emitter and ground of the NPN transistor Q6; the base and emitter of the eighth NPN transistor Q8 are respectively connected to the NPN transistor Q5 The emitter is connected to the resistor R2; the ratio of the emitter area of the fifth NPN transistor Q5 to the sixth NPN transistor Q6 is 8:1, and the ratio of the emitter area of the seventh NPN transistor Q7 to the eighth NPN transistor Q8 is 1: 8. NPN transistors QS-Q8 form a translinear linear circuit, which generates a positive temperature coefficient current _I1 with resistor R2; the base of the fifth NPN transistor Q5 is connected to the base of the NPN transistor Q10, which is the ninth NPN The transistor Q10 provides voltage bias, and the Q10 is connected with the resistor R3 to generate a negative temperature coefficient current I ₂ ; the first to fourth low-voltage PMOS transistors M1-M4 constitute the first cascode current mirror, and the fifth to eighth low-voltage PMOS transistors M5-M8 form a second cascode current mirror, and the first and second cascode current mirrors form a current addition circuit for adding the positive temperature coefficient current _I1 and the negative temperature coefficient current _I2 , Provide DC bias for the ninth PNP transistor Q9; the drain of the fourth low-voltage PMOS transistor M4 is respectively connected to the emitter of the sixth low-voltage PMOS transistor M6 and the PNP transistor Q9, and the voltage V _BE generated by the BE junction of the Q9 is output to Voltage/current conversion circuit 4; the seventh, eighth, eleventh and twelfth low-voltage PMOS transistors M7, M8, M11 and M12 form a third cascode current mirror for outputting negative temperature coefficient current I ₂ to The reference voltage generating circuit 5; the first, second, thirteenth and fourteenth low-voltage PMOS transistors M1, M2, M13 and M14 form a fourth cascode current mirror for outputting a positive temperature coefficient current _I1 to the reference Voltage generating circuit 5.

The value of the positive temperature coefficient current _I1 is: $I_1=\frac{V_{\mathrm{BE}6}+V_{\mathrm{BE}7}-V_{\mathrm{BE}5}-V_{\mathrm{BE}8}}{R_2}=\frac{2V_T\ln 8}{R_2};$

The value of the negative temperature coefficient current I ₂ is: $I_2=\frac{V_{\mathrm{BE}6}+V_{\mathrm{BE}7}-V_{\mathrm{BE}10}}{R_3}\≈\frac{V_{\mathrm{BE}6}}{R_3};$

The voltages V _BE5 , V _BE6 , V _BE7 , V _BE8 and V _BE10 are the BE junction voltages of the fifth, sixth, seventh, eighth and ninth NPN transistors Q5, Q6, Q7, Q8 and Q10 respectively, V _T As thermal voltage, by selecting the resistance ratio of the resistors R2 and R3, the first-order compensation of the current flowing through the PNP transistor Q9 with respect to temperature can be realized.

The value of the voltage V _BE is: $V_{\mathrm{BE}}=V_{G0}-(V_{G0}-V_{\mathrm{BE}0})\left(\frac{T}{T_0}\right)-(\mathrm{\η}-\mathrm{\α})V_T\ln \left(\frac{T}{T_0}\right),$ Among them, V _G0 is the bandgap voltage of silicon, T is the absolute temperature, T ₀ is the absolute temperature corresponding to 25°C, V _BE0 is the BE junction voltage at temperature T ₀ , η is a constant that depends on the BJT tube structure, and α is a constant that depends on A constant for the temperature characteristic of the emitter current of a bipolar transistor. At this time, the current flowing through the PNP transistor Q9 is approximately independent of the temperature, so α=1.

第九和第十低压PMOS管M9和M10构成第一电流镜，用于把电流I₃输出到基准电压产生电路5。  Voltage/current conversion circuit 4, including but not limited to operational transconductance amplifier OTA, two low-voltage PMOS transistors M9-M10 and resistor R4; the positive phase input terminal, negative phase input terminal and output terminal of operational transconductance amplifier OTA are respectively connected to resistors R4, the voltage V _BE generated by the positive and negative temperature coefficient current generation circuit and the grid of the ninth low-voltage PMOS transistor M9; the operational amplifier OTA, the ninth low-voltage PMOS transistor M9 and the resistor R4 form a current series negative feedback circuit for converting the voltage V _BE converted to current:

The ninth and tenth low-voltage PMOS transistors M9 and M10 constitute a first current mirror for outputting the current I ₃ to the reference voltage generation circuit 5 .

The reference voltage generating circuit 5 includes but not limited to two low-voltage NMOS transistors M15-M16 and two resistors R5-R6; the NMOS transistors M15 and M16 form a second current mirror for converting the current generated by the positive and negative temperature coefficient current generating circuit I ₂ is subtracted from the current I ₃ generated by the voltage/current conversion circuit, and the subtracted current generates a negative temperature coefficient voltage V ₁ through the resistors R5 and R6; the current I ₁ generated by the resistor R6 through the positive and negative temperature coefficient current generation circuit, A positive temperature coefficient voltage V ₂ is generated; the sum of the voltages across the resistors R5 and R6 constitutes the reference voltage V _REF , that is, V _REF =V ₁ +V ₂ .

The value of the positive temperature coefficient voltage V ₁ is: V ₁ =(I ₂ -I ₃ )(R ₅ +R ₆ );

The value of the negative temperature coefficient voltage V ₂ is: V ₂ =I ₁ R ₆ ;

By setting the size of resistors R2~R6, the reference voltage with zero temperature coefficient can be obtained, and its value is: $V_{\mathrm{BEF}}=(\frac{1}{R_3}-\frac{1}{R_4})(R_5+R_6)V_{G0}.$

Effect of the present invention can be further illustrated by following simulation:

1) Simulation conditions

The wide input bandgap reference voltage source with curvature temperature compensation proposed by the present invention is simulated by using Cadence circuit design and simulation software. The condition of simulation 1 is that the power supply voltage changes from 0V to 40V; the condition of simulation 2 is that the power supply voltage is 30V, and the temperature changes from -40℃ to 125℃; the condition of simulation 3 is that the power supply voltage is 30V, the temperature is -40℃, 25 °C, 125 °C. the

2) Simulation content and results

Simulation 1 is to simulate the variation of the reference voltage with the power supply voltage, and the simulation results are shown in Figure 3. Figure 3 shows that when the power supply voltage changes from 7.2V to 40V, the reference voltage only changes by 5.21mV, and the linear adjustment rate of the reference voltage obtained by dividing the change of the reference voltage by the change of the power supply voltage is 159uV/V. It can be seen that the reference voltage is affected by the power supply voltage Changes have little effect. the

In simulation 2, the temperature characteristic of the reference voltage is simulated, and the simulation result is shown in FIG. 4 . Figure 4 shows that: when the temperature changes from -40°C to 125°C, the temperature coefficient of the reference voltage is only 3.5ppm/°C, which shows that the temperature stability of the reference voltage is good. the

Simulation 3 simulates the power supply rejection ratio characteristics of the reference voltage, and the simulation results are shown in Figure 5. Figure 5 shows that the low-frequency power supply rejection ratios of the reference voltage at -40°C, 25°C, and 125°C are -96dB, -94dB, and -83dB, respectively. It can be seen that the power supply rejection ratio of the reference voltage is high. the

The above is only a best example of the present invention, and does not constitute any limitation to the present invention. Obviously, under the conception of the present invention, various changes and improvements can be made to the circuit, but these are all included in the protection of the present invention. the

Claims (6)

1. the bandgap voltage reference of wide input tape curvature temperature compensation comprises:

Pre-biased circuit (1) is used to curvature temperature-compensation circuit (2) that bias voltage V is provided _BIASWith bias current I _BIAS

Curvature temperature-compensation circuit (2) is used to produce the benchmark output voltage V with curvature temperature compensation _REF

It is characterized in that:

Described pre-biased circuit (1) comprises six high voltage PMOS pipe HM1～HM6, two high pressure NMOS pipe HM7～HM8, two electric capacity of voltage regulation C1～C2, four NPN pipes Q1～Q4, resistance R 1 and Zener diode ZD1; These six high voltage PMOS pipe HM1～HM6 and two high pressure NMOS pipe HM7～HM8 constitute the automatic biasing current mirror of being with source negative feedback; Resistance R 1 is connected across drain electrode and the source electrode of the first high pressure NMOS pipe HM7, and it and a NPN manage Q1 and the 2nd NPN pipe Q2 constitutes start-up circuit, makes circuit break away from the degeneracy point; Two electric capacity of voltage regulation C1～C2 are connected between the grid and ground of two high pressure NMOS pipe HM7～HM8, make grid voltage stable; Zener diode ZD1 and the 3rd NPN pipe Q3, the 4th NPN pipe Q4 constitute mu balanced circuit, the emitter output offset voltage signal V of this Q4 _BIASTo curvature temperature-compensation circuit (2).

Described curvature temperature-compensation circuit (2), comprise Positive and Negative Coefficient Temperature current generating circuit (3), voltage (4) and reference voltage generating circuit (5), the positive and negative temperature coefficient electric current I that this Positive and Negative Coefficient Temperature current generating circuit (3) produces ₁, I ₂With bipolar transistor BE junction voltage V _BE, output to reference voltage generating circuit (5) and voltage (4) respectively; This voltage (4) is with bipolar transistor BE junction voltage V _BEBe converted into electric current I ₃, and output to reference voltage generating circuit (5), by reference voltage generating circuit (5), produce reference voltage V _REF

2. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation, it is characterized in that: described Positive and Negative Coefficient Temperature current generating circuit (3) comprises 12 low pressure PMOS pipe M1～M8 and M11～M14, six bipolar transistor Q5～Q10 and two resistance R 2～R3; The collector of the 5th NPN pipe Q5 and the bias current I of pre-biased circuit (1) output _BIASConnect, obtain direct current biasing; The 5th NPN pipe Q5, the 6th NPN pipe Q6, the 7th NPN pipe Q7 and the 8th NPN pipe Q8 constitute translinear circuit, and this translinear circuit and resistance R 2 produce the positive temperature coefficient (PTC) electric current I ₁The base stage of the 5th NPN pipe Q5 is connected with the base stage of NPN pipe Q10, and for described Q10 provides voltage bias, this Q10 is connected generation negative temperature parameter current I with resistance R 3 ₂Low pressure PMOS pipe M1～M4 constitutes first common-source common-gate current mirror, low pressure PMOS pipe M5～M8 constitutes second common-source common-gate current mirror, the drain electrode of low pressure PMOS pipe M4 is connected with the emitter of low pressure PMOS pipe M6, PNP pipe Q9 respectively, first and second common-source common-gate current mirrors constitute current adder circuit, are used for the positive temperature coefficient (PTC) electric current I ₁With negative temperature parameter current I ₂Carry out addition, Q9 provides direct current biasing for the 9th PNP pipe, the voltage V that the BE knot of this Q9 produces _BEOutput to voltage (4); Low pressure PMOS pipe M7, M8, M11 and M12 constitute the 3rd common-source common-gate current mirror, and export negative temperature parameter current I by the drain electrode of low pressure PMOS pipe M12 ₂To reference voltage generating circuit (5); Low pressure PMOS pipe M1, M2, M13 and M14 constitute the 4th common-source common-gate current mirror, and export the positive temperature coefficient (PTC) electric current I by the drain electrode of low pressure PMOS pipe M14 ₁To reference voltage generating circuit (5).

3. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: described voltage (4) comprises that operation transconductance amplifier OTA, two low pressure PMOS manage M9～M10 and resistance R 4; The normal phase input end of operation transconductance amplifier OTA, inverting input and output terminal be the voltage V of connecting resistance R4, the generation of Positive and Negative Coefficient Temperature current generating circuit respectively _BEWith the grid of low pressure PMOS pipe M9, operational amplifier OTA, low pressure PMOS pipe M9 and resistance R 4 constitute electric current series connection negative-feedback circuit, are used for voltage V _BEBe converted into electric current I ₃Low pressure PMOS pipe M9 and M10 constitute first current mirror, are used for electric current I ₃Output to reference voltage generating circuit (5).

4. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: described reference voltage generating circuit (5) comprises two low pressure NMOS pipe M15～M16 and two resistance R 5～R6; Low pressure NMOS pipe M15 and M16 constitute second current mirror, are used for the electric current I that Positive and Negative Coefficient Temperature current generating circuit (3) is produced ₂Produce electric current I with voltage (4) ₃Subtract each other, the electric current after subtracting each other produces negative temperature coefficient voltage V by resistance R 5 and R6 ₁The electric current I that resistance R 6 produces by Positive and Negative Coefficient Temperature current generating circuit (3) ₁, produce positive temperature coefficient (PTC) voltage V ₂The both end voltage sum of resistance R 5 and R6 constitutes reference voltage V _REF, i.e. V _REF=V ₁+ V ₂

5. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: the mutual conductance of high voltage PMOS pipe HM1 is greater than the mutual conductance of HM3.

6. the bandgap voltage reference of wide input tape curvature according to claim 2 temperature compensation, it is characterized in that: the 5th NPN pipe Q5 is 8: 1 with the ratio of the emitter area of the 6th NPN pipe Q6, and the 7th NPN pipe Q7 is 1: 8 with the ratio of the emitter area of the 8th NPN pipe Q8.

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