CN102270008A - Band-gap reference voltage source with wide input belt point curvature compensation - Google Patents

Abstract

The invention discloses a band-gap reference voltage source with wide input belt point curvature compensation, and the band-gap reference voltage source is mainly used for solving the problems of low source rejection ratio and low temperature stability. The band-gap reference voltage source comprises a pre-bias circuit (1), a positive and negative temperature coefficient current generation circuit (3), a voltage/current conversion circuit (4) and a reference voltage generation circuit (5). The output voltage VBIAS of the pre-bias circuit (1) is output to the positive and negative temperature coefficient current generation circuit (3), the voltage/current conversion circuit (4) and the reference voltage generation circuit (5) respectively; the current IBIAS generated by the pre-bias circuit (1) is output to the positive and negative temperature coefficient current generation circuit (3); currents I1 and I2 generated by the positive and negative temperature coefficient current generation circuit (3) are output to the reference voltage generation circuit (5); and simultaneously, the voltage VBE generated by the positive and negative temperature coefficient current generation circuit (3) is converted into a current I3 by the voltage/current conversion circuit (4) and is output to the reference voltage generation circuit (5); and the reference voltage generation circuit (5) outputs the reference voltage VREF. The band-gap reference voltage source is high in rejection ratio and excellent in temperature stability and can be applied to an integrated circuit with wide input and high precision.

Description

The bandgap voltage reference of wide input tape curvature compensation

Technical field

The invention belongs to the microelectronics field, relate to the voltage reference circuit of integrated circuit, be specifically related to the bandgap voltage reference of a kind of wide input tape curvature temperature compensation.

Background technology

Reference voltage source is requisite unit in many mimic channels and the hybrid digital-analog integrated circuit, and the operate as normal of Circuits System and stable performance all be unable to do without the stable benchmark voltage that is independent of temperature and power source change.Along with the increase of Circuits System complexity and the enhancing of chip functions, the requirement of some performance index of reference voltage source is also improved thereupon.In some integrated circuit (IC) chip, often require the input supply voltage scope from several variations that lie prostrate tens volts, as power MOSFET, the IGBT chip for driving that direct current is converted to alternating current, be used for improving the power factor correction chip of electric power utilization factor and charger, adapter constant pressure and flow control chip.

The voltage reference technology of generally acknowledging is a bandgap reference voltage at present.The design concept of tradition bandgap voltage reference is according to the band gap voltage of silicon materials and power supply and the irrelevant characteristic of temperature, carry out linear combination by the voltage that has an opposite temperature coefficients with two and obtain zero-temperature coefficient, wherein negative temperature coefficient voltage is that positive temperature coefficient (PTC) is the difference DELTA V that is operated in the BE junction voltage of the bipolar transistor under the different current densities by two by the BE knot generation of bipolar transistor _BEProduce.On the one hand, because the restriction of technology and circuit structure, the input range of traditional bandgap voltage reference is narrower usually.On the other hand, because Δ VBE is linear and VBE is non-linear with variation of temperature with variation of temperature, there is error in traditional single order temperature compensation.Chinese patent application 200810231711.4 had proposed a kind of " wide input CMOS band-gap reference circuit structure " in 2008, the automatic biasing current mirror that this band-gap reference circuit structure is made of high-voltage MOS pipe, expanded the scope of input supply voltage, but the Power Supply Rejection Ratio of this automatic biasing current mirror is relatively poor, and the noise on the power supply will influence the benchmark output voltage.Simultaneously, relatively low pressure metal-oxide-semiconductor, this high-voltage MOS pipe are to reach withstand voltage high requirement, and not only manufacturing process is comparatively complicated, and the output reference voltage precision is relatively poor.

Summary of the invention

The objective of the invention is to avoid above-mentioned the deficiencies in the prior art, the bandgap voltage reference of a kind of wide input tape curvature temperature compensation is provided, with the Power Supply Rejection Ratio and the temperature stability of raising benchmark, thereby the precision of lifting reference voltage satisfies the requirement of integrated circuit development.

Realize that key problem in technology of the present invention is to have designed a kind of pre-biased circuit, when having guaranteed wide input, improved the Power Supply Rejection Ratio of benchmark, and designed a kind of curvature temperature-compensation circuit, be operated in the BJT pipe V of linear zone with counteracting _BETemperature variant nonlinear characteristic, the temperature stability of raising benchmark.

For achieving the above object, the present invention includes:

Pre-biased circuit is used to the curvature temperature-compensation circuit that bias voltage V is provided _BIASWith bias current I _BIAS

The curvature temperature-compensation circuit is used to produce the benchmark output voltage V with curvature temperature compensation _REF

The bandgap voltage reference of above-mentioned wide input tape curvature temperature compensation, wherein said pre-biased circuit comprises six high voltage PMOS pipe HM1～HM6, two high pressure NMOS pipe HM7～HM8, two electric capacity of voltage regulation C1～C2, four NPN pipes Q1～Q4, resistance R 1 and Zener diode ZD1; These six high voltage PMOS pipe HM1～HM6 and two high pressure NMOS pipe HM7～HM8 constitute the automatic biasing current mirror of being with source negative feedback, the mutual conductance of high voltage PMOS pipe HM1 makes described pre-biased circuit carry out the transition to normal operating conditions from starting state greater than the mutual conductance of HM3; Resistance R 1 is connected across drain electrode and the source electrode of the first high pressure NMOS pipe HM7, and it and a NPN manage Q1 and the 2nd NPN pipe Q2 constitutes start-up circuit, makes circuit break away from the degeneracy point; Two electric capacity of voltage regulation C1～C2 are connected between the grid and ground of two high pressure NMOS pipe HM7～HM8, make grid voltage stable; Zener diode ZD1 and the 3rd NPN pipe Q3, the 4th NPN pipe Q4 constitute mu balanced circuit, the emitter output offset voltage signal V of this Q4 _BIASTo the curvature temperature-compensation circuit.

Above-mentioned bandgap voltage reference, wherein said curvature temperature-compensation circuit, comprise Positive and Negative Coefficient Temperature current generating circuit, voltage and reference voltage generating circuit, the positive and negative temperature coefficient electric current I that this Positive and Negative Coefficient Temperature current generating circuit produces ₁, I ₂With bipolar transistor BE junction voltage V _BE, output to reference voltage generating circuit and voltage respectively; This voltage is with bipolar transistor BE junction voltage V _BEBe converted into electric current I ₃, and output to reference voltage generating circuit, by reference voltage generating circuit, produce reference voltage V _REF

Above-mentioned curvature temperature-compensation circuit, wherein said Positive and Negative Coefficient Temperature current generating circuit comprises 12 low pressure PMOS pipe M1～M8 and M11～M14, six bipolar transistor Q5～Q10 and two resistance R 2～R3; The collector of the 5th NPN pipe Q5 and the bias current I of pre-biased circuit output _BIASConnect, obtain direct current biasing; The 5th NPN pipe Q5 is 8: 1 with the ratio of the emitter area of the 6th NPN pipe Q6, the 7th NPN pipe Q7 is 1: 8 with the ratio of the emitter area of the 8th NPN pipe Q8, the 5th NPN pipe Q5, the 6th NPN pipe Q6, the 7th NPN pipe Q7 and the 8th NPN pipe Q8 constitute translinear circuit, and this translinear circuit and resistance R 2 produce the positive temperature coefficient (PTC) electric current I ₁The base stage of the 5th NPN pipe Q5 is connected with the base stage of NPN pipe Q10, and for described Q10 provides voltage bias, this Q10 is connected generation negative temperature parameter current I with resistance R 3 ₂Low pressure PMOS pipe M1～M4 constitutes first common-source common-gate current mirror, low pressure PMOS pipe M5～M8 constitutes second common-source common-gate current mirror, the drain electrode of low pressure PMOS pipe M4 is connected with the emitter of low pressure PMOS pipe M6, PNP pipe Q9 respectively, first and second common-source common-gate current mirrors constitute current adder circuit, are used for the positive temperature coefficient (PTC) electric current I ₁With negative temperature parameter current I ₂Carry out addition, Q9 provides direct current biasing for the 9th PNP pipe, the voltage V that the BE knot of this Q9 produces _BEOutput to voltage; Low pressure PMOS pipe M7, M8, M11 and M12 constitute the 3rd common-source common-gate current mirror, and export negative temperature parameter current I by the drain electrode of low pressure PMOS pipe M12 ₂To reference voltage generating circuit; Low pressure PMOS pipe M1, M2, M13 and M14 constitute the 4th common-source common-gate current mirror, and export the positive temperature coefficient (PTC) electric current I by the drain electrode of low pressure PMOS pipe M14 ₁To reference voltage generating circuit.

Above-mentioned curvature temperature-compensation circuit, wherein said voltage comprises that operation transconductance amplifier OTA, two low pressure PMOS manage M9～M10 and resistance R 4; The normal phase input end of operation transconductance amplifier OTA, inverting input and output terminal be the voltage V of connecting resistance R4, the generation of Positive and Negative Coefficient Temperature current generating circuit respectively _BEAnd the grid of low pressure PMOS pipe M9, operational amplifier OTA, low pressure PMOS pipe M9 and resistance R 4 constitute electric current series connection negative-feedback circuit, are used for voltage V _BEBe converted into electric current I ₃Low pressure PMOS pipe M9 and M10 constitute first current mirroring circuit, are used for electric current I ₃Output to reference voltage generating circuit.

Above-mentioned curvature temperature-compensation circuit, wherein said reference voltage generating circuit comprises two low pressure NMOS pipe M15～M16 and two resistance R 5～R6; Low pressure NMOS pipe M15 and M16 constitute second current mirroring circuit, are used for the electric current I that the Positive and Negative Coefficient Temperature current generating circuit is produced ₂Produce electric current I with voltage ₃Subtract each other, the electric current after subtracting each other produces negative temperature coefficient voltage V by resistance R 5 and R6 ₁The electric current I that resistance R 6 produces by the Positive and Negative Coefficient Temperature current generating circuit ₁, produce positive temperature coefficient (PTC) voltage V ₂The both end voltage sum of resistance R 5 and R6 constitutes reference voltage V _REF, i.e. V _REF=V ₁+ V ₂

Above-mentioned pre-biased circuit, the mutual conductance of high voltage PMOS pipe HM1 is greater than the mutual conductance of HM3.

Above-mentioned Positive and Negative Coefficient Temperature current generating circuit, the 5th NPN pipe Q5 is 8: 1 with the ratio of the emitter area of the 6th NPN pipe Q6, the 7th NPN pipe Q7 is 1: 8 with the ratio of the emitter area of the 8th NPN pipe Q8.

Advantage of the present invention is:

(1) the present invention has been by having increased pre-biased circuit in band-gap reference circuit, relatively expanded the scope of input supply voltage with traditional band-gap reference.

(2) the present invention and other wide input band-gap reference relatively owing to adopt the automatic biasing current mirror and the common-source common-gate current mirror of band source negative feedback, have improved Power Supply Rejection Ratio effectively.

(3) the present invention is owing to designed a kind of V _BELinearizing curvature temperature-compensation circuit has reduced the temperature coefficient of band-gap reference with traditional single order temperature compensation comparison the method, has improved temperature stability.

Simulation result shows, the bandgap voltage reference of wide input tape curvature provided by the present invention temperature compensation has improved the Power Supply Rejection Ratio and the temperature stability of band-gap reference, thereby improved the precision of band-gap reference when guaranteeing benchmark wide power voltage range.

Description of drawings

Fig. 1 is the block diagram of the bandgap voltage reference of wide input tape curvature provided by the invention temperature compensation;

Fig. 2 is the circuit theory diagrams of the bandgap voltage reference of wide input tape curvature provided by the invention temperature compensation;

Fig. 3 is the simulation curve figure of output reference voltage of the present invention with mains voltage variations;

Fig. 4 is the temperature characterisitic simulation curve figure of output reference voltage of the present invention;

Fig. 5 is the power supply rejection ratio characteristics simulation curve figure of output reference voltage of the present invention.

Embodiment

Followingly the present invention is described in further detail with reference to accompanying drawing.

With reference to Fig. 1, the present invention includes pre-biased circuit 1, curvature temperature-compensation circuit 2.Wherein: curvature temperature-compensation circuit 2 mainly is made up of Positive and Negative Coefficient Temperature current generating circuit 3, voltage 4 and reference voltage generating circuit 5.Positive and Negative Coefficient Temperature current generating circuit 3 comprises one road voltage input end, one road current input terminal, one road voltage output end V _BEWith two current output terminal I ₁, I ₂Voltage 4 comprises two voltage input ends and one road current output terminal I ₃Reference voltage generating circuit 5 comprises one road voltage input end, three road current input terminals and one road voltage output end V _REFThe voltage input end of Positive and Negative Coefficient Temperature current generating circuit 3 and current input terminal respectively with the output voltage V of pre-biased circuit 1 _BIASWith output current I _BIASConnect its road voltage output V _BEBe connected with the voltage input end of voltage 4, in addition two-way electric current output I ₁, I ₂Be connected with the two-way current input terminal of reference voltage generating circuit 5; Another road voltage input end of voltage 4 and the output voltage V of pre-biased circuit 1 _BIASConnect its electric current output I ₃Be connected with the current input terminal of reference voltage generating circuit 5; The voltage output V of the voltage input end of reference voltage generating circuit 5 and pre-biased circuit 1 _BIASConnect output voltage V _REF

Pre-biased circuit 1 provides bias voltage V for Positive and Negative Coefficient Temperature current generating circuit 3, voltage 4 and reference voltage generating circuit 5 _BIAS, provide bias current I for Positive and Negative Coefficient Temperature current generating circuit 3 simultaneously _BIASThe voltage V that Positive and Negative Coefficient Temperature current generating circuit 3 produces _BE, be converted into electric current I by voltage 4 ₃Output to reference voltage generating circuit 5, simultaneously with the positive and negative temperature coefficient electric current I of its generation ₁, I ₂Directly output to reference voltage generating circuit 5; Reference voltage generating circuit 5 output reference voltage V _REF

With reference to Fig. 2, the structure and the principles illustrated of each element circuit of the present invention are as follows:

Pre-biased circuit 1 includes but not limited to six high voltage PMOS pipe HM1～HM6, two high pressure NMOS pipe HM7～HM8, two electric capacity of voltage regulation C1～C2, four NPN pipes Q1～Q4, resistance R 1 and Zener diode ZD1; These six high voltage PMOS pipe HM1～HM6 and two high pressure NMOS pipe HM7～HM8 constitute the automatic biasing current mirror of being with source negative feedback, the mutual conductance of high voltage PMOS pipe HM1 makes described pre-biased circuit carry out the transition to normal operating conditions from starting state greater than the mutual conductance of HM3; The source electrode of high pressure NMOS pipe HM7 is connected the drain electrode output offset current signal I of high voltage PMOS pipe HM6 with the collector and emitter of resistance R 1, two NPN pipes Q1, Q3 respectively _BIASTo Positive and Negative Coefficient Temperature current generating circuit 3; Resistance R 1 is connected across drain electrode and the source electrode of high pressure NMOS pipe HM7, and it constitutes start-up circuit with NPN pipe Q1 that connects and NPN pipe Q2, makes circuit break away from the degeneracy point; Two electric capacity of voltage regulation C1～C2 are connected between the grid and ground of two high pressure NMOS pipe HM7～HM8, make grid voltage stable; The positive pole of Zener diode ZD1 is connected with the emitter of ground with NPN pipe Q2 respectively with negative terminal, constitutes mu balanced circuit, the emitter output offset voltage signal V of this Q4 with NPN pipe Q3, the NPN pipe Q4 that connects _BIASTo Positive and Negative Coefficient Temperature current generating circuit 3, voltage 4 and reference voltage generating circuit 5.

Positive and Negative Coefficient Temperature current generating circuit 3 includes but not limited to 12 low pressure PMOS pipe M1～M8 and M11～M14, six bipolar transistor Q5～Q10 and two resistance R 2～R3; Collector, base stage and the emitter of the 5th NPN pipe Q5 respectively with the bias current I of pre-biased circuit output _BIASBe connected with the collector of NPN pipe Q5, Q7; The collector and emitter of the 6th NPN pipe Q6 is connected with the drain electrode of low pressure PMOS pipe M2 and the collector of NPN pipe Q8 respectively; The base stage of the 7th NPN pipe Q7 is connected with ground with the emitter of NPN pipe Q6 respectively with emitter; The base stage of the 8th NPN pipe Q8 is connected with resistance R 2 with the emitter of NPN pipe Q5 respectively with emitter; The 5th NPN pipe Q5 is 8: 1 with the ratio of the emitter area of the 6th NPN pipe Q6, the 7th NPN pipe Q7 is 1: 8 with the ratio of the emitter area of the 8th NPN pipe Q8, NPN pipe QS～Q8 constitutes translinear circuit, and this translinear circuit and resistance R 2 produce the positive temperature coefficient (PTC) electric current I ₁The base stage of the 5th NPN pipe Q5 is connected with the base stage of NPN pipe Q10, and Q10 provides voltage bias for the 9th NPN pipe, and this Q10 is connected generation negative temperature parameter current I with resistance R 3 ₂First to fourth low pressure PMOS pipe M1～M4 constitutes first common-source common-gate current mirror, the the 5th to the 8th low pressure PMOS pipe M5～M8 constitutes second common-source common-gate current mirror, this first and second common-source common-gate current mirror constitutes current adder circuit, is used for the positive temperature coefficient (PTC) electric current I ₁With negative temperature parameter current I ₂Carry out addition, Q9 provides direct current biasing for the 9th PNP pipe; The drain electrode of the 4th low pressure PMOS pipe M4 is connected the voltage V that the BE knot of this Q9 produces with the emitter of low the 6th low pressure PMOS pipe M6 and PNP pipe Q9 respectively _BEOutput to voltage 4; Seven, the 8th, the 11 and the 12 low pressure PMOS pipe M7, M8, M11 and M12 constitute the 3rd common-source common-gate current mirror, are used to export negative temperature parameter current I ₂To reference voltage generating circuit 5; First, second, the 13 and the 14 low pressure PMOS pipe M1, M2, M13 and M14 constitute the 4th common-source common-gate current mirror, is used to export the positive temperature coefficient (PTC) electric current I ₁To reference voltage generating circuit 5.

Described positive temperature coefficient (PTC) electric current I ₁Value be: $I_1=\frac{V_{\mathrm{BE}6}+V_{\mathrm{BE}7}-V_{\mathrm{BE}5}-V_{\mathrm{BE}8}}{R_2}=\frac{2V_T\ln 8}{R_2};$

Described negative temperature parameter current I ₂Value be: $I_2=\frac{V_{\mathrm{BE}6}+V_{\mathrm{BE}7}-V_{\mathrm{BE}10}}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA0000070758820000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}\&ap;\frac{V_{\mathrm{BE}6}}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA0000070758820000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3};$

Voltage V wherein _BE5, V _BE6, V _BE7, V _BE8And V _BE10Be respectively the BE junction voltage of the 5th, the 6th, the 7th, the 8th and the 9th NPN pipe Q5, Q6, Q7, Q8 and Q10, V _TBe thermal voltage, the ratio of the resistance by selecting resistance R 2 and R3 can realize flowing through the first compensation phase of the electric current of PNP pipe Q9 about temperature.

Described voltage V _BEValue be: $V_{\mathrm{BE}}=V_{G0}-(V_{G0}-V_{\mathrm{BE}0})\left(\frac{T}{T_0}\right)-(\mathrm{\&eta;}-\mathrm{\&alpha;})V_T\ln \left(\frac{T}{T_0}\right),$ V wherein _G0Be the band gap voltage of silicon, T is an absolute temperature, T ₀Be the absolute temperature of 25 ℃ of correspondences, V _BE0It is temperature T ₀The time the BE junction voltage, η is the constant that depends on the BJT tubular construction, α is the constant that depends on the emitter bipolar transistor current temperature characteristic.The electric current that flows through PNP pipe Q9 this moment is approximate temperature independent, then α=1.

Voltage 4 includes but not limited to that operation transconductance amplifier OTA, two low pressure PMOS manage M9～M10 and resistance R 4; The normal phase input end of operation transconductance amplifier OTA, inverting input and output terminal be the voltage V of connecting resistance R4, the generation of Positive and Negative Coefficient Temperature current generating circuit respectively _BEGrid with the 9th low pressure PMOS pipe M9; Operational amplifier OTA, the 9th low pressure PMOS pipe M9 and resistance R 4 constitute electric current series connection negative-feedback circuit, are used for voltage V _BEBe converted into electric current:

The the 9th and the tenth low pressure PMOS pipe M9 and M10 constitute first current mirror, are used for electric current I ₃Output to reference voltage generating circuit 5.

Reference voltage generating circuit 5 includes but not limited to two low pressure NMOS pipe M15～M16 and two resistance R 5～R6; NMOS pipe M15 and M16 constitute second current mirror, are used for the electric current I that the Positive and Negative Coefficient Temperature current generating circuit is produced ₂Produce electric current I with voltage ₃Subtract each other, the electric current after subtracting each other produces negative temperature coefficient voltage V by resistance R 5 and R6 ₁The electric current I that resistance R 6 produces by the Positive and Negative Coefficient Temperature current generating circuit ₁, produce positive temperature coefficient (PTC) voltage V ₂The both end voltage sum of resistance R 5 and R6 constitutes reference voltage V _REF, i.e. V _REF=V ₁+ V ₂

Described positive temperature coefficient (PTC) voltage V ₁Value be: V ₁=(I ₂-I ₃) (R ₅+ R ₆);

Described negative temperature coefficient voltage V ₂Value be: V ₂=I ₁R ₆

By the size of resistance R 2～R6 is set, can obtain the reference voltage of zero-temperature coefficient, its value is: $V_{\mathrm{BEF}}=(\frac{1}{R_3}-\frac{1}{R_4})(R_5+R_6)V_{G0}.$

Effect of the present invention can further specify by following emulation:

1) simulated conditions

Utilize Cadence circuit design and simulation software that the bandgap voltage reference of the wide input tape curvature temperature compensation of the present invention's proposition has been carried out emulation.The condition of emulation 1 is that supply voltage changes to 40V from 0V; The condition of emulation 2 is that supply voltage is 30V, and temperature changes to 125 ℃ from-40 ℃; The condition of emulation 3 is that supply voltage is 30V, and temperature is-40 ℃, 25 ℃, 125 ℃.

2) emulation content and result

Emulation 1 is carried out emulation to reference voltage with the variation of supply voltage, simulation result such as Fig. 3.Fig. 3 shows: when supply voltage changes at 7.2V～40V, reference voltage only changes 5.21mV, is 159uV/V with the variation of reference voltage divided by the line regulation that the variation of supply voltage obtains reference voltage, and visual reference voltage is subjected to the influence of mains voltage variations little.

Emulation 2 is carried out emulation to the temperature characterisitic of reference voltage, simulation result such as Fig. 4.Fig. 4 shows: the temperature coefficient of temperature reference voltage when changing for-40 ℃～125 ℃ only is 3.5ppm/ ℃, visual reference voltage temperature good stability.

The power supply rejection ratio characteristics of 3 pairs of reference voltages of emulation carries out emulation, simulation result such as Fig. 5.Fig. 5 shows: in the time of-40 ℃, 25 ℃, 125 ℃ the low-frequency power rejection ratio of reference voltage be respectively-96dB ,-94dB ,-83dB, the Power Supply Rejection Ratio height of visual reference voltage.

Below only be a preferred example of the present invention, do not constitute any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement, but these are all at the row of protection of the present invention its circuit.

Claims (6)

1. the bandgap voltage reference of wide input tape curvature temperature compensation comprises:

Pre-biased circuit (1) is used to curvature temperature-compensation circuit (2) that bias voltage V is provided _BIASWith bias current I _BIAS

Curvature temperature-compensation circuit (2) is used to produce the benchmark output voltage V with curvature temperature compensation _REF

It is characterized in that:

Described pre-biased circuit (1) comprises six high voltage PMOS pipe HM1～HM6, two high pressure NMOS pipe HM7～HM8, two electric capacity of voltage regulation C1～C2, four NPN pipes Q1～Q4, resistance R 1 and Zener diode ZD1; These six high voltage PMOS pipe HM1～HM6 and two high pressure NMOS pipe HM7～HM8 constitute the automatic biasing current mirror of being with source negative feedback; Resistance R 1 is connected across drain electrode and the source electrode of the first high pressure NMOS pipe HM7, and it and a NPN manage Q1 and the 2nd NPN pipe Q2 constitutes start-up circuit, makes circuit break away from the degeneracy point; Two electric capacity of voltage regulation C1～C2 are connected between the grid and ground of two high pressure NMOS pipe HM7～HM8, make grid voltage stable; Zener diode ZD1 and the 3rd NPN pipe Q3, the 4th NPN pipe Q4 constitute mu balanced circuit, the emitter output offset voltage signal V of this Q4 _BIASTo curvature temperature-compensation circuit (2).

Described curvature temperature-compensation circuit (2), comprise Positive and Negative Coefficient Temperature current generating circuit (3), voltage (4) and reference voltage generating circuit (5), the positive and negative temperature coefficient electric current I that this Positive and Negative Coefficient Temperature current generating circuit (3) produces ₁, I ₂With bipolar transistor BE junction voltage V _BE, output to reference voltage generating circuit (5) and voltage (4) respectively; This voltage (4) is with bipolar transistor BE junction voltage V _BEBe converted into electric current I ₃, and output to reference voltage generating circuit (5), by reference voltage generating circuit (5), produce reference voltage V _REF

2. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation, it is characterized in that: described Positive and Negative Coefficient Temperature current generating circuit (3) comprises 12 low pressure PMOS pipe M1～M8 and M11～M14, six bipolar transistor Q5～Q10 and two resistance R 2～R3; The collector of the 5th NPN pipe Q5 and the bias current I of pre-biased circuit (1) output _BIASConnect, obtain direct current biasing; The 5th NPN pipe Q5, the 6th NPN pipe Q6, the 7th NPN pipe Q7 and the 8th NPN pipe Q8 constitute translinear circuit, and this translinear circuit and resistance R 2 produce the positive temperature coefficient (PTC) electric current I ₁The base stage of the 5th NPN pipe Q5 is connected with the base stage of NPN pipe Q10, and for described Q10 provides voltage bias, this Q10 is connected generation negative temperature parameter current I with resistance R 3 ₂Low pressure PMOS pipe M1～M4 constitutes first common-source common-gate current mirror, low pressure PMOS pipe M5～M8 constitutes second common-source common-gate current mirror, the drain electrode of low pressure PMOS pipe M4 is connected with the emitter of low pressure PMOS pipe M6, PNP pipe Q9 respectively, first and second common-source common-gate current mirrors constitute current adder circuit, are used for the positive temperature coefficient (PTC) electric current I ₁With negative temperature parameter current I ₂Carry out addition, Q9 provides direct current biasing for the 9th PNP pipe, the voltage V that the BE knot of this Q9 produces _BEOutput to voltage (4); Low pressure PMOS pipe M7, M8, M11 and M12 constitute the 3rd common-source common-gate current mirror, and export negative temperature parameter current I by the drain electrode of low pressure PMOS pipe M12 ₂To reference voltage generating circuit (5); Low pressure PMOS pipe M1, M2, M13 and M14 constitute the 4th common-source common-gate current mirror, and export the positive temperature coefficient (PTC) electric current I by the drain electrode of low pressure PMOS pipe M14 ₁To reference voltage generating circuit (5).

3. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: described voltage (4) comprises that operation transconductance amplifier OTA, two low pressure PMOS manage M9～M10 and resistance R 4; The normal phase input end of operation transconductance amplifier OTA, inverting input and output terminal be the voltage V of connecting resistance R4, the generation of Positive and Negative Coefficient Temperature current generating circuit respectively _BEWith the grid of low pressure PMOS pipe M9, operational amplifier OTA, low pressure PMOS pipe M9 and resistance R 4 constitute electric current series connection negative-feedback circuit, are used for voltage V _BEBe converted into electric current I ₃Low pressure PMOS pipe M9 and M10 constitute first current mirror, are used for electric current I ₃Output to reference voltage generating circuit (5).

4. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: described reference voltage generating circuit (5) comprises two low pressure NMOS pipe M15～M16 and two resistance R 5～R6; Low pressure NMOS pipe M15 and M16 constitute second current mirror, are used for the electric current I that Positive and Negative Coefficient Temperature current generating circuit (3) is produced ₂Produce electric current I with voltage (4) ₃Subtract each other, the electric current after subtracting each other produces negative temperature coefficient voltage V by resistance R 5 and R6 ₁The electric current I that resistance R 6 produces by Positive and Negative Coefficient Temperature current generating circuit (3) ₁, produce positive temperature coefficient (PTC) voltage V ₂The both end voltage sum of resistance R 5 and R6 constitutes reference voltage V _REF, i.e. V _REF=V ₁+ V ₂

5. the bandgap voltage reference of wide input tape curvature according to claim 1 temperature compensation is characterized in that: the mutual conductance of high voltage PMOS pipe HM1 is greater than the mutual conductance of HM3.

6. the bandgap voltage reference of wide input tape curvature according to claim 2 temperature compensation, it is characterized in that: the 5th NPN pipe Q5 is 8: 1 with the ratio of the emitter area of the 6th NPN pipe Q6, and the 7th NPN pipe Q7 is 1: 8 with the ratio of the emitter area of the 8th NPN pipe Q8.

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