CN104460799B - CMOS reference voltage source circuits - Google Patents
CMOS reference voltage source circuits Download PDFInfo
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Abstract
The invention discloses a kind of CMOS reference voltage source circuits, including：Start-up circuit, which is after DC source is connected, there is provided start voltage；First bias current generating circuit, for receiving the startup voltage of start-up circuit offer, produces the first bias current, and provides output voltage, and the temperature coefficient direction of the first bias current is first direction；Second bias current generating circuit, for receiving the output voltage of the first bias current generating circuit offer as input, produces the second bias current, and the temperature coefficient direction of the second bias current is second direction；Reference voltage generating circuit, for receiving the first bias current and the second bias current as input, obtains reference voltage by adjusting first, second bias current.The present invention improves the reliability of reference voltage source circuit and motility.
Description
Technical field
The present invention relates to CMOS transistor field of circuit technology, more particularly to CMOS reference voltage source circuits.
Background technology
In simulation, reference voltage source in numerical model analysis, and digital circuit, is often used, its stability is directly connected to
The performance of whole circuit.General conventional reference voltage source is to adopt BiCMOS technique, a kind of traditional bandgap base that such as Fig. 1 is given
Reference voltage source circuit, including triode transistor Q1And Q2, error amplifier OP, feedback resistance R1And R2, adjust resistance R3；Transistor
Q1And Q2Emitter stage analogue ground AVSS, two inputs of amplifier difference connecting nodes A and B, outfan output VREF, while
Connection resistance R1And R2.In profound and negative feedbck, two inputs distinguish connecting nodes A and B to amplifier operation, make two point voltage phases
Deng while connecting two resistance identical resistance R1And R2, make to flow through Q1And Q2Two-way electric current it is equal, so as to obtain：
VBE1-VBE2=I2R3=VT lnN (1)
And then obtain output voltage VO UT：
The circuit there are problems that it is following two, first, usual VREFFor 1.25V or so, it is impossible to apply in low-voltage circuit；
Secondly, the method needs to be realized using transistor and metal-oxide-semiconductor jointly, and requirement is proposed to technique.
Fig. 2 gives a kind of improved plan, M in band-gap circuit1, M2And M3Composition current mirror, amplifier OP1In .0
Profound and negative feedbck state, makes two point voltages of AB equal, is VBE, that is, flow through R2Electric current be VBE/R2, with negative temperature coefficient, and
By resistance R1Electric current be electric current with VT direct proportionalities, two-way electric current sum flows through M2, it is copied to I3, then resistance
R3 both end voltages are：
It is appropriate to choose N, R1, R2And R3The output voltage V of zero-temperature coefficient can be obtainedREF, and the temperature of output voltage
Coefficient and R3Mutually independent, that is, the bandgap voltage reference for exporting can be adjusted.But the circuit has equally used crystal with technology one
Pipe, needs to use BiCMOS technique, this reference circuit cannot be used under CMOS technology.
Fig. 3 gives a kind of band-gap reference circuit of CMOS technology, M in the band-gap circuit1And M3It is operated in sub-threshold region,
M is flow through1And M3Electric current be respectively
M2And M4Pipe connects into current mirror form, and breadth length ratio is equal, i.e.,
I1=I2 (6)
Jing (4), (5), (6) obtain
Understand to flow through resistance R1Electric current be
I2Temperature coefficient and VTProportional, i.e. I2For positive temperature coefficient electric current.
M6Pipe and M4Pipe forms current mirror, is M5Stable drain-source current, M are provided7The clamped M of gate source voltage of pipe5Drain-gate
Voltage, makes M5Steady operation is in sub-threshold region.Flow through resistance R2Electric current I4For
The gate source voltage of sub-threshold region metal-oxide-semiconductor has negative temperature coefficient, i.e. electric current I4For negative temperature parameter current.M9And M4、
M10And M8Current mirror, i.e. I are formed respectively5、I6Positive temperature coefficient electric current and negative temperature parameter current, superposition and resistance are replicated respectively
R3, form the output voltage V of zero-temperature coefficientREF。
The shortcoming of the circuit is M1、M3Sub-threshold region is operated in all, gate source voltage is less, but R1Needs get a part
Pressure drop, so M1、M3Gate source voltage have significant difference.By process deviation influence, M in side circuit1Gate source voltage have can
Can exceed that threshold voltage, it is impossible to which guarantee is operated in sub-threshold region, produce estimated positive temperature coefficient electric current, thus reliability compared with
Difference.
The processing compatibility of the band-gap reference circuit in order to improve Fig. 1, shown in 2, it is necessary to using cmos circuit structure.Except this
Outside, in order to improve the motility of reference circuit output voltage shown in Fig. 1, while the stability of reference circuit shown in Fig. 3 is improved,
Then need using new circuit structure.
The content of the invention
For the problems referred to above, it is an object of the invention to design be suitable to what is realized in CMOS technology, high reliability and spirit
The reference voltage source circuit of activity.
The present invention is adopted the following technical scheme that：A kind of CMOS reference voltage source circuits, including：Start-up circuit, which is being connected
After DC source, there is provided start voltage；First bias current generating circuit, for receiving the startup voltage of start-up circuit offer,
The first bias current is produced, and output voltage is provided, the temperature coefficient direction of the first bias current is first direction；Second biasing
Current generating circuit, for receiving the output voltage of the first bias current generating circuit offer as input, produces second and biases
Electric current, the temperature coefficient direction of the second bias current is second direction；Reference voltage generating circuit, for receiving the first biased electrical
Stream and the second bias current obtain reference voltage by adjusting first, second bias current as input.
The present invention realizes that using standard CMOS process circuit structure does not need triode transistor；Adopted two-way temperature simultaneously
The different electric current of degree characteristic is superimposed on the mode of same resistance, the benchmark that the voltage at resistance two ends is gone to zero as temperature coefficient
Voltage, therefore reference voltage value can be with flexible, with suitable for different circuit requirements；Additionally, what is adopted is operated in subthreshold
The MOS device in value area, increased matching and negative feedback design, therefore the circuit structure is difficult by process deviation and voltage dithering
Affect, it is ensured that the reliability of whole reference voltage source circuit.Realize that the circuit of the bandgap voltage reference produces two-way temperature system
The contrary electric current of number variation tendency, two-way electric current are superimposed on same resistance, the appropriate ratio for adjusting two-way electric current, and formation can
The bandgap voltage reference of flexible.
The CMOS reference voltage sources of the present invention, with clear advantage and positive effect, and at many aspects due to mesh
Front conventional reference voltage source circuit.
(1) audion is not contained in circuit of the present invention, only includes NMOS tube, PMOS, three kinds of devices of resistance, therefore, have
The advantage of process is simple, realizes that on CMOS technology line convenient, effective, compatibility is good；
(2) present invention adopts new sub-threshold region CMOS reference circuit structures, increased the metal-oxide-semiconductor for being operated in sub-threshold region
Structural parameters and working condition matching, compared to traditional reference circuit containing sub-threshold region device, reduce technique
Impact of the deviation to the normal realization of circuit function, improves the stability of sub-threshold region device work in circuit, it is ensured that CMOS
The reliability of reference voltage source；
(3) it is of the invention by the way of two-way temperature characterisitic different electric currents is superimposed on same resistance, by resistance two ends
The reference voltage that goes to zero as temperature coefficient of voltage, therefore reference voltage value can be with flexible, with suitable for different
Circuit requirements.
Description of the drawings
By reading the detailed description made to non-limiting example made with reference to the following drawings, other of the invention
Feature, objects and advantages will become more apparent upon, and in accompanying drawing, same or analogous reference represents same or analogous part.
Fig. 1 show prior art 1, is using BiCMOS technique band gap reference voltage source circuit；
Fig. 2 show prior art 2, is using BiCMOS technique band gap reference voltage source circuit；
Fig. 3 show prior art 3, is a kind of sub-threshold region CMOS reference voltage source circuits；
Fig. 4 show CMOS reference voltage source circuits modular structure schematic diagram of the present invention；
Fig. 5 show CMOS reference voltage source circuits figure of the present invention.
Specific embodiment
Below by way of the present invention specific embodiment and combine accompanying drawing, to the purpose of the present invention, circuit structure and advantage make
Further describe.
Fig. 4 is CMOS reference voltage source circuit modular structure schematic diagrams, and the circuit includes start-up circuit 101, the first biasing
Current generating circuit 102, the second bias current generating circuit 103, reference voltage generating circuit 104；Start-up circuit 101, first
Bias current generating circuit 102, the second bias current generating circuit 103, the DC supply input end of reference voltage generating circuit 104
Connect DC source VDD respectively, the input of the first bias current generating circuit 102 connects the outfan of start-up circuit 101, the
The outfan of one bias current generating circuit 102 is connected to the first input end of reference voltage generating circuit 104 and the second biasing
The input of current generating circuit 103, the outfan of the second bias current generating circuit 103 are connected to reference voltage generating circuit
104 the second input, the reference voltage output end output reference voltage of reference voltage generating circuit 104.
Fig. 5 is CMOS reference voltage source circuit figures.Start-up circuit 101 is by PMOS MS1、MS2With NMOS tube MS3Composition,
PMOS MS1Source electrode, PMOS MS2Source electrode and NMOS tube MS3Grid as start-up circuit 101 DC supply input
End, PMOS MS1Drain electrode respectively with PMOS MS2Grid and NMOS tube MS3Drain electrode be connected, NMOS tube MS3Source electrode connect public affairs
Holding altogether, PMOS MS1Grid and PMOS MS2Drain electrode respectively as start-up circuit 101 first, second outfan；
First bias current generating circuit 102 is by 4 PMOSs M3, M4, M5And M6, 2 NMOS tubes M7And M8And 2 electric
Resistance R1And R2Composition, PMOS M1And M3Source electrode as DC supply input end, the first outfan of start-up circuit 101 and PMOS
Pipe M1And M3Grid, and M3Drain electrode connect altogether, and the first outfan as the first bias current generating circuit 102 and
The first input end of two bias current generating circuits 103, and reference voltage generating circuit 104 first input end be connected,
PMOS M1Drain electrode and PMOS M2Source electrode be connected, PMOS M3Drain electrode and PMOS M4Source electrode be connected, PMOS M2
Grid and PMOS M4Grid and drain electrode connect altogether, and the second outfan as the first bias current generating circuit 102 with
Second input of the second bias current generating circuit 103, and reference voltage generating circuit 104 the second input be connected,
101 second outfan of start-up circuit respectively with PMOS M2Drain electrode, NMOS tube M5Drain and gate, and NMOS tube M6Grid
Extremely connect altogether, PMOS M4Drain electrode and NMOS tube M6Drain electrode be connected, NMOS tube M5Source electrode and resistance R1It is connected, resistance R1It is another
One termination common, NMOS tube M6Source electrode and resistance R2It is connected, resistance R2Another termination common.
Second bias current generating circuit 103 is by 6 PMOSs M7, M8, M11、M12、M13And M14, 2 NMOS tubes M9And M10
And a resistance R3Composition, PMOS M7, PMOS13With PMOS M11Source electrode as DC supply input end, the first biasing
First outfan of current generating circuit 102 and PMOS M7Grid be connected, PMOS M7Drain electrode and PMOS M8Source electrode
It is connected, PMOS M8Grid be connected with the second outfan of the first bias current generating circuit 102, PMOS M8Drain electrode with
NMOS tube M9Drain electrode and NMOS tube M10Grid connect altogether, NMOS tube M9Source electrode connect common, PMOS M13Grid and
Drain electrode, and PMOS M11Grid connect altogether, and the first outfan as the second bias current generating circuit 103 and benchmark electricity
Pressure produces the first input end of circuit 104 and is connected, PMOS M13Drain electrode and PMOS M14Source electrode be connected, PMOS M11's
Drain electrode and PMOS M12Source electrode be connected, PMOS M14Grid and drain electrode, and PMOS M12Grid connect altogether, and conduct
Second outfan of the second bias current generating circuit 103 is connected with the second input of reference voltage generating circuit 104, PMOS
Pipe M14Drain electrode and NMOS tube M10Drain electrode be connected, NMOS tube M10Source electrode connect common, PMOS M12Drain electrode and NMOS
Pipe M9Grid and resistance R3Connect altogether, resistance R3Another termination common.
Reference voltage generating circuit 104 is by 4 PMOSs M15, M16, M17And M18, a resistance R4Composition, PMOS M15's
Source electrode and PMOS M17Source electrode as DC supply input end, PMOS M15Grid and the first bias current generating circuit 102
The first outfan be connected, PMOS M17Grid be connected with the first outfan of the second bias current generating circuit 103, PMOS
Pipe M15Drain electrode and PMOS M16Source electrode be connected, PMOS M17Drain electrode and PMOS M18Source electrode be connected, PMOS M16
Grid be connected with the second outfan of the first bias current generating circuit 102, PMOS M18Grid and the second bias current
The second outfan for producing circuit 103 is connected, PMOS M16Drain electrode and PMOS M18Drain electrode be connected to resistance R altogether4, and conduct
Reference voltage output end, resistance R4Another termination common.
The course of work of the circuit of the present invention：As connection direct current power source voltage VDDWhen, NMOS tube MS3Open, by PMOS
MS2Grid voltage be pulled down to and be close to common voltage, MS2Pipe is opened, and is provided enough for 101 second outfan of start-up circuit
Voltage, is PMOS M5And M6Gate charges, it is ensured that metal-oxide-semiconductor open, circuit work depart from off state.
PMOS M in first bias current generating circuit 1021, M2, M3And M4For common-source common-gate current mirror, wherein M1、M3
And M2、M4Breadth length ratio it is equal so that I1=I2, while resistance R1=R2So that NMOS tube M5And M6Gate source voltage it is equal, M5
And M6Sub-threshold region is operated in, and working condition is approximately the same, i.e.,
Wherein NMOS tube M5Source voltage VGS5=I1·R1, (10) are obtained with Taylor function approximate expansion
So as to obtain I1Expression formula
Understand that wherein relevant with temperature variable is VTAnd VG5.PMOS M1, M2, M3And M4Saturation region is operated in, its source grid
Voltage has positive temperature coefficient property, V when temperature is raisedSGIncrease, saturation depth increase, VSD1、VSD2Reduce, therefore VG5Increase；
V is known againTFor positive temperature coefficient parameter, therefore I1Raise with temperature and increase.Jing 0.18um 3.3v SOI CMOS technologies are emulated,
-- in 50-150 degree temperature ranges, electric current I1Temperature curve be approximately first order linear curve.
In the second bias current generating circuit 103, PMOS M7And M8Form current mirror and replicate I2, it is NMOS tube M9Carry
For bias current；While resistance R3Two sections meet M respectively9Grid and source electrode, therefore flow through R3Electric current be
M9It is operated in sub-threshold region, VGS9With negative temperature coefficient, therefore I4For negative temperature parameter current.Wherein M9, M10,
M11, M12,M13, M14And R3Connect for negative feedback, feedback regulation M9Gate source voltage keep steady statue, not with voltage or electric current
Shake and change.
In reference voltage generating circuit, Positive and Negative Coefficient Temperature electric current is overlapped；PMOS M15And M16Replicate positive temperature
Coefficient current I1, PMOS M17And M18Replicate negative temperature parameter current I4, two-way replica current I6And I7Flow through jointly resistance R4,
Obtain reference voltage VREF, i.e.,
VREF=(I6+I7)R4=(AI1+BI4)R4 (14)
As can be seen that by appropriate adjustment factor A, B, the i.e. ratio of Positive and Negative Coefficient Temperature electric current, zero-temperature coefficient can be produced
The reference voltage of coefficient.Meanwhile, by adjusting R4Resistance, can be with the value of flexible reference voltage, it is adaptable to different electricity
Road demand.
In the circuit design, two-way current generating circuit is negative feedback structure, and stability under working conditions is good, and in Asia
The working condition of the metal-oxide-semiconductor of threshold zone is consistent, and can reduce impact of the process deviation to which, in addition, this circuit energy
CMOS technology is enough fully compatible with, and the reference voltage of circuit output can be according to different demands, by adjusting R4Resistance enter
Row flexible.
Claims (5)
1. a kind of CMOS reference voltage source circuits, it is characterised in that include：
Start-up circuit, which is after DC source is connected, there is provided start voltage；Wherein, the start-up circuit is included：First PMOS
(MS2) and the first NMOS tube (MS3)；First PMOS (MS2) source electrode and the first NMOS tube (MS3) grid be connected to startup electricity
DC supply input end (the V on roadDD), the first PMOS (MS2) grid be connected to the first NMOS tube (MS3) drain electrode, a NMOS
Pipe (MS3) source ground, the first PMOS (MS2) drain electrode be connected to the first biasing as the first outfan of start-up circuit
The first input end of current generating circuit；
First bias current generating circuit, for receiving the startup voltage of start-up circuit offer, produces the first bias current, and carries
For output voltage, the temperature coefficient direction of the first bias current is first direction；Wherein, first bias current generating circuit
Comprising：Second NMOS tube (M5), the 3rd NMOS tube (M6), first resistor (R1) and second resistance (R2)；Second NMOS tube (M5)
Grid and drain electrode and the 3rd NMOS tube (M6) grid connect altogether and the first input end as the first bias current generating circuit with
The start-up circuit is connected, the second NMOS tube (M5) source electrode and first resistor (R1) one end be connected, first resistor (R1) other end
Ground connection, the 3rd NMOS tube (M6) source electrode and second resistance (R2) one end be connected, second resistance (R2) other end ground connection；
Second bias current generating circuit, for receiving the output voltage of the first bias current generating circuit offer as input,
The second bias current is produced, the temperature coefficient direction of the second bias current is second direction；Wherein, the second biased electrical miscarriage
Comprising for replicating the current mirroring circuit of the first bias current, the current mirroring circuit includes the 7th PMOS (M to raw circuit7),
Eight PMOS (M8) and the 4th NMOS tube (M9)；7th PMOS (M7) source electrode meet DC supply input end (VDD), the 7th PMOS
(M7) drain electrode and the 8th PMOS (M8) source electrode connect, the 8th PMOS (M8) drain electrode and the 4th NMOS tube (M9) leakage
Pole connects, the 4th NMOS tube (M9) source electrode meet common, the 7th PMOS (M7) grid produce as the second bias current
Second input of circuit is connected with the second outfan of the first bias current generating circuit, the 8th PMOS (M8) grid make
It is connected with the first outfan of the first bias current generating circuit for the first input end of the second bias current generating circuit；
Reference voltage generating circuit, for receiving the first bias current and the second bias current as input, by adjustment first,
Second bias current obtains reference voltage；Wherein, the reference voltage generating circuit includes the 13rd PMOS (M15), the 14th
PMOS (M16), the 15th PMOS (M17), the 16th PMOS (M18) and the 4th resistance (R4)；13rd PMOS (M15)
With the 14th PMOS (M16) circuit that formed is used to replicate the first bias current, the 15th PMOS (M17) and the 16th
PMOS (M18) circuit that formed is used to replicate the second bias current；13rd PMOS (M15) source electrode and the 15th PMOS
Pipe (M17) source electrode be connected to DC supply input end (VDD), the 13rd PMOS (M15) grid be connected to the first bias current
Produce the second outfan of circuit, the 15th PMOS (M17) grid be connected to the second defeated of the second bias current generating circuit
Go out end, the 13rd PMOS (M15) drain electrode be connected to the 14th PMOS (M16) source electrode, the 15th PMOS (M17) leakage
Pole is connected to the 16th PMOS (M18) source electrode, the 14th PMOS (M16) grid be connected to the first bias current generation
First outfan of circuit, the 16th PMOS (M18) grid be connected to the second bias current generating circuit first output
End, the 14th PMOS (M16) drain electrode and the 16th PMOS (M18) drain electrode and the 4th resistance (R4) one end connect altogether, and
As reference voltage output end (VREF), the 4th resistance (R4) the other end be connected to common.
2. CMOS reference voltage source circuits according to claim 1, wherein the start-up circuit is also included：Second PMOS
(MS1)；Second PMOS (MS1) source electrode be connected to DC supply input end (VDD), the second PMOS (MS1) drain electrode and described
One PMOS (MS2) grid and the first NMOS tube (MS3) drain electrode connect altogether, the second PMOS (MS1) grid as opening
Second outfan on galvanic electricity road is connected to the second input of first bias current generating circuit.
3. CMOS reference voltage source circuits according to claim 1, wherein first bias current generating circuit is also wrapped
Containing the first common-source common-gate current mirror circuit, for by the second NMOS tube (M5) and the 3rd NMOS tube (M6) sub-threshold region is biased in, and
Guarantee flows through first resistor (R1) electric current be equal to flow through second resistance (R2) electric current；First common-source common-gate current mirror circuit bag
Containing the 3rd PMOS (M1), the 4th PMOS (M2), the 5th PMOS (M3) and the 6th PMOS (M4)；3rd PMOS (M1)
Source electrode and the 5th PMOS (M3) source electrode be connected to DC supply input end (VDD), the 3rd PMOS (M1) grid, the 5th
PMOS (M3) grid, the second outfan of start-up circuit connect altogether, and as the first bias current generating circuit second defeated
Go out end, the 3rd PMOS (M1) drain electrode be connected to the 4th PMOS (M2) source electrode, the 5th PMOS (M3) drain electrode be connected to
6th PMOS (M4) source electrode, and with the 5th PMOS (M3) grid connect altogether, the 4th PMOS (M2) grid and the 6th
PMOS (M4) grid connect altogether and as the first outfan of the first bias current generating circuit, the 4th PMOS (M2) leakage
Pole is connected to the second NMOS tube (M5) drain electrode, the 6th PMOS (M4) drain electrode be connected to the 3rd NMOS tube (M6)
Drain electrode.
4. CMOS reference voltage source circuits according to claim 1, wherein second bias current generating circuit is also wrapped
Contain：5th NMOS tube (M10), the 9th PMOS (M11), the tenth PMOS (M12), the 11st PMOS (M13), the 12nd PMOS
Pipe (M14) and 3rd resistor (R3)；Wherein the 9th PMOS (M11), the tenth PMOS (M12), the 11st PMOS (M13) and the
12 PMOS (M14) for the second common-source common-gate current mirror circuit of formation, it is ensured that through 3rd resistor (R3) and the 5th NMOS tube
(M10) electric current it is equal；9th PMOS (M11) source electrode and the 11st PMOS (M13) source electrode be connected to DC supply input
End (VDD), the 9th PMOS (M11) grid and the 11st PMOS (M13) grid and drain electrode connect altogether, and as second biasing
Second outfan of current generating circuit, the 9th PMOS (M11) drain electrode be connected to the tenth PMOS (M12) source electrode, the tenth
One PMOS (M13) drain electrode be connected to the 12nd PMOS (M14) source electrode, the tenth PMOS (M12) grid and the 12nd
PMOS (M14) grid and drain electrode connect altogether, and as the first outfan of the second bias current generating circuit, the 12nd PMOS
Pipe (M14) drain electrode be connected to the 5th NMOS tube (M10) drain electrode, the 5th NMOS tube (M10) source ground, the 5th NMOS tube
(M10) grid and the 4th NMOS tube (M9) drain electrode be connected, the tenth PMOS (M12) drain electrode and the 4th NMOS tube
(M9) grid connect altogether, and be connected to 3rd resistor (R3) one end, 3rd resistor (R3) the other end ground connection.
5. CMOS reference voltage source circuits according to claim 1, wherein the first direction is for just, the second direction
It is negative.
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| CN107066015B (en) * | 2017-04-19 | 2018-03-09 | 桂林电子科技大学 | A kind of full cascade reference voltage source |
| CN107179798A (en) * | 2017-07-10 | 2017-09-19 | 北京兆芯电子科技有限公司 | Reference voltage generating circuit and method |
| KR102347178B1 (en) * | 2017-07-19 | 2022-01-04 | 삼성전자주식회사 | Terminal device having reference voltage circuit |
| CN112783256B (en) * | 2019-11-08 | 2022-06-24 | 奇景光电股份有限公司 | Low dropout regulator based on subthreshold region |
| CN111880599B (en) * | 2020-07-11 | 2021-06-22 | 许昌学院 | High-precision reference voltage source for resisting production process deviation |
| CN115268560A (en) * | 2021-04-30 | 2022-11-01 | 炬芯科技股份有限公司 | Reference voltage generating circuit and integrated chip |
| CN114578889B (en) * | 2022-03-08 | 2023-10-17 | 安徽传矽微电子有限公司 | Controllable low-power consumption CMOS reference source and module and chip thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101004618A (en) * | 2006-12-28 | 2007-07-25 | 东南大学 | CMOS reference source circuit |
| CN101013331A (en) * | 2006-12-28 | 2007-08-08 | 东南大学 | CMOS reference voltage source with adjustable output voltage |
| CN101178610A (en) * | 2007-12-05 | 2008-05-14 | 西安标新电子科技有限责任公司 | Circuit outputting adjustable positive and negative or zero-temperature coefficient electrical current and voltage reference |
| CN101571728A (en) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | Non-bandgap high-precision reference voltage source |
| CN102096436A (en) * | 2011-03-15 | 2011-06-15 | 清华大学 | Low-voltage low-power band gap reference voltage source implemented by MOS device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7113025B2 (en) * | 2004-04-16 | 2006-09-26 | Raum Technology Corp. | Low-voltage bandgap voltage reference circuit |
| US7728574B2 (en) * | 2006-02-17 | 2010-06-01 | Micron Technology, Inc. | Reference circuit with start-up control, generator, device, system and method including same |
-
2014
- 2014-11-24 CN CN201410683487.8A patent/CN104460799B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101004618A (en) * | 2006-12-28 | 2007-07-25 | 东南大学 | CMOS reference source circuit |
| CN101013331A (en) * | 2006-12-28 | 2007-08-08 | 东南大学 | CMOS reference voltage source with adjustable output voltage |
| CN101178610A (en) * | 2007-12-05 | 2008-05-14 | 西安标新电子科技有限责任公司 | Circuit outputting adjustable positive and negative or zero-temperature coefficient electrical current and voltage reference |
| CN101571728A (en) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | Non-bandgap high-precision reference voltage source |
| CN102096436A (en) * | 2011-03-15 | 2011-06-15 | 清华大学 | Low-voltage low-power band gap reference voltage source implemented by MOS device |
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| CN104460799A (en) | 2015-03-25 |
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