CN107300943A - A kind of bias current generating circuit - Google Patents
A kind of bias current generating circuit Download PDFInfo
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- CN107300943A CN107300943A CN201710693312.9A CN201710693312A CN107300943A CN 107300943 A CN107300943 A CN 107300943A CN 201710693312 A CN201710693312 A CN 201710693312A CN 107300943 A CN107300943 A CN 107300943A
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- pmos
- nmos tube
- grid
- current
- drain electrode
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Automation & Control Theory (AREA)
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Abstract
The invention discloses a kind of bias current generating circuit, this bias current generating circuit is formed by stacking by two branch current generation circuits, wherein first branch current generation circuit is positive temperature coefficient current generating circuit, and another branch current generation circuit is negative temperature parameter current generation circuit.In described positive temperature coefficient current generating unit, draw one and control voltage to the negative temperature parameter current generation unit, for producing negative temperature parameter current, then export described positive temperature coefficient electric current and negative temperature parameter current superposition.In described negative temperature parameter current generation unit, draw one and control voltage to positive temperature coefficient current generating unit, for stability contorting loop, reduce output current and be influenced by temperature.Compared with prior art, present invention eliminates transistor circuit, band-gap reference circuit is eliminated, the amplifier circuit of complexity is eliminated, circuit area and power consumption is reduced, while improving the overall performance of circuit.
Description
Technical field
The present invention relates to integrated circuit fields, espespecially a kind of bias current generating circuit.
Background technology
Conventional simple bias current generating circuit, i.e., as shown in figure 1, by PMOS M3, PMOS M4, PMOS
M5, and NMOS tube M1, NMOS tube M2 and resistance RB compositions.Thus the current generating circuit constituted, and supply voltage are unrelated, but
It is relevant with temperature.Because the resistance of resistance is changed with the change of temperature.The calculation formula of specific electric current is as follows：
Wherein, RBIt is resistance, μNIt is the mobility of electronics in NMOS tube raceway groove, Cox is NMOS oxide layer unit areas
Capacitance,It is NMOS tube M1 channel width and length ratio,Be NMOS tube M2 channel width and length it
Than.Because RBAnd μNAll it is influenced by temperature, so the output current IB that can be seen that circuit from above-mentioned formula is affected by temperature
It is very big.
Bias current generating circuit is typically necessary to realize to the insensitive of temperature change and enters trip temperature benefit to circuit
Repay.Wherein general temperature compensation is to produce two-way bias current to be overlapped, and one of them is positive temperature coefficient electric current,
Another is negative temperature parameter current.After the superposition of two-way electric current, the change influence of total output current on temperature is smaller.But one
As this circuit need two temperature coefficient generation circuits, circuit is complicated, and power consumption and area of circuit etc. are all than larger.
The content of the invention
To solve the above problems, the present invention provides a kind of bias current generating circuit, it is folded by two branch current units
Plus form, eliminate the amplifier circuit of complexity.Circuit area and power consumption are reduced, performance is improved.
The technical solution adopted by the present invention is：A kind of bias current generating circuit, including positive temperature coefficient electric current produce list
Member, negative temperature parameter current generation unit；Wherein described positive temperature coefficient current generating unit and negative temperature parameter current are produced
Unit is connected；Wherein described positive temperature coefficient current generating unit produces positive temperature coefficient electric current IPTAT3, the negative temperature
Coefficient current generation unit produces negative temperature parameter current ICTAT3, and the positive temperature coefficient electric current IPTAT3 and negative temperature system
The ICTAT3 superpositions of number electric current are output to electric current IOUT.Wherein described positive temperature coefficient current generating unit includes the first NMOS tube
M1, the second NMOS tube M2, first resistor RB, the 3rd PMOS M3, the 4th PMOS M4, the 5th PMOS M5；Wherein described
Three PMOS M3, the 4th PMOS M4, the 5th PMOS M5 source electrode are connected with supply voltage VDD respectively, wherein the described 3rd
PMOS M3 drain and gate is connected with each other, and the grid of the 3rd PMOS M3 is connected with the 4th PMOS M4 grid,
The grid of the 4th PMOS M4 is connected with the 5th PMOS M5 grid, and drain electrode and the circuit of the 5th PMOS M5
Output end is connected；Wherein described first NMOS tube M1 drain electrode is connected with the 3rd PMOS M3 drain electrode, first NMOS tube
M1 source electrode is connected by first resistor RB with ground, and the grid of the first NMOS tube M1 and the second NMOS tube M2 grid connect
Connect；The source electrode of the second NMOS tube M2 connects with ground, the drain electrode and the 4th PMOS M4 drain electrode of the second NMOS tube M2
Connect, wherein the drain and gate of the second NMOS tube M2 connects with negative temperature parameter current generation unit respectively.
Specifically, wherein it is electric current IPTAT1, the positive temperature to flow through the electric current between the 3rd PMOS M3 source electrodes and drain electrode
Coefficient current IPTAT3 flows through the 5th PMOS M5 source electrodes and drains and exported by circuit output end；The electric current IPTAT2 streams
Enter to the second NMOS tube M2 and produce control voltage, and negative temperature parameter current generation is output to by the second NMOS tube M2 drain electrode
Unit, and it is used as the control voltage of negative temperature parameter current generation circuit so that negative temperature parameter current generation unit produces negative
Temperature coefficient current ICTAT3.
Specifically, in the positive temperature coefficient current generating unit, in addition to second resistance R2, electric capacity C1, wherein described
The drain electrode of second resistance R2 one end and the second NMOS tube M2 is connected, and the other end is connected with electric capacity C1, the electric capacity C1 other ends and
One NMOS tube M1 grid is connected.
Specifically, the negative temperature parameter current generation unit, including the 6th PMOS M6, the 7th PMOS M7, the 8th
PMOS M8, the 9th NMOS tube M9,3rd resistor R3；Wherein described 6th PMOS M6, the 7th PMOS M7, the 8th PMOS
M8 source electrode is connected with supply voltage VDD respectively, and the 6th PMOS M6 drain and gate is connected with each other, the 6th PMOS M6's
Grid and the 7th PMOS M7 grid connect, and the 7th PMOS M7 grid is connected with the 8th PMOS M8 grid, and institute
The drain electrode for stating the 8th PMOS M8 is connected with circuit output end；Wherein described 7th PMOS M7 drain electrode passes through 3rd resistor R3
Connect with ground, the drain electrode of the 7th PMOS M7 is connected with the first NMOS tube M1 grid；Wherein described 9th NMOS tube M9
Drain electrode be connected with the 6th PMOS M6 drain electrode, the source electrode of the 9th NMOS tube M9 connects with ground, the 9th NMOS tube
M9 grid connects with the second NMOS tube M2 drain electrode.
Specifically, wherein it is electric current ICTAT2, the negative temperature to flow through the electric current between the 7th PMOS M7 source electrodes and drain electrode
Coefficient current ICTAT3 flows through the 8th PMOS M8 source electrodes and drains and exported by circuit output end；Wherein electric current ICTAT2 flows
Enter to the 3rd resistor R3 control voltages produced to feed back to the first NMOS tube M1 and the second NMOS tube M2 grid, be used as positive temperature
The control voltage of coefficient current generation circuit so that positive temperature coefficient current generating unit produces positive temperature coefficient electric current
IPTAT3。
The beneficial effects of the present invention are：This bias current circuit is formed by stacking by two branch current circuits, wherein one
Individual affluent-dividing is positive temperature coefficient current unit, and another branch current is negative temperature parameter current unit, and by circuit output
Superimposed current IOUT so that the change of temperature diminishes to the influence for exporting superimposed current IOUT；Relative to existing technology, the present invention is saved
Transistor circuit has been removed, band-gap reference circuit is eliminated, the amplifier circuit of complexity has been eliminated, circuit area can be greatly reduced
And power consumption, while improving the overall performance of circuit.
Brief description of the drawings
Fig. 1 is prior art bias current generating circuit structural representation；
Fig. 2 is electrical block diagram in the present invention；
Fig. 3 is that positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3 varies with temperature signal in the present invention
Figure；
Fig. 4 is that superimposed current IOUT varies with temperature schematic diagram in the present invention；
Drawing reference numeral explanation：1- positive temperature coefficient current generating units；2- negative temperature parameter current generation units；
Embodiment
Refer to shown in Fig. 2, a kind of bias current generating circuit, including positive temperature coefficient current generating unit 1, negative temperature
Coefficient current generation unit 2.Wherein described positive temperature coefficient current generating unit 1 and the phase of negative temperature parameter current generation unit 2
Connection.The positive temperature coefficient current generating unit 1 includes the first NMOS tube M1, the second NMOS tube M2, first resistor RB, the 3rd
PMOS M3, the 4th PMOS M4, the 5th PMOS M5；Wherein described 3rd PMOS M3, the 4th PMOS M4, the 5th PMOS
Pipe M5 source electrode is connected with supply voltage VDD respectively, wherein the drain and gate of the 3rd PMOS M3 is connected with each other, it is described
3rd PMOS M3 grid is connected with the 4th PMOS M4 grid, the grid and the 5th PMOS of the 4th PMOS M4
M5 grid is connected, and constitutes the breadth length ratio direct proportionality of the first current mirror, its size of current and pipe；And the described 5th
PMOS M5 drain electrode is connected with circuit output end；Wherein described first NMOS tube M1 drain electrode and the 3rd PMOS M3 drain electrode
Connection, the source electrode of the first NMOS tube M1 by first resistor RB with connect, the grid of the first NMOS tube M1 and the
Two NMOS tube M2 grid connection；The source electrode of the second NMOS tube M2 with ground connect, the drain electrode of the second NMOS tube M2 with
4th PMOS M4 drain electrode connects, wherein the drain and gate of the second NMOS tube M2 is produced with negative temperature parameter current respectively
Raw unit 2 connects；
The electric current wherein flowed through between the 3rd PMOS M3 source electrodes and drain electrode is electric current IPTAT1, flows through the 4th PMOS M4 sources
Electric current between pole and drain electrode is electric current IPTAT2, and it is positive temperature coefficient to flow through the electric current between the 5th PMOS M5 source electrode and drain electrode
Electric current IPTAT3；The drain electrode that wherein described electric current IPTAT2 flows into the second NMOS tube M2 produces control voltage, is output to negative temperature
Coefficient current generation unit 2 so that negative temperature parameter current generation unit 2 produces negative temperature parameter current ICTAT3, and described
Positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3 superpositions are output to electric current IOUT.
This bias current circuit is formed by stacking by two branch current circuits, and one of affluent-dividing is positive temperature coefficient electricity
Unit is flowed, another branch current is negative temperature parameter current unit, wherein by positive temperature coefficient current generating unit 1, using
In generation positive temperature coefficient electric current IPTAT3；In described positive temperature coefficient current generating unit 1, flowed by electric current IPTAT2
Enter the drain electrode to the second NMOS tube M2, produce control voltage and be output to negative temperature parameter current generation unit 2 so that negative temperature system
Number current generating unit 2 produces negative temperature parameter current ICTAT3, and the positive temperature coefficient electric current IPTAT3 and negative temperature system
The ICTAT3 superpositions of number electric current, are output to electric current IOUT so that influence of the change of temperature to output current IO UT diminishes；It is relative with
Existing technology, present invention eliminates transistor circuit, eliminates band-gap reference circuit, eliminates the amplifier circuit of complexity, can be big
Circuit area and power consumption are reduced greatly, while improving the overall performance of circuit.
Specifically, in the positive temperature coefficient current generating unit 1, in addition to second resistance R2, electric capacity C1, wherein described
The drain electrode of second resistance R2 one end and the second NMOS tube M2 is connected, and the second resistance R2 other end is connected with electric capacity C1, electric capacity
The C1 other ends and the first NMOS tube M1 grid are connected.In described positive temperature coefficient current generating unit 1, second resistance
R2, electric capacity C1 constitute a resistance-capacitance network, constitute feedback, play frequency compensation effect.
Specifically, wherein the negative temperature parameter current generation unit 2, including the 6th PMOS M6, the 7th PMOS M7,
8th PMOS M8, the 9th NMOS tube M9,3rd resistor R3；Wherein described 6th PMOS M6, the 7th PMOS M7, the 8th
PMOS M8 source electrode is connected with supply voltage VDD respectively, and the 6th PMOS M6 drain and gate is connected with each other, the 6th PMOS
Pipe M6 grid and the 7th PMOS M7 grid connect, the grid phase of the 7th PMOS M7 grid and the 8th PMOS M8
Even, the second current mirror is constituted, and the drain electrode of the 8th PMOS M8 is connected with circuit output end；Wherein described 7th PMOS
M7 drain electrode is connected by 3rd resistor R3 with ground, and the drain electrode of the 7th PMOS M7 connects with the first NMOS tube M1 grid
Connect；Wherein described 9th NMOS tube M9 drain electrode is connected with the 6th PMOS M6 drain electrode, the source electrode of the 9th NMOS tube M9
Connect with ground, the grid of the 9th NMOS tube M9 connects with the second NMOS tube M2 drain electrode.
The electric current wherein flowed through between the 6th PMOS M6 source electrode and drain electrode is electric current ICTAT1, flows through the 7th PMOS M7
Source electrode and drain electrode between electric current flow through the 8th PMOS M8 source for electric current ICTAT2, the negative temperature parameter current ICTAT3
Pole and drain electrode are simultaneously exported by circuit output end；Wherein electric current ICTAT2 is flowed into the control voltage feedback of 3rd resistor R3 generations
To the first NMOS tube M1 and the second NMOS tube M2 grid.Described control voltage, for stability contorting loop, reduces output
Electric current is influenced by temperature.
As shown in Figure 3-4, Fig. 3 waveform is positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3, Fig. 4
Waveform represents is superimposed current IOUT, be the sum of IPTAT3 and ICTAT3 current values.The temperature range of emulation is from -40
Spend+125 degree.In terms of simulation result, superimposed current IOUT is very small to+125 degree temperature ranges changes in -40 degree, it is maximum and
Minimum current fluctuation is only 0.6%.
Embodiment of above is only that the preferred embodiment of the present invention is described, and not the scope of the present invention is entered
Row is limited, on the premise of design spirit of the present invention is not departed from, technical side of this area ordinary skill technical staff to the present invention
In various modifications and improvement that case is made, the protection domain that claims of the present invention determination all should be fallen into.
Claims (3)
1. a kind of bias current generating circuit, it is characterised in that：Including positive temperature coefficient current generating unit, negative temperature coefficient electricity
Stream generation unit；Wherein described positive temperature coefficient current generating unit is connected with negative temperature parameter current generation unit；Wherein
The positive temperature coefficient current generating unit includes the first NMOS tube, the second NMOS tube, first resistor, the 3rd PMOS, the 4th
PMOS, the 5th PMOS；Wherein described 3rd PMOS, the 4th PMOS, the 5th PMOS source electrode respectively with power supply electricity
Pressure connection, wherein the drain and gate of the 3rd PMOS is connected with each other, the grid and the 4th PMOS of the 3rd PMOS
The grid of pipe is connected, and the grid of the 4th PMOS is connected with the grid of the 5th PMOS, and the leakage of the 5th PMOS
Pole is connected with circuit output end；The drain electrode of wherein described first NMOS tube is connected with the drain electrode of the 3rd PMOS, and described first
The source electrode of NMOS tube is connected by first resistor with ground, and the grid of first NMOS tube is connected with the grid of the second NMOS tube；
The source electrode of second NMOS tube connects with ground, and the drain electrode of second NMOS tube connects with the drain electrode of the 4th PMOS, wherein
The drain and gate of second NMOS tube connects with negative temperature parameter current generation unit respectively.
2. a kind of bias current generating circuit according to claim 1, it is characterised in that：The positive temperature coefficient electric current production
In raw unit, in addition to second resistance, electric capacity, wherein the drain electrode of one end of the second resistance and the second NMOS tube is connected, separately
One end is connected with electric capacity, and the grid of the electric capacity other end and the first NMOS tube is connected.
3. a kind of bias current generating circuit according to claim 1, it is characterised in that：The negative temperature parameter current production
Raw unit, including the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th NMOS tube, 3rd resistor；Wherein described 6th
PMOS, the 7th PMOS, the source electrode of the 8th PMOS are connected with supply voltage respectively, the drain and gate phase of the 6th PMOS
Connect, the grid of the 6th PMOS and the grid of the 7th PMOS connect, the grid of the 7th PMOS and the 8th PMOS
Grid is connected, and the drain electrode of the 8th PMOS is connected with circuit output end；The drain electrode of wherein described 7th PMOS passes through
3rd resistor connects with ground, and the drain electrode of the 7th PMOS is connected with the grid of the first NMOS tube；Wherein described 9th NMOS
The drain electrode of pipe is connected with the drain electrode of the 6th PMOS, and the source electrode of the 9th NMOS tube connects with ground, the 9th NMOS tube
Grid connects with the drain electrode of the second NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710693312.9A CN107300943B (en) | 2017-08-14 | 2017-08-14 | A kind of bias current generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710693312.9A CN107300943B (en) | 2017-08-14 | 2017-08-14 | A kind of bias current generating circuit |
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| CN107300943A true CN107300943A (en) | 2017-10-27 |
| CN107300943B CN107300943B (en) | 2018-12-11 |
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| CN201710693312.9A Active CN107300943B (en) | 2017-08-14 | 2017-08-14 | A kind of bias current generating circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111552343A (en) * | 2020-05-22 | 2020-08-18 | 聚洵半导体科技（上海）有限公司 | Low-voltage low-current bias current circuit |
| CN113566997A (en) * | 2021-07-26 | 2021-10-29 | 深圳青铜剑技术有限公司 | Temperature sensing circuit |
| CN114610108A (en) * | 2022-03-07 | 2022-06-10 | 上海类比半导体技术有限公司 | Bias current generating circuit |
| US11709517B2 (en) | 2020-03-12 | 2023-07-25 | Nxp Usa, Inc. | Bias current generator circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100201406A1 (en) * | 2009-02-10 | 2010-08-12 | Illegems Paul F | Temperature and Supply Independent CMOS Current Source |
| CN102346497A (en) * | 2011-05-27 | 2012-02-08 | 上海宏力半导体制造有限公司 | Reference current generating circuit |
| CN103699167A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Reference voltage circuit for radiofrequency identification |
| US20150194954A1 (en) * | 2014-01-07 | 2015-07-09 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Circuit for generating bias current |
-
2017
- 2017-08-14 CN CN201710693312.9A patent/CN107300943B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100201406A1 (en) * | 2009-02-10 | 2010-08-12 | Illegems Paul F | Temperature and Supply Independent CMOS Current Source |
| CN102346497A (en) * | 2011-05-27 | 2012-02-08 | 上海宏力半导体制造有限公司 | Reference current generating circuit |
| CN103699167A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Reference voltage circuit for radiofrequency identification |
| US20150194954A1 (en) * | 2014-01-07 | 2015-07-09 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Circuit for generating bias current |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11709517B2 (en) | 2020-03-12 | 2023-07-25 | Nxp Usa, Inc. | Bias current generator circuit |
| CN111552343A (en) * | 2020-05-22 | 2020-08-18 | 聚洵半导体科技（上海）有限公司 | Low-voltage low-current bias current circuit |
| CN113566997A (en) * | 2021-07-26 | 2021-10-29 | 深圳青铜剑技术有限公司 | Temperature sensing circuit |
| CN114610108A (en) * | 2022-03-07 | 2022-06-10 | 上海类比半导体技术有限公司 | Bias current generating circuit |
| CN114610108B (en) * | 2022-03-07 | 2024-02-23 | 上海类比半导体技术有限公司 | Bias current generating circuit |
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| Publication number | Publication date |
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| CN107300943B (en) | 2018-12-11 |
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