CN107300943B - A kind of bias current generating circuit - Google Patents
A kind of bias current generating circuit Download PDFInfo
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- CN107300943B CN107300943B CN201710693312.9A CN201710693312A CN107300943B CN 107300943 B CN107300943 B CN 107300943B CN 201710693312 A CN201710693312 A CN 201710693312A CN 107300943 B CN107300943 B CN 107300943B
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- pmos tube
- tube
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- drain electrode
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention discloses a kind of bias current generating circuits, this bias current generating circuit is formed by stacking by two branch current generation circuits, wherein first branch current generation circuit is positive temperature coefficient current generating circuit, another branch current generation circuit is negative temperature parameter current generation circuit.It in the positive temperature coefficient current generating unit, draws one and controls voltage to the negative temperature parameter current generation unit, for generating negative temperature parameter current, then by the positive temperature coefficient electric current and negative temperature parameter current superposition output.It is generated in unit in the negative temperature parameter current, draws one and control voltage to positive temperature coefficient current generating unit, be used for stability contorting loop, reduced output electric current and be influenced by temperature.Compared with prior art, present invention eliminates transistor circuits, eliminate band-gap reference circuit, eliminate complicated amplifier circuit, reduce circuit area and power consumption, while improving the overall performance of circuit.
Description
Technical field
The present invention relates to integrated circuit fields, espespecially a kind of bias current generating circuit.
Background technique
Common simple bias current generating circuit, i.e., as shown in Figure 1, by PMOS tube M3, PMOS tube M4, PMOS tube
M5 and NMOS tube M1, NMOS tube M2 and resistance RB composition.Thus the current generating circuit and supply voltage formed is unrelated, but
It is related with temperature.Change because the resistance value of resistance is the variation with temperature.The calculation formula of specific electric current is as follows:
Wherein, RBIt is resistance, μNIt is the mobility of electronics in NMOS tube channel, Cox is NMOS oxide layer unit area
Capacitance,It is the channel width and length ratio of NMOS tube M1,Be NMOS tube M2 channel width and length it
Than.Because of RBAnd μNAll it is influenced by temperature, so as can be seen from the above formula that, the output electric current I of circuitBIt is affected by temperature
It is very big.
Bias current generating circuit is typically necessary to realize to the insensitive of temperature change and carries out temperature benefit to circuit
It repays.Wherein general temperature-compensation method is to generate two-way bias current to be overlapped, one of them is positive temperature coefficient electric current,
The other is negative temperature parameter current.After the superposition of two-way electric current, the variation of total output current vs. temperature influences smaller.But one
As this circuit need two temperature coefficient generation circuits, circuit is complicated, and the power consumption of circuit and area etc. are all bigger.
Summary of the invention
To solve the above problems, the present invention provides a kind of bias current generating circuit, it is folded by two branch current units
Add, eliminates complicated amplifier circuit.Circuit area and power consumption are reduced, performance is improved.
The technical solution adopted by the present invention is that: a kind of bias current generating circuit, including positive temperature coefficient electric current generate list
Member, negative temperature parameter current generate unit；Wherein the positive temperature coefficient current generating unit and negative temperature parameter current generate
Unit is connected；Wherein the positive temperature coefficient current generating unit generates positive temperature coefficient electric current IPTAT3, the negative temperature
Coefficient current generates unit and generates negative temperature parameter current ICTAT3, and the positive temperature coefficient electric current IPTAT3 and negative temperature system
Number electric current ICTAT3 superposition is output to electric current IOUT.Wherein the positive temperature coefficient current generating unit includes the first NMOS tube
M1, the second NMOS tube M2, first resistor RB, third PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS tube M5；Wherein described
Three PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS tube M5 source electrode connect respectively with supply voltage VDD, wherein the third
The drain and gate of PMOS tube M3 is connected with each other, and the grid of the third PMOS tube M3 is connected with the grid of the 4th PMOS tube M4,
The grid of the 4th PMOS tube M4 is connected with the grid of the 5th PMOS tube M5, and drain electrode and the circuit of the 5th PMOS tube M5
Output end is connected；Wherein the drain electrode of the first NMOS tube M1 is connect with the drain electrode of third PMOS tube M3, first NMOS tube
The source electrode of M1 is connected by first resistor RB with ground, and the grid of the first NMOS tube M1 and the grid of the second NMOS tube M2 connect
It connects；The source electrode of the second NMOS tube M2 connects with ground, the drain electrode and the drain electrode of the 4th PMOS tube M4 of the second NMOS tube M2
Connect, connects wherein the drain and gate of the second NMOS tube M2 generates unit with negative temperature parameter current respectively.
Specifically, wherein flowing through the electric current between third PMOS tube M3 source electrode and drain electrode is electric current IPTAT1, the positive temperature
Coefficient current IPTAT3 flows through the 5th PMOS tube M5 source electrode and drain electrode and is exported by circuit output end；The electric current IPTAT2 stream
Enter to the second NMOS tube M2 and generate control voltage, and negative temperature parameter current is output to by the drain electrode of the second NMOS tube M2 and is generated
Unit, and the control voltage as negative temperature parameter current generation circuit, so that negative temperature parameter current generates unit generation and bears
Temperature coefficient current ICTAT3.
It specifically, further include second resistance R2, capacitor C1 in the positive temperature coefficient current generating unit, wherein described
One end of second resistance R2 is connected with the drain electrode of the second NMOS tube M2, and the other end is connected with capacitor C1, the capacitor C1 other end and
The grid of one NMOS tube M1 is connected.
Specifically, the negative temperature parameter current generates unit, including the 6th PMOS tube M6, the 7th PMOS tube M7, the 8th
PMOS tube M8, the 9th NMOS tube M9,3rd resistor R3；Wherein the 6th PMOS tube M6, the 7th PMOS tube M7, the 8th PMOS tube
The source electrode of M8 is connect with supply voltage VDD respectively, and the drain and gate of the 6th PMOS tube M6 is connected with each other, the 6th PMOS tube M6's
The grid of grid and the 7th PMOS tube M7 connect, and the grid of the 7th PMOS tube M7 is connected with the grid of the 8th PMOS tube M8, and institute
The drain electrode for stating the 8th PMOS tube M8 is connect with circuit output end；Wherein the drain electrode of the 7th PMOS tube M7 passes through 3rd resistor R3
Connect with ground, the drain electrode of the 7th PMOS tube M7 is connect with the grid of the first NMOS tube M1；Wherein the 9th NMOS tube M9
Drain electrode connect with the drain electrode of the 6th PMOS tube M6, the source electrode of the 9th NMOS tube M9 connects with ground, the 9th NMOS tube
The grid of M9 connects with the drain electrode of the second NMOS tube M2.
Specifically, wherein flowing through the electric current between the 7th PMOS tube M7 source electrode and drain electrode is electric current ICTAT2, the negative temperature
Coefficient current ICTAT3 flows through the 8th PMOS tube M8 source electrode and drain electrode and is exported by circuit output end；Wherein electric current ICTAT2 flows
Enter the grid to the control Voltage Feedback that 3rd resistor R3 is generated to the first NMOS tube M1 and the second NMOS tube M2, as positive temperature
The control voltage of coefficient current generation circuit, so that positive temperature coefficient current generating unit generates positive temperature coefficient electric current
IPTAT3。
The beneficial effects of the present invention are: this bias current circuit is formed by stacking by two branch current circuits, wherein one
A affluent-dividing is positive temperature coefficient current unit, another branch current is negative temperature parameter current unit, and by circuit output
Superimposed current IOUT, so that influence of the variation of temperature to output superimposed current IOUT becomes smaller；Relative to existing technology, the present invention is saved
Transistor circuit has been removed, band-gap reference circuit is eliminated, complicated amplifier circuit has been eliminated, circuit area can be greatly reduced
And power consumption, while improving the overall performance of circuit.
Detailed description of the invention
Fig. 1 is prior art bias current generating circuit structural schematic diagram；
Fig. 2 is electrical block diagram in the present invention；
Fig. 3 is that positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3 vary with temperature signal in the present invention
Figure；
Fig. 4 is that superimposed current IOUT varies with temperature schematic diagram in the present invention；
Drawing reference numeral explanation: 1- positive temperature coefficient current generating unit；2- negative temperature parameter current generates unit；
Specific embodiment
It please refers to shown in Fig. 2, a kind of bias current generating circuit, including positive temperature coefficient current generating unit 1, negative temperature
Coefficient current generates unit 2.Wherein the positive temperature coefficient current generating unit 1 and negative temperature parameter current generate 2 phase of unit
Connection.The positive temperature coefficient current generating unit 1 includes the first NMOS tube M1, the second NMOS tube M2, first resistor RB, third
PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS tube M5；Wherein the third PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS
The source electrode of pipe M5 is connect with supply voltage VDD respectively, wherein the drain and gate of the third PMOS tube M3 is connected with each other, it is described
The grid of third PMOS tube M3 is connected with the grid of the 4th PMOS tube M4, the grid and the 5th PMOS tube of the 4th PMOS tube M4
The grid of M5 is connected, and constitutes the first current mirror, the breadth length ratio direct proportionality of size of current and pipe；And the described 5th
The drain electrode of PMOS tube M5 is connected with circuit output end；The wherein drain electrode of the drain electrode of the first NMOS tube M1 and third PMOS tube M3
Connection, the source electrode of the first NMOS tube M1 by first resistor RB with connect, the grid of the first NMOS tube M1 and the
The grid of two NMOS tube M2 connects；The source electrode of the second NMOS tube M2 with ground connect, the drain electrode of the second NMOS tube M2 with
The drain electrode of 4th PMOS tube M4 connects, wherein the drain and gate of the second NMOS tube M2 is produced with negative temperature parameter current respectively
Raw unit 2 connects；
The electric current wherein flowed through between third PMOS tube M3 source electrode and drain electrode is electric current IPTAT1, flows through the 4th source PMOS tube M4
Electric current between pole and drain electrode is electric current IPTAT2, and flowing through the electric current between the source electrode and drain electrode of the 5th PMOS tube M5 is positive temperature coefficient
Electric current IPTAT3；The drain electrode that wherein the electric current IPTAT2 flows into the second NMOS tube M2 generates control voltage, is output to negative temperature
Coefficient current generates unit 2, so that negative temperature parameter current generates unit 2 and generates negative temperature parameter current ICTAT3, and described
Positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3 superposition is output to electric current IOUT.
This bias current circuit is formed by stacking by two branch current circuits, and one of affluent-dividing is positive temperature coefficient electricity
Unit is flowed, another branch current is negative temperature parameter current unit, wherein using by positive temperature coefficient current generating unit 1
In generation positive temperature coefficient electric current IPTAT3；In the positive temperature coefficient current generating unit 1, flowed by electric current IPTAT2
Enter the drain electrode to the second NMOS tube M2, generates control voltage output to negative temperature parameter current and generate unit 2, so that negative temperature system
Number current generating unit 2 generates negative temperature parameter current ICTAT3, and the positive temperature coefficient electric current IPTAT3 and negative temperature system
Number electric current ICTAT3 superposition, is output to electric current IOUT, so that influence of the variation of temperature to output current IO UT becomes smaller；It is opposite with
Existing technology, present invention eliminates transistor circuits, eliminate band-gap reference circuit, eliminate complicated amplifier circuit, can be big
Circuit area and power consumption are reduced greatly, while improving the overall performance of circuit.
It specifically, further include second resistance R2, capacitor C1 in the positive temperature coefficient current generating unit 1, wherein described
One end of second resistance R2 is connected with the drain electrode of the second NMOS tube M2, and the other end of second resistance R2 is connected with capacitor C1, capacitor
The grid of the C1 other end and the first NMOS tube M1 are connected.In the positive temperature coefficient current generating unit 1, second resistance
R2, capacitor C1 constitute a resistance-capacitance network, constitute feedback, play the role of frequency compensation.
Specifically, wherein the negative temperature parameter current generate unit 2, including the 6th PMOS tube M6, the 7th PMOS tube M7,
8th PMOS tube M8, the 9th NMOS tube M9,3rd resistor R3；Wherein the 6th PMOS tube M6, the 7th PMOS tube M7, the 8th
The source electrode of PMOS tube M8 is connect with supply voltage VDD respectively, and the drain and gate of the 6th PMOS tube M6 is connected with each other, the 6th PMOS
The grid of the grid of pipe M6 and the 7th PMOS tube M7 connect, the grid phase of the grid and the 8th PMOS tube M8 of the 7th PMOS tube M7
Even, the second current mirror is constituted, and the drain electrode of the 8th PMOS tube M8 is connect with circuit output end；Wherein the 7th PMOS tube
The drain electrode of M7 is connected by 3rd resistor R3 with ground, and the drain electrode of the 7th PMOS tube M7 connects with the grid of the first NMOS tube M1
It connects；Wherein the drain electrode of the 9th NMOS tube M9 is connect with the drain electrode of the 6th PMOS tube M6, the source electrode of the 9th NMOS tube M9
Connect with ground, the grid of the 9th NMOS tube M9 connects with the drain electrode of the second NMOS tube M2.
The electric current wherein flowed through between the source electrode and drain electrode of the 6th PMOS tube M6 is electric current ICTAT1, flows through the 7th PMOS tube M7
Source electrode and drain electrode between electric current be electric current ICTAT2, the negative temperature parameter current ICTAT3 flows through the source of the 8th PMOS tube M8
Pole and drain electrode are simultaneously exported by circuit output end；Wherein electric current ICTAT2 is flowed into the control Voltage Feedback of 3rd resistor R3 generation
To the grid of the first NMOS tube M1 and the second NMOS tube M2.The control voltage is used for stability contorting loop, reduces output
Electric current is influenced by temperature.
As shown in Figure 3-4, the waveform of Fig. 3 is positive temperature coefficient electric current IPTAT3 and negative temperature parameter current ICTAT3, Fig. 4
Waveform indicate be superimposed current IOUT, be the sum of IPTAT3 and ICTAT3 current value.The temperature range of emulation is from -40
Spend+125 degree.Seen from the simulation results, superimposed current IOUT is very small to+125 degree temperature ranges variations in -40 degree, it is maximum and
The smallest current fluctuation is only 0.6%.
Embodiment of above be only preferred embodiments of the present invention will be described, not to the scope of the present invention into
Row limits, and without departing from the spirit of the design of the present invention, this field ordinary engineering and technical personnel is to technical side of the invention
The various changes and improvements that case is made, should fall within the scope of protection determined by the claims of the present invention.
Claims (2)
1. a kind of bias current generating circuit, it is characterised in that: including positive temperature coefficient current generating unit, negative temperature coefficient electricity
Stream generation unit；Wherein the positive temperature coefficient current generating unit generates unit with negative temperature parameter current and is connected；Wherein
The positive temperature coefficient current generating unit includes the first NMOS tube, the second NMOS tube, first resistor, third PMOS tube, the 4th
PMOS tube, the 5th PMOS tube；Wherein the third PMOS tube, the 4th PMOS tube, the source electrode of the 5th PMOS tube are electric with power supply respectively
Pressure connection, wherein the drain and gate of the third PMOS tube is connected with each other, the grid and the 4th PMOS of the third PMOS tube
The grid of pipe is connected, and the grid of the 4th PMOS tube is connected with the grid of the 5th PMOS tube, and the leakage of the 5th PMOS tube
Pole is connected with circuit output end；Wherein the drain electrode of first NMOS tube is connect with the drain electrode of third PMOS tube, and described first
The source electrode of NMOS tube is connected by first resistor with ground, and the grid of first NMOS tube is connect with the grid of the second NMOS tube；
The source electrode of second NMOS tube connects with ground, and the drain electrode of second NMOS tube connects with the drain electrode of the 4th PMOS tube, wherein
The drain and gate of second NMOS tube generates unit with negative temperature parameter current respectively and connects；The negative temperature parameter current
Generate unit, including the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th NMOS tube, 3rd resistor；Wherein described
Six PMOS tube, the 7th PMOS tube, the 8th PMOS tube source electrode connect respectively with supply voltage, the drain and gate of the 6th PMOS tube
It is connected with each other, the grid of the 6th PMOS tube and the grid of the 7th PMOS tube connect, the grid and the 8th PMOS tube of the 7th PMOS tube
Grid be connected, and the drain electrode of the 8th PMOS tube is connect with circuit output end；Wherein the drain electrode of the 7th PMOS tube is logical
It crosses 3rd resistor to connect with ground, the drain electrode of the 7th PMOS tube is connect with the grid of the first NMOS tube；Wherein the described 9th
The drain electrode of NMOS tube is connect with the drain electrode of the 6th PMOS tube, and the source electrode of the 9th NMOS tube connects with ground, the 9th NMOS
The grid of pipe connects with the drain electrode of the second NMOS tube, and the grid of second NMOS tube is connect with the drain electrode of the 7th PMOS tube.
2. a kind of bias current generating circuit according to claim 1, it is characterised in that: the positive temperature coefficient electric current produces
It further include second resistance, capacitor, wherein one end of the second resistance is connected with the drain electrode of the second NMOS tube, separately in raw unit
One end is connected with one end of capacitor, and the grid of the capacitor other end and the first NMOS tube is connected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710693312.9A CN107300943B (en) | 2017-08-14 | 2017-08-14 | A kind of bias current generating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710693312.9A CN107300943B (en) | 2017-08-14 | 2017-08-14 | A kind of bias current generating circuit |
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| CN107300943A CN107300943A (en) | 2017-10-27 |
| CN107300943B true CN107300943B (en) | 2018-12-11 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113391667A (en) | 2020-03-12 | 2021-09-14 | 恩智浦美国有限公司 | Bias current generating circuit |
| CN111552343B (en) * | 2020-05-22 | 2022-08-16 | 聚洵半导体科技（上海）有限公司 | Low-voltage low-current bias current circuit |
| CN113566997A (en) * | 2021-07-26 | 2021-10-29 | 深圳青铜剑技术有限公司 | Temperature sensing circuit |
| CN114610108B (en) * | 2022-03-07 | 2024-02-23 | 上海类比半导体技术有限公司 | Bias current generating circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346497A (en) * | 2011-05-27 | 2012-02-08 | 上海宏力半导体制造有限公司 | Reference current generating circuit |
| CN103699167A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Reference voltage circuit for radiofrequency identification |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7944271B2 (en) * | 2009-02-10 | 2011-05-17 | Standard Microsystems Corporation | Temperature and supply independent CMOS current source |
| CN103729004B (en) * | 2014-01-07 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | A kind of bias current generating circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346497A (en) * | 2011-05-27 | 2012-02-08 | 上海宏力半导体制造有限公司 | Reference current generating circuit |
| CN103699167A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Reference voltage circuit for radiofrequency identification |
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