CN208061059U - A kind of reference voltage generating circuit of super low-power consumption - Google Patents
A kind of reference voltage generating circuit of super low-power consumption Download PDFInfo
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- CN208061059U CN208061059U CN201820420924.0U CN201820420924U CN208061059U CN 208061059 U CN208061059 U CN 208061059U CN 201820420924 U CN201820420924 U CN 201820420924U CN 208061059 U CN208061059 U CN 208061059U
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Abstract
The utility model discloses a kind of reference voltage generating circuits of super low-power consumption, including the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9.The utility model designs circuit based on the thermal voltage of metal-oxide-semiconductor threshold voltage and positive temperature coefficient with negative temperature coefficient, a kind of reference voltage generating circuit of super low-power consumption is provided, circuit structure is all made of MOS transistor, do not use triode and resistance, comply with standard CMOS technology, it is designed compared to band-gap reference, reduce volume and power consumption, simultaneously, the utility model carries out tc compensation and reference voltage output under the premise of saving current mirror branch all the way, only need three road current mirror branches that can build reference voltage generating circuit, it further reduced the power consumption of reference voltage generating circuit.
Description
Technical field
The utility model is related to reference voltage sources, more particularly to a kind of reference voltage generating circuit of super low-power consumption.
Background technology
Reference voltage source is a kind of circuit common in integrated circuit, for generating one not with the base of mains voltage variations
Quasi- voltage, this voltage can be used for providing accurately reference voltage, reference voltage source for other modules in IC system
There is consequence, the performance of precision, speed all strong influence circuit systems in IC system；Traditional base
Quasi- voltage generation circuit is designed using band-gap reference, in the designs, utilizes base stage-emitter electricity of bipolar transistor
Pressing element has negative temperature characteristic, and the difference for the base stage-emitter voltage being operated under different current densities then has positive temperature special
Property, the two mutually compensates for that temperature independent output voltage can be obtained, but but there is the higher problems of power consumption for band-gap reference.
In order to reduce the power consumption of reference voltage source, disclose that " one kind is super application No. is the patent of CN201611221434.X
Low-power-consumptioreference reference voltage source circuit system ", the patent based on negative temperature coefficient threshold voltage and with positive temperature coefficient
Thermal voltage design circuit, circuit structure is all made of MOS transistor, is not used triode and resistance, is also subtracted significantly
Small chip area designs compared to band-gap reference, also reduces power consumption；But the patent needs four road current mirror branch in total
Road, wherein three road current mirror branches are for building PTAT current generation circuit, the 4th road current mirror branch is for building load electricity
Road generates reference voltage and compensation temperature coefficient, but program current mirror branch is excessive, still remains that power consumption is larger to ask
Topic.
Utility model content
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of reference voltage generation of super low-power consumption
Circuit carries out tc compensation and reference voltage output under the premise of saving current mirror branch all the way, significantly reduces
The power consumption of reference voltage generating circuit.
The purpose of this utility model is achieved through the following technical solutions：A kind of reference voltage generation of super low-power consumption
Circuit, including the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th MOS
Pipe M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9；
The source level of the 7th metal-oxide-semiconductor M7 connects supply voltage, the leakage of the drain of the 7th metal-oxide-semiconductor M7 and the first metal-oxide-semiconductor M1
Grade connection, the grid of the 7th metal-oxide-semiconductor M7 are connect with the grid of the 8th metal-oxide-semiconductor M8；The source level of the 8th metal-oxide-semiconductor M8 connects
Supply voltage, the drain of the 8th metal-oxide-semiconductor M8 are connect with the drain of the second metal-oxide-semiconductor M2, and the grid of the 8th metal-oxide-semiconductor M8 is also with
The drain of eight metal-oxide-semiconductor M8 connects；The source level of the 9th metal-oxide-semiconductor M9 connects supply voltage, the drain and third of the 9th metal-oxide-semiconductor M9
The drain of metal-oxide-semiconductor M3 connects, and the grid of the 9th metal-oxide-semiconductor M9 is connect with the drain of the 8th metal-oxide-semiconductor M8；
The grid of the first metal-oxide-semiconductor M1 is connect with the grid of the second metal-oxide-semiconductor M2, and the grid of the first metal-oxide-semiconductor M1 is also
It is connect with the drain of the first metal-oxide-semiconductor M1, the source level of the first metal-oxide-semiconductor M1 is connect with the drain of the 6th metal-oxide-semiconductor M6, the first MOS
The drain of pipe M1 is also connected with the output end of reference voltage generating circuit；The source level of the second metal-oxide-semiconductor M2 and the 4th metal-oxide-semiconductor M4's
Drain connects；The source level of the third metal-oxide-semiconductor M3 is grounded, and the grid of third metal-oxide-semiconductor M3 is connect with the grid of the 4th metal-oxide-semiconductor M4,
The grid of the third metal-oxide-semiconductor M3 is also connect with the drain of third metal-oxide-semiconductor M3；The source level and the 5th metal-oxide-semiconductor of 4th metal-oxide-semiconductor
Drain connection；The source level of the 5th metal-oxide-semiconductor M5 is grounded, and the grid of the 5th metal-oxide-semiconductor M5 connects with the grid of third metal-oxide-semiconductor M3
It connects, the source level ground connection of the 6th metal-oxide-semiconductor M6, the grid of the 6th metal-oxide-semiconductor is connect with the grid of third metal-oxide-semiconductor M3.
The first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th
Metal-oxide-semiconductor M6 is NMOS tube.
7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 is PMOS tube.
The first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 the 6th
Metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 include substrate；Wherein, the 7th metal-oxide-semiconductor M7, the 8th
The substrate connection supply voltage of metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9；First metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3,
The Substrate ground of four metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6.
The utility model has the beneficial effects that：The utility model carries out temperature under the premise of saving current mirror branch all the way
Spend compensating coefficient and reference voltage output, it is only necessary to which three road current mirror branches can build reference voltage generating circuit, significantly drop
The low power consumption of reference voltage generating circuit.
Description of the drawings
Fig. 1 is the circuit diagram of the utility model.
Specific implementation mode
The technical solution of the utility model, but the scope of protection of the utility model are described in further detail below in conjunction with the accompanying drawings
It is not limited to as described below.
As shown in Figure 1, a kind of reference voltage generating circuit of super low-power consumption, including the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2,
Third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th
Metal-oxide-semiconductor M9；
The source level of the 7th metal-oxide-semiconductor M7 connects supply voltage, the leakage of the drain of the 7th metal-oxide-semiconductor M7 and the first metal-oxide-semiconductor M1
Grade connection, the grid of the 7th metal-oxide-semiconductor M7 are connect with the grid of the 8th metal-oxide-semiconductor M8；The source level of the 8th metal-oxide-semiconductor M8 connects
Supply voltage, the drain of the 8th metal-oxide-semiconductor M8 are connect with the drain of the second metal-oxide-semiconductor M2, and the grid of the 8th metal-oxide-semiconductor M8 is also with
The drain of eight metal-oxide-semiconductor M8 connects；The source level of the 9th metal-oxide-semiconductor M9 connects supply voltage, the drain and third of the 9th metal-oxide-semiconductor M9
The drain of metal-oxide-semiconductor M3 connects, and the grid of the 9th metal-oxide-semiconductor M9 is connect with the drain of the 8th metal-oxide-semiconductor M8；
The grid of the first metal-oxide-semiconductor M1 is connect with the grid of the second metal-oxide-semiconductor M2, and the grid of the first metal-oxide-semiconductor M1 is also
It is connect with the drain of the first metal-oxide-semiconductor M1, the source level of the first metal-oxide-semiconductor M1 is connect with the drain of the 6th metal-oxide-semiconductor M6, the first MOS
The drain of pipe M1 is also connected with the output end of reference voltage generating circuit；The source level of the second metal-oxide-semiconductor M2 and the 4th metal-oxide-semiconductor M4's
Drain connects；The source level of the third metal-oxide-semiconductor M3 is grounded, and the grid of third metal-oxide-semiconductor M3 is connect with the grid of the 4th metal-oxide-semiconductor M4,
The grid of the third metal-oxide-semiconductor M3 is also connect with the drain of third metal-oxide-semiconductor M3；The source level and the 5th metal-oxide-semiconductor of 4th metal-oxide-semiconductor
Drain connection；The source level of the 5th metal-oxide-semiconductor M5 is grounded, and the grid of the 5th metal-oxide-semiconductor M5 connects with the grid of third metal-oxide-semiconductor M3
It connects, the source level ground connection of the 6th metal-oxide-semiconductor M6, the grid of the 6th metal-oxide-semiconductor is connect with the grid of third metal-oxide-semiconductor M3.
The first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th
Metal-oxide-semiconductor M6 is NMOS tube.
7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 is PMOS tube.
The first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 the 6th
Metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 include substrate；Wherein, the 7th metal-oxide-semiconductor M7, the 8th
The substrate connection supply voltage of metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9；First metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3,
The Substrate ground of four metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6.
In embodiments herein, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9 and third metal-oxide-semiconductor M3 works
Make to be operated in sub-threshold region in saturation region, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are operated in linearly
Area
In the present invention, the 8th metal-oxide-semiconductor M8 with constitute current mirror, shape with the 7th metal-oxide-semiconductor M7 and the 9th metal-oxide-semiconductor respectively
Tri- road current mirror branches of Cheng Liao；
The electric current of first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is respectively：
Wherein,Indicate that thermal voltage, K1 are the breadth length ratio of the first metal-oxide-semiconductor M1, K2 indicates the width of the second metal-oxide-semiconductor M2
Long ratio, I indicate characteristic current,μnFor mobility, CoxFor the gate oxide capacitance of unit area；
VGS1 is the gate source voltage of the first metal-oxide-semiconductor M1, and VTH1 is the threshold voltage of the first metal-oxide-semiconductor M1；VGS2 is the grid of the second metal-oxide-semiconductor M2
Source voltage, VTH2 are the threshold voltage of the second metal-oxide-semiconductor M2, and m is the constant more than 1, indicates thermodynamic voltage.
The calculation formula of I1, I2 are deformed to obtain：
Because the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 constitute current mirror, electric currents of the first metal-oxide-semiconductor M1 in the 7th metal-oxide-semiconductor M7
Mirror branch road, the second metal-oxide-semiconductor M2 on the current mirror branch road of the 8th metal-oxide-semiconductor M8, therefore：
Wherein, K7, K8 indicate the breadth length ratio of M7 and M8 respectively；
4th metal-oxide-semiconductor M4 is equivalent to resistance, for generating bias current, the drain-source voltage VDS of the 4th metal-oxide-semiconductorM4For：
In formula, the δ VTH i.e. difference of the threshold voltage of the first NMOS tube MN1 and the second NMOS tube MN2, in formula,
It is directly proportional to thermodynamic temperature T, therefore VDSM4For positive temperature coefficient.
Third metal-oxide-semiconductor M3 is mainly used for adjusting the grid voltage of the 4th metal-oxide-semiconductor M4；5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 are impartial
It imitates in resistance, the negative temperature coefficient for compensating VTH1；
The electric current of third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 5th metal-oxide-semiconductor M5 is respectively：
I3 is the electric current for flowing through third metal-oxide-semiconductor M3, and I4 is the electric current for flowing through the 4th metal-oxide-semiconductor M4, and I5 is to flow through the 5th metal-oxide-semiconductor
The electric current of M5；
M8 and M9 forms current mirror, so having
Bringing the expression formula of I3 and I5 into above formula can obtain：
It enables
It enables
By circuit it is found that I4=I5,
The expression formula above formula of I4 and I5, which is substituted into formula, to be obtained
It enables(Vx-Vth)=Va is then：
Again because having acquired Va=AVDS aboveM5
The breadth length ratio of 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor is proportional so that the drain-source of the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor
Voltage is consistent, i.e. VDSM5=VDSM6, further according to acquiring above
VDSM5=VDSM6=A ' * VDSM4；
VDSM5Indicate the drain-source voltage of the 5th metal-oxide-semiconductor；VDSM6For the drain-source voltage of the 6th metal-oxide-semiconductor M6；
In the utility model, the voltage VREF of reference voltage generating circuit output is：
By above formula it can be found that by the way that suitable parameters are arranged, you can obtain corresponding A, B values, and then generate sufficiently large
Positive temperature voltage, offset with the negative temperature coefficient of VTH1, obtain the reference voltage of zero warm coefficient.
To sum up, the utility model carries out tc compensation and benchmark electricity under the premise of saving current mirror branch all the way
Pressure output, it is only necessary to which three road current mirror branches can build reference voltage generating circuit, significantly reduce reference voltage and generate electricity
The power consumption on road.
Claims (4)
1. a kind of reference voltage generating circuit of super low-power consumption, it is characterised in that：Including the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2,
Third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th
Metal-oxide-semiconductor M9；
The source level of the 7th metal-oxide-semiconductor M7 connects supply voltage, and the drain of the 7th metal-oxide-semiconductor M7 and the drain of the first metal-oxide-semiconductor M1 connect
It connects, the grid of the 7th metal-oxide-semiconductor M7 is connect with the grid of the 8th metal-oxide-semiconductor M8；The source level of the 8th metal-oxide-semiconductor M8 connects power supply
Voltage, the drain of the 8th metal-oxide-semiconductor M8 are connect with the drain of the second metal-oxide-semiconductor M2, and the grid of the 8th metal-oxide-semiconductor M8 is also with the 8th
The drain of metal-oxide-semiconductor M8 connects；The source level of the 9th metal-oxide-semiconductor M9 connects supply voltage, the drain and third of the 9th metal-oxide-semiconductor M9
The drain of metal-oxide-semiconductor M3 connects, and the grid of the 9th metal-oxide-semiconductor M9 is connect with the drain of the 8th metal-oxide-semiconductor M8；
The grid of the first metal-oxide-semiconductor M1 is connect with the grid of the second metal-oxide-semiconductor M2, and the grid of the first metal-oxide-semiconductor M1 is also with
The drain of one metal-oxide-semiconductor M1 connects, and the source level of the first metal-oxide-semiconductor M1 is connect with the drain of the 6th metal-oxide-semiconductor M6, the first metal-oxide-semiconductor M1
Drain be also connected with the output end of reference voltage generating circuit；The drain of the source level and the 4th metal-oxide-semiconductor M4 of the second metal-oxide-semiconductor M2
Connection；The source level of the third metal-oxide-semiconductor M3 is grounded, and the grid of third metal-oxide-semiconductor M3 is connect with the grid of the 4th metal-oxide-semiconductor M4, described
The grid of third metal-oxide-semiconductor M3 is also connect with the drain of third metal-oxide-semiconductor M3；The leakage of the source level and the 5th metal-oxide-semiconductor of 4th metal-oxide-semiconductor
Grade connection；The source level of the 5th metal-oxide-semiconductor M5 is grounded, and the grid of the 5th metal-oxide-semiconductor M5 is connect with the grid of third metal-oxide-semiconductor M3, institute
The source level ground connection of the 6th metal-oxide-semiconductor M6 is stated, the grid of the 6th metal-oxide-semiconductor is connect with the grid of third metal-oxide-semiconductor M3.
2. a kind of reference voltage generating circuit of super low-power consumption according to claim 1, it is characterised in that：Described first
Metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 are NMOS
Pipe.
3. a kind of reference voltage generating circuit of super low-power consumption according to claim 1, it is characterised in that：Described the 7th
Metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 are PMOS tube.
4. a kind of reference voltage generating circuit of super low-power consumption according to claim 1, it is characterised in that：Described first
Metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6 of the 5th metal-oxide-semiconductor M5, the 7th metal-oxide-semiconductor
M7, the 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9 include substrate；Wherein, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor
The substrate of M9 connects supply voltage；First metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th MOS
The Substrate ground of pipe M5 and the 6th metal-oxide-semiconductor M6.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108181968A (en) * | 2018-03-27 | 2018-06-19 | 芯蓉光科（成都）信息技术有限公司 | A kind of reference voltage generating circuit of super low-power consumption |
| CN109901656A (en) * | 2019-04-10 | 2019-06-18 | 电子科技大学 | A kind of full metal-oxide-semiconductor band-gap reference circuit of low-power consumption and the converter based on it |
| CN115576383A (en) * | 2022-09-20 | 2023-01-06 | 北京聚思芯半导体技术有限公司 | Band-gap reference circuit and band-gap reference chip |
-
2018
- 2018-03-27 CN CN201820420924.0U patent/CN208061059U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108181968A (en) * | 2018-03-27 | 2018-06-19 | 芯蓉光科（成都）信息技术有限公司 | A kind of reference voltage generating circuit of super low-power consumption |
| CN108181968B (en) * | 2018-03-27 | 2024-03-19 | 芯蓉光科（成都）信息技术有限公司 | Reference voltage generating circuit |
| CN109901656A (en) * | 2019-04-10 | 2019-06-18 | 电子科技大学 | A kind of full metal-oxide-semiconductor band-gap reference circuit of low-power consumption and the converter based on it |
| CN115576383A (en) * | 2022-09-20 | 2023-01-06 | 北京聚思芯半导体技术有限公司 | Band-gap reference circuit and band-gap reference chip |
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