CN109725675A - Cascode current bias structure and current biasing circuit and SUB-BGR - Google Patents
Cascode current bias structure and current biasing circuit and SUB-BGR Download PDFInfo
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Abstract
The invention discloses a kind of cascode current bias structures, it include: that the first MOS and the 2nd MOS first end are connected as the current offset construction first end, first MOS second end connects the 4th MOS first end, 2nd MOS is as the current offset structure second end, 3rd MOS second end, 6th MOS second end, 3rd MOS third end, 4th MOS third end, which is connected, is used as the current offset structure third end, 4th MOS second end, 5th MOS second end, 5th MOS third end is connected with the 6th MOS third end, 5th MOS first end, 7th MOS first end, 7th MOS third end and the 8th MOS third end are as the 4th end of current offset structure, 6th MOS first end connects the 8th MOS second end, 8th MOS first end connects the 9th M OS second end, the 7th MOS first end are connected as the 5th end of current offset structure with the 9th MOS first end, and the 9th MOS is as third end the 5th end of current offset structure.The invention also discloses a kind of current biasing circuit and SUB-BGR.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of cascode current bias structure of CMOS technology.
The invention further relates to a kind of current biasing circuits with the cascode current bias structure.And it is a kind of with described
The SUB-BGR of cascode current bias structure and current biasing circuit.
Background technique
In many circuits, the bias current and current mirror used is all it is implicitly assumed that available " ideal " base
Quasi- electric current (IREF), the reference current not with technique, the variation of power supply and temperature and change.In traditional current offset, it is
Obtain solution insensitive to VDD, circuit must bias (Self Bias) by oneself, as shown in Fig. 2, PMOS3
I is replicated with PMOS4OUTSo that it is determined that IREF, IREF, which is booted, in essence is biased to IOUT, if ignoring channel length
Mudulation effect (Channel Length Modulation effect), then IOUT=KIREF.Because of each diode fashion connection
Device all have a driven with current sources, so comparatively, IREF and IOUT are unrelated with VDD.
In order to uniquely determine current value, another constraint is added in circuit, as shown in Fig. 2, because PMOS device has phase
Same size, although requiring IOUT=IREF, resistance RS reduces the electric current of the PMOS3 of its connection.V can be write outGS4=
VGS3+IDRS, and M1~M4 works in saturation region, then has:
Ignore bulk effect, VTH1=VTH2；
Such as formula 3) shown in, electric current IOUTFunction that is unrelated with power vd D but still being flow-route and temperature.Wherein, μ-carrier
Mobility.
Although traditional IBIAS circuit has been accomplished unrelated with power supply substantially, the precision of reference current nevertheless suffers from other
The influence of external factor, such as temperature and technique.The purpose of the present invention is increase on the basis of Cascode current mirror IBIAS
Tc compensation, to reduce technique, voltage, influence of the extraneous factors such as temperature to reference current precision as far as possible.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of cascode current bias structures.
A kind of and power supply and temperature are realized by temperature-compensating mode another technical problem to be solved by the present invention is that providing
All unrelated current biasing circuit.
The invention solves another technical problem be to provide and a kind of there is above-mentioned cascode current bias structure and electricity
Flow the SUB-BGR of biasing circuit.
SUB=sub threshold subthreshold value, SUB-BGR refer in particular to the super low-power consumption band-gap reference designed in sub-threshold region
Source.
In order to solve the above technical problems, the present invention provides cascode current bias structure 20, comprising: the first MOS~the
Nine MOS M1~M9；
First MOS M1 and the 2nd MOS M2 first end, which are connected, is used as current offset construction first end A, the first MOS M1
Second end connects the 4th MOS M4 first end, the 2nd MOS M2 second end, the 3rd MOS M3 first end, the first MOS M1 third end
It is connected with the 2nd MOS M2 third end as current offset structure second end B, the 3rd MOS M3 second end, the 6th MOS M6 the
Two ends, the 3rd MOS M3 third end, the 4th M4 third end MOS, which are connected, is used as current offset structure third end C, the 4th MOS
M4 second end, the 5th MOS M5 second end, the 5th M5 third end MOS are connected with the 6th MOSM6 third end, the 5th MOS M5
One end, the 7th MOS M7 first end, the 7th M7 third end MOS and the 8th M8 third end MOS are as the current offset structure
Four end D, the 6th MOS M6 first end connect the 8th MOS M8 second end, and the 8th MOS M8 first end connects the 9th MOS M9 second
End, the 7th MOS M7 first end are connected as the 5th end E of the current offset structure, the 9th MOS M9 with the 9th MOS M9 first end
As third end the 5th end F of the current offset structure.
It is further improved the cascode current bias structure, the first MOS M1~M8 of MOS~the 8th is constituted
Cascade cascade electricity structure.
It is further improved the cascode current bias structure, the first MOS M1 and the 2nd MOS M2 size phase
Together, the 3rd MOS M3 and the 4th MOS M4 size are identical, and the 5th MOS M5 and the 6th MOS M6 size are identical, described
7th MOS M7 size is Z times of size of the 8th MOS M8, and the MOS size is the model of wide and long the ratio Z, Z of the conducting channel of MOS
The integer for 1~1000 is enclosed, which is calculated with the electric current desired value of actual design.
It is further improved the cascode current bias structure, the first MOS~the 4th MOS M1~M4 is
NMOS, the 5th MOS~the 9th MOS M5~M9 is PMOS.
It is further improved the cascode current bias structure, the first MOS M1~M9 first end of MOS~the 9th is
Source electrode, the first MOS M1~M9 second end of MOS~the 9th are drain electrodes, and the first MOS M1~M9 third of MOS~the 9th end is grid.
The present invention provides a kind of current offset electricity with cascode current bias structure 20 described in above-mentioned any one
Road, comprising: start-up circuit 10, cascode current bias structure 20, positive temperature coefficient voltage generation circuit 30 and bias generate
Circuit 40；
The 10 first end G of start-up circuit, 20 first end A of cascode current bias structure, positive temperature coefficient voltage produce
Raw 30 first end K of circuit connects ground GND, the 10 second end H of start-up circuit, cascade with bias generating circuit first end P
20 third end C of current offset structure is connected with 40 third end R of bias generating circuit, and the 10 third end I of start-up circuit, common source are total
The 4th end D of gate current bias structure 20 connects benchmark current terminal after being connected with the 4th end N of positive temperature coefficient voltage generation circuit 30
IREF, the 20 second end B of cascode current bias structure are connected with 40 second end Q of bias generating circuit, and the common source is total
The 5th end F of gate current bias structure 20 is connected with 30 second end L of positive temperature coefficient voltage generation circuit, the positive temperature coefficient electricity
Pressure 30 third end M of generation circuit is connected with the 4th end S of bias generating circuit 40, the 4th end J of start-up circuit 10, cascade
The 5th end E of current offset structure 20, positive temperature coefficient voltage generation circuit 30 the 5th end O and the 5th end T of bias generating circuit 40
Connect power supply power vd D.
It is further improved the current biasing circuit, the positive temperature coefficient voltage generation circuit 30 includes the tenth MOS
~the ten six MOS M10~M16；
15th MOS M15 and the 16th MOS M16 first end, which are connected, is used as the positive temperature coefficient voltage generation circuit 30
First end K, the 15th MOS M15 second end connect the 13rd MOS M13 first end, the 16th MOS M16 second end, the 15th
MOS M15 third end, the 16th M16 third end MOS are connected with the 14th MOS M14 first end, the 13rd MOS M13 second
End, the 11st MOS M11 second end are connected as the positive temperature coefficient voltage generation circuit 30 with the 11st MOS M11 third end
Second end L, the 14th MOS M14 second end, the 13rd MOS M13 third end, the 14th M14 third end MOS and the 12nd
MOS M12 second end is connected, the 11st MOS M11 first end, the tenth MOS M10 second end and the 12nd MOS M12 first end
It is connected, the 12nd M12 third end MOS is as 30 third end M of the positive temperature coefficient voltage generation circuit, the tenth MOS M10 third
End is used as the 4th end N of the positive temperature coefficient voltage generation circuit 30, and the tenth MOS M10 first end is as the positive temperature coefficient voltage
The 5th end T of generation circuit 30.
It is further improved the current biasing circuit, the tenth MOS M10~M16 of MOS~the 16th work is in Asia
Threshold zone.
It is further improved the current biasing circuit, the 11st MOS M11 and the 12nd MOS M12 dimension scale
For 10:1, the MOS size is the wide and long ratio of the conducting channel of MOS.
It is further improved the current biasing circuit, the tenth MOS~the 12nd MOS M10~M12 is PMOS, the
13~the 16th MOS M13~M16 is NMOS.
It is further improved the current biasing circuit, the tenth MOS~the 16th MOS M10~M16 first end is
Source electrode, the 16th MOS M10~M16 second end of the tenth MOS are to drain, the tenth MOS~the 16th MOS M10~
M16 third end is grid.
It is further improved the current biasing circuit, the bias generating circuit 40 includes the 17th MOS~the 19th
MOSM17~M19；
19th MOS M19 first end connects as 40 first end P of the bias generating circuit, the 19th MOS M19 second end
Hit the 18th MOS M18 first end, the 19th M19 third end MOS is as 40 second end Q of the bias generating circuit, and the 18th
MOS M18 second end, the 17th MOS M17 second end and the 17th MOS M17 third end are connected as the bias generating circuit
40 the 4th end S, the 18th M18 third end MOS is as 40 third end R of the bias generating circuit, the 17th MOS M17 first end
As the 5th end T of the bias generating circuit 40.
It is further improved the current biasing circuit, the 40 second end Q mirror image cascade electricity of bias generating circuit
Flow 20 second end B electric current of bias structure, 40 third end R mirror image cascode current bias structure 20 of the bias generating circuit the
Three end C electric currents.
It is further improved the current biasing circuit, the 17th MOS M17 and the 19th MOS M19 size phase
Together, the MOS size is the wide and long ratio of the conducting channel of MOS.
Be further improved the current biasing circuit, the 17th MOS M17 is PMOS, the 18th MOS M18 and
19 MOS are NMOS.
It is further improved the current biasing circuit, the 17th MOS~the 19th MOS M17~M19 first end
It is source electrode, the 17th MOS~the 19th MOS M17~M19 second end is drain electrode, the 17th MOS~the 19th
MOSM17~M19 third end is grid.
It is further improved the current biasing circuit, the start-up circuit 10 includes the 20th MOS M20, the 21st
MOS M21 and resistance Rp；
The resistance Rp first end connects the 20th MOS as 10 first end G of the start-up circuit, the resistance Rp second end
M20 second end and the 21st MOS M21 third end, the 21st MOS M21 second end is as 10 second end of start-up circuit
H, the 20th M20 third end MOS is as 10 third end I of the start-up circuit, the 20th MOS M20 first end and the 21st MOS
M21 first end, which is connected, is used as the 4th end J of the start-up circuit 10.
It is further improved the current biasing circuit, the 20th MOS M20 and the 21st MOS M21 is
PMOS；
It is further improved the current biasing circuit, the 20th MOS M20 and the 21st MOS M21 first end
It is source electrode, the 20th MOS M20 and the 21st MOS M21 second end are drain electrode, the 20th MOS M20 and second
11 MOS M21 third ends are grids.
The present invention provides a kind of SUB-BGR with current biasing circuit described in above-mentioned any one, comprising: current offset
Circuit I BIAS, positive temperature coefficient are voltage generator PTAT, the 22nd MOS M22 and the first triode TR；
The current biasing circuit IBIAS and positive temperature coefficient be voltage generator PTAT be connected to supply voltage VDD and
Between ground GND, the reference current end IREF connection positive temperature coefficient of the current biasing circuit IBIAS is voltage generator PTAT
Input terminal VIN, the 22nd MOS M22 first end connect supply voltage VDD, the 22nd MOS M22 second end
It connects the first triode TR first end and positive temperature coefficient is voltage generator PTAT input terminal VIN, the first triode TR second
End and third end are grounded GND, and the M22 third end the 22nd MOS connects the reference current end of current biasing circuit IBIAS
IREF, the positive temperature coefficient are that voltage generator PTAT output end VREF is exported as the SUB-BGR.
It is further improved the SUB-BGR, the 22nd MOS M22 is PMOS.
It is further improved the SUB-BGR, the 22nd MOS M22 first end is source electrode, the described 22nd
MOS M22 second end is drain electrode, and the 22nd MOS M22 third end is grid.
It is further improved the SUB-BGR, first triode is PNP triode.
It is further improved the SUB-BGR, the first triode first end is emitter, first triode the
Two ends are collectors, and the first triode first end is base stage.
It is further improved the SUB-BGR, the positive temperature coefficient is that voltage generator PTAT includes the 23rd MOS
~the two ten eight MOS M23-M28 and current source CS；
The 23rd MOS M23 first end and the 24th MOS M24 first end are through current source CS ground connection GND, institute
State the 23rd MOS M23 second end, the 25th MOS M25 second end, the 25th M25 third end MOS and the 26th
The M26 third end MOS is connected, input terminal VIN of the M23 third end the 23rd MOS as the SUB-BGR, and described second
14 MOS M24 second ends, the 24th M24 third end MOS are connected as the SUB- with the 26th MOS M26 second end
The output end VOUT of BGR, the 25th MOS M25 first end, the 27th MOSM27 second end, the 27th MOS
M27 third end is connected with the 28th MOS M28 third end, the 26th MOS M26 first end and the 28th MOS
M28 second end is connected, the 27th MOS M27 first end and the 28th MOS M28 first end phase downlink connection power supply electricity
Press VDD.
It is further improved the SUB-BGR, the 23rd MOS M23 and the 24th MOS M24 is NMOS, institute
Stating the 25th MOS of MOS~the 28th is PMOS.
It is further improved the SUB-BGR, the 23rd MOS~the 28th MOS M23-M28 first end is
Source electrode, the 23rd MOS~the 28th MOS M23-M28 second end are drain electrode, the 23rd MOS~the 20th
Eight MOS M23-M28 third ends are grids.
The present invention increases M3~M6MOSFET on the basis of conventional current biases (M1, M2, M7, M8, M9), makes M1~M8
Cascade Cascade structure is constituted, so that flowing through M3, the electric current of M4 is equal to each other, therefore the source potential of M3, M4 are equal.Together
When the circuit include a voltage offset electric circuit (M17~M19), positive temperature coefficient voltage generator (M10~M16, PTAT
Voltage generator) and a start-up circuit for preventing circuit from entering zero current degenerate state.Wherein PTAT voltage part
All MOSFETs work in sub-threshold region, PTAT voltage generator as shown in Figure 4 is the differential amplification of a buffer connection
Device, when its tail current is sufficiently small, by taking the differential pair tube of W/L=4/4 as an example, when wake flow is less than 0.02uA, so that differential pair tube
M23, M24 work in sub-threshold region.Its drain current is and differential input voltage holds exponential relationship, at the same with thermal voltage (VT)
Inverse ratio also holds exponential relationship.The thermal voltage holds direct ratio with temperature again.
Input offset voltage (the V of the bufferoffset), Voffset=VOUT-VIN
=VGS, M2-VGS, M1 4)
VOUT is equal to Differential Input VIN ', VOFFSET=VIN-VIN ' simultaneously.Can be by the sub-threshold region of metal-oxide-semiconductor
VGS-Vth-(VGS'-Vth')；By the sub-threshold region characteristic of metal-oxide-semiconductor can calculate VOFFSET be a positive temperature coefficient voltage.
As shown in Fig. 2, MOS resistance M17 and M9 work are in strong inversion and deep triode region, gate length and width phase
Together, and they are by identical current offset.Due to the presence of PTAT unit input offset, so that the grid source electricity of M17 and M9
Pressure is different.This offset voltage with positive temperature coefficient is passed on MOS resistance M9 by buffer, compensates for current source (M1
~M9) temperature coefficient itself.The M17 and M9 of identical size make their threshold voltage close simultaneously, so that M17 and M9 is produced
Raw current differential is insensitive to technique.
Size of traditional bootstrapping eccentrically arranged type IBIAS output electric current under TT_1.2V_25 degree is 4.012uA.Maximum/most
Low current generates under SS_1.08V_125 degree, FF_1.08V_-40 degree respectively, and size is respectively 5.53uA, 2.77uA；Bootstrapping
The electric current output Variation of eccentrically arranged type IBIAS is -31%~37%.
And the corner simulation result of the Cascode IBIAS with temperature-compensating is as shown in table 1, wherein IR5nx is to be somebody's turn to do
Variation under output PIN, the Worst case of IBIAS circuit is -11%~14.3%.This technology solution is big
Width improves precision of the IBIAS output electric current at corner and different external environments (temperature, voltage).Band as shown in table 1 below
Tc compensation Cascode IBIAS Corner simulation result.Use scope of the present invention is wider, if setting applied to SUB-BGR
In meter, saturation current I can be provided for bipolar device (BJT)S, make bipolar device work in diode region, to generate one
Base emitter voltage VBE with negative temperature coefficient.IBIAS may be that the offer of PTAT voltage generator is accurate all the way simultaneously
Bias current, to improve the precision of BGR.
Table 1
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is a kind of reference current circuit structural schematic diagram that generation is unrelated with power supply.
Fig. 2 is current biasing circuit structural schematic diagram of the present invention.
Fig. 3 is SUB-BGR structural schematic diagram of the present invention.
Fig. 4 is PTAT structural schematic diagram of the present invention.
Description of symbols
NMOS1, NMOS2 are different NMOS
PMOS3~PMOS7 is different PMOS
The first MOS M1~M28 of MOS~the 28th
Rp, Rs indicate different resistance
CS is current source
TR is the first triode
It indicates not
Same MOS size.
Specific embodiment
The present invention provides cascode current bias structure 20, comprising: the first MOS M1~M9 of MOS~the 9th；Described
MOS M1~the M4 of one MOS~the 4th is NMOS, and the 5th MOS~the 9th MOS M5~M9 is PMOS.First MOS~the 9th
MOSM1~M9 first end is source electrode, and the first MOS M1~M9 second end of MOS~the 9th is drain electrode, the first MOS M1 of MOS~the 9th
~M9 third end is grid.
First MOS M1 and the 2nd MOS M2 first end, which are connected, is used as current offset construction first end A, the first MOS M1
Second end connects the 4th MOS M4 first end, the 2nd MOS M2 second end, the 3rd MOS M3 first end, the first MOS M1 third end
It is connected with the 2nd MOS M2 third end as current offset structure second end B, the 3rd MOS M3 second end, the 6th MOS M6 the
Two ends, the 3rd MOS M3 third end, the 4th M4 third end MOS, which are connected, is used as current offset structure third end C, the 4th MOS
M4 second end, the 5th MOS M5 second end, the 5th M5 third end MOS are connected with the 6th MOSM6 third end, the 5th MOS M5
One end, the 7th MOS M7 first end, the 7th M7 third end MOS and the 8th M8 third end MOS are as the current offset structure
Four end D, the 6th MOS M6 first end connect the 8th MOS M8 second end, and the 8th MOS M8 first end connects the 9th MOS M9 second
End, the 7th MOS M7 first end are connected as the 5th end E of the current offset structure, the 9th MOS M9 with the 9th MOS M9 first end
As third end the 5th end F of the current offset structure.
Wherein, the first MOS M1~M8 of MOS~the 8th constitutes cascade cascade electricity structure, the first MOS M1
Identical with the 2nd MOS M2 size, the 3rd MOS M3 and the 4th MOS M4 size are identical, the 5th MOS M5 and the 6th
MOS M6 size is identical, and the 7th MOS M7 size is Z times of size of the 8th MOS M8, and the MOS size is the conductive ditch of MOS
The integer that road width and the range of long ratio Z, Z are 1~1000, calculates the Z value with the electric current desired value of actual design.
As shown in Fig. 2, the present invention provides a kind of current biasing circuit with the cascode current bias structure 20,
It include: start-up circuit 10, cascode current bias structure 20, positive temperature coefficient voltage generation circuit 30 and bias generating circuit
40；
The 10 first end G of start-up circuit, 20 first end A of cascode current bias structure, positive temperature coefficient voltage produce
Raw 30 first end K of circuit connects ground GND, the 10 second end H of start-up circuit, cascade with bias generating circuit first end P
20 third end C of current offset structure is connected with 40 third end R of bias generating circuit, and the 10 third end I of start-up circuit, common source are total
The 4th end D of gate current bias structure 20 connects benchmark current terminal after being connected with the 4th end N of positive temperature coefficient voltage generation circuit 30
IREF, the 20 second end B of cascode current bias structure are connected with 40 second end Q of bias generating circuit, and the common source is total
The 5th end F of gate current bias structure 20 is connected with 30 second end L of positive temperature coefficient voltage generation circuit, the positive temperature coefficient electricity
Pressure 30 third end M of generation circuit is connected with the 4th end S of bias generating circuit 40, the 4th end J of start-up circuit 10, cascade
The 5th end E of current offset structure 20, positive temperature coefficient voltage generation circuit 30 the 5th end O and the 5th end T of bias generating circuit 40
Connect power supply power vd D.
30 1 embodiment of positive temperature coefficient voltage generation circuit includes the tenth MOS M10~M16 of MOS~the 16th；
Tenth MOS~the 12nd MOS M10~M12 is PMOS, and the 13rd~the 16th MOS M13~M16 is NMOS, described
MOS M10~M16 the first end of ten MOS~the 16th is source electrode, and the 16th MOS M10~M16 second end of the tenth MOS is leakage
Pole, the tenth MOS~the 16th MOS M10~M16 third end is grid.
15th MOS M15 and the 16th MOS M16 first end, which are connected, is used as the positive temperature coefficient voltage generation circuit 30
First end K, the 15th MOS M15 second end connect the 13rd MOS M13 first end, the 16th MOS M16 second end, the 15th
MOS M15 third end, the 16th M16 third end MOS are connected with the 14th MOS M14 first end, the 13rd MOS M13 second
End, the 11st MOS M11 second end are connected as the positive temperature coefficient voltage generation circuit 30 with the 11st MOS M11 third end
Second end L, the 14th MOS M14 second end, the 13rd MOS M13 third end, the 14th M14 third end MOS and the 12nd
MOS M12 second end is connected, the 11st MOS M11 first end, the tenth MOS M10 second end and the 12nd MOS M12 first end
It is connected, the 12nd M12 third end MOS is as 30 third end M of the positive temperature coefficient voltage generation circuit, the tenth MOS M10 third
End is used as the 4th end N of the positive temperature coefficient voltage generation circuit 30, and the tenth MOS M10 first end is as the positive temperature coefficient voltage
The 5th end T of generation circuit 30.
The tenth MOS M10~M16 of MOS~the 16th work is in sub-threshold region, the 11st MOS M11 and the tenth
Two MOS M12 dimension scales are 10:1, and the MOS size is the wide and long ratio of the conducting channel of MOS.
Wherein, 40 1 embodiment of bias generating circuit, including the 17th MOS M17~M19 of MOS~the 19th；Institute
Stating the 17th MOS M17 is PMOS, and the 18th MOS M18 and 19 MOS are NMOS, the 17th MOS~the 19th MOS
M17~M19 first end is source electrode, and the 17th MOS~the 19th MOS M17~M19 second end is to drain, the described 17th
MOS M17~M19 the third of MOS~the 19th end is grid.
19th MOS M19 first end connects as 40 first end P of the bias generating circuit, the 19th MOS M19 second end
Hit the 18th MOS M18 first end, the 19th M19 third end MOS is as 40 second end Q of the bias generating circuit, and the 18th
MOS M18 second end, the 17th MOS M17 second end and the 17th MOS M17 third end are connected as the bias generating circuit
40 the 4th end S, the 18th M18 third end MOS is as 40 third end R of the bias generating circuit, the 17th MOS M17 first end
As the 5th end T of the bias generating circuit 40.
40 second end Q mirror image cascode current bias structure of bias generating circuit, the 20 second end B electric current, it is described inclined
Press 40 third end R mirror image cascode current bias structure of generation circuit, 20 third end C electric current.
The 17th MOS M17 and the 19th MOS M19 size are identical, and the MOS size is that the conducting channel of MOS is wide
And long ratio.
Wherein, 10 1 embodiment of start-up circuit includes the 20th MOS M20, the 21st MOS M21 and resistance Rp；
The 20th MOS M20 and the 21st MOS M21 is PMOS, the 20th MOS M20 and the 21st MOSM21
One end is source electrode, and the 20th MOS M20 and the 21st MOS M21 second end are drain electrodes, the 20th MOS M20 and
21st MOS M21 third end is grid.
The resistance Rp first end connects the 20th MOS as 10 first end G of the start-up circuit, the resistance Rp second end
M20 second end and the 21st MOS M21 third end, the 21st MOS M21 second end is as 10 second end of start-up circuit
H, the 20th M20 third end MOS is as 10 third end I of the start-up circuit, the 20th MOS M20 first end and the 21st MOS
M21 first end, which is connected, is used as the 4th end J of the start-up circuit 10.
As shown in figure 3, the present invention provides a kind of SUB-BGR with above-mentioned current biasing circuit, comprising: current offset electricity
Road IBIAS, positive temperature coefficient are voltage generator PTAT, the 22nd MOS M22 and the first triode TR；Described 22nd
MOS M22 is PMOS, and the 22nd MOS M22 first end is source electrode, and the 22nd MOS M22 second end is leakage
Pole, the 22nd MOS M22 third end is grid, and first triode is PNP triode, first triode
One end is emitter, and the first triode second end is collector, and the first triode first end is base stage.
Bias current sources generate the current offset unrelated with power supply and temperature, this current offset makes the PN of PNP triode
Junction diode forward voltage (base emitter voltage) band negative temperature coefficient and VBE have negative temperature coefficient.Positive temperature simultaneously
Coefficient generation circuit (PTAT) generates positive temperature coefficient voltage under identical current offset, special using " empty short " of difference amplifier
Property, VBE superposition VPTAT is generated into the VREF voltage without temperature coefficient.
The current biasing circuit IBIAS and positive temperature coefficient be voltage generator PTAT be connected to supply voltage VDD and
Between ground GND, the reference current end IREF connection positive temperature coefficient of the current biasing circuit IBIAS is voltage generator PTAT
Input terminal VIN, the 22nd MOS M22 first end connect supply voltage VDD, the 22nd MOS M22 second end
It connects the first triode TR first end and positive temperature coefficient is voltage generator PTAT input terminal VIN, the first triode TR second
End and third end are grounded GND, and the M22 third end the 22nd MOS connects the reference current end of current biasing circuit IBIAS
IREF, the positive temperature coefficient are that voltage generator PTAT output end VREF is exported as the SUB-BGR.
As shown in figure 4, it includes the 23rd MOS~the second that the positive temperature coefficient, which is mono- embodiment of voltage generator PTAT,
18 MOS M23-M28 and current source CS；The 23rd MOS M23 and the 24th MOS M24 is NMOS, described second
The MOS of 15 MOS~the 28th is PMOS, and the 23rd MOS~the 28th MOS M23-M28 first end is source electrode,
23rd MOS~the 28th MOS M23-M28 second end is drain electrode, the 23rd MOS~the 28th MOS
M23-M28 third end is grid.
The 23rd MOS M23 first end and the 24th MOS M24 first end are through current source CS ground connection GND, institute
State the 23rd MOS M23 second end, the 25th MOS M25 second end, the 25th M25 third end MOS and the 26th
The M26 third end MOS is connected, input terminal VIN of the M23 third end the 23rd MOS as the SUB-BGR, and described second
14 MOS M24 second ends, the 24th M24 third end MOS are connected as the SUB- with the 26th MOS M26 second end
The output end VOUT of BGR, the 25th MOS M25 first end, the 27th MOSM27 second end, the 27th MOS
M27 third end is connected with the 28th MOS M28 third end, the 26th MOS M26 first end and the 28th MOS
M28 second end is connected, the 27th MOS M27 first end and the 28th MOS M28 first end phase downlink connection power supply electricity
Press VDD.
Above by specific embodiment and embodiment, invention is explained in detail, but these are not composition pair
Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (27)
1. a kind of cascode current bias structure characterized by comprising the first MOS of MOS~the 9th (M1~M9)；
First MOS (M1) is connected as the current offset construction first end (A), the first MOS (M1) with the 2nd MOS (M2) first end
Second end connects the 4th MOS (M4) first end, the 2nd MOS (M2) second end, the 3rd MOS (M3) first end, the first MOS (M1) the
Three ends are connected as the current offset structure second end (B), the 3rd MOS (M3) second end, the 6th with the 2nd MOS (M2) third end
MOS (M6) second end, the 3rd MOS (M3) third end, the 4th (M4) the third end MOS, which are connected, is used as the current offset structure third end
(C), the 4th MOS (M4) second end, the 5th MOS (M5) second end, the 5th (M5) the third end MOS and the 6th MOS (M6) third end
It is connected, the 5th MOS (M5) first end, the 7th MOS (M7) first end, the 7th (M7) the third end MOS and the 8th MOS (M8) third end
As the 4th end (D) of current offset structure, the 6th MOS (M6) first end connects the 8th MOS (M8) second end, the 8th MOS
(M8) first end connects the 9th MOS (M9) second end, and the 7th MOS (M7) first end is connected conduct with the 9th MOS (M9) first end
The 5th end (E) of current offset structure, the 9th MOS (M9) are used as third end the 5th end (F) of current offset structure.
2. cascode current bias structure as described in claim 1, it is characterised in that: the first MOS~the 8th MOS
(M1~M8) constitutes cascade cascade electricity structure.
3. cascode current bias structure as described in claim 1, it is characterised in that: the first MOS (M1) and second
MOS (M2) size is identical, and the 3rd MOS (M3) is identical with the 4th MOS (M4) size, the 5th MOS (M5) and the 6th MOS
(M6) size is identical, and the 7th MOS (M7) size is the 8th Z times of size of MOS (M8), and the MOS size is the conductive ditch of MOS
Road width and long ratio are Z, the integer that the range of Z is 1~1000.
4. cascode current bias structure as described in claim 1, it is characterised in that: the first MOS~the 4th MOS
(M1~M4) is NMOS, and the 5th MOS of MOS~the 9th (M5~M9) is PMOS.
5. cascode current bias structure as claimed in claim 4, it is characterised in that: the first MOS of MOS~the 9th (M1~
M9) first end is source electrode, and the first MOS~the 9th MOS (M1~M9) second end is drain electrode, the first MOS of MOS~the 9th (M1~M9)
Third end is grid.
6. one kind has the current biasing circuit of cascode current bias structure (20) described in claim 1-5 any one,
It is characterised by comprising: start-up circuit (10), cascode current bias structure (20), positive temperature coefficient voltage generation circuit
(30) and bias generating circuit (40)；
Start-up circuit (10) first end (G), cascode current bias structure (20) first end (A), positive temperature coefficient electricity
With pressing generation circuit (30) first end (K) and bias generating circuit first end (P) connection (GND), the start-up circuit (10) the
Two ends (H), cascode current bias structure (20) third end (C) are connected with bias generating circuit (40) third end (R), described
Start-up circuit (10) third end (I), the 4th end (D) of cascode current bias structure (20) and positive temperature coefficient voltage generate electricity
The 4th end (N) of road (30) connects benchmark current terminal (IREF) after being connected, cascode current bias structure (20) second end
(B) it is connected with bias generating circuit (40) second end (Q), the 5th end (F) of cascode current bias structure (20) and just
Temperature system voltage generation circuit (30) second end (L) is connected, positive temperature coefficient voltage generation circuit (30) the third end (M)
It is connected with the 4th end (S) of bias generating circuit (40), the 4th end (J) of start-up circuit (10), cascode current bias junctions
The 5th end (E) of structure (20), the 5th end (O) of positive temperature coefficient voltage generation circuit (30) and the 5th end of bias generating circuit (40)
(T) power supply power supply (VDD) is connected.
7. current biasing circuit as claimed in claim 6, it is characterised in that: the positive temperature coefficient voltage generation circuit (30)
Including the tenth MOS of MOS~the 16th (M10~M16)；
15th MOS (M15) is connected as the positive temperature coefficient voltage generation circuit (30) with the 16th MOS (M16) first end
First end (K), the 15th MOS (M15) second end the 13rd MOS (M13) first end of connection, the 16th MOS (M16) second end,
15th MOS (M15) third end, the 16th (M16) the third end MOS are connected with the 14th MOS (M14) first end, the 13rd MOS
(M13) second end, the 11st MOS (M11) second end and the 11st MOS (M11) third end are connected as positive temperature coefficient electricity
Press generation circuit (30) second end (L), the 14th MOS (M14) second end, the 13rd MOS (M13) third end, the 14th MOS
(M14) third end is connected with the 12nd MOS (M12) second end, the 11st MOS (M11) first end, the tenth MOS (M10) second end
It is connected with the 12nd MOS (M12) first end, the 12nd (M12) the third end MOS is as the positive temperature coefficient voltage generation circuit
(30) third end (M), the tenth (M10) the third end MOS is as the 4th end (N) of positive temperature coefficient voltage generation circuit (30), and
Ten MOS (M10) first end is as the 5th end (T) of positive temperature coefficient voltage generation circuit (30).
8. current biasing circuit as claimed in claim 7, it is characterised in that: the tenth MOS~the 16th MOS (M10~
M16) work is in sub-threshold region.
9. current biasing circuit as claimed in claim 7, it is characterised in that: the 11st MOS (M11) and the 12nd MOS
(M12) dimension scale is 10:1, and the MOS size is the wide and long ratio of the conducting channel of MOS.
10. current biasing circuit as claimed in claim 7, it is characterised in that: the tenth MOS~the 12nd MOS (M10~
It M12) is PMOS, the 13rd~the 16th MOS (M13~M16) is NMOS.
11. current biasing circuit as claimed in claim 10, it is characterised in that: the tenth MOS~the 16th MOS (M10~
M16) first end is source electrode, and the tenth MOS the 16th MOS (M10~M16) second end is drain electrode, the tenth MOS~the tenth
Six MOS (M10~M16) third end is grid.
12. current biasing circuit as claimed in claim 6, it is characterised in that: the bias generating circuit (40) includes the tenth
The MOS of seven MOS~the 19th (M17~M19)；
19th MOS (M19) first end is as bias generating circuit (40) first end (P), the 19th MOS (M19) second end
Double hit the 18th MOS (M18) first end, the 19th (M19) the third end MOS as bias generating circuit (40) second end (Q),
18th MOS (M18) second end, the 17th MOS (M17) second end are connected as the bias with the 17th MOS (M17) third end
The 4th end (S) of generation circuit (40), the 18th (M18) the third end MOS is as bias generating circuit (40) the third end (R), and
17 MOS (M17) first end is as the 5th end (T) of bias generating circuit (40).
13. current biasing circuit as claimed in claim 12, it is characterised in that: bias generating circuit (40) second end
(Q) mirror image cascode current bias structure (20) second end (B) electric current, bias generating circuit (40) third end (R) mirror
As cascode current bias structure (20) third end (C) electric current.
14. current biasing circuit as claimed in claim 12, it is characterised in that: the 17th MOS (M17) and the 19th
MOS (M19) size is identical, and the MOS size is the wide and long ratio of the conducting channel of MOS.
15. current biasing circuit as claimed in claim 11, it is characterised in that: the 17th MOS (M17) is PMOS, the
18 MOS (M18) He Shijiu MOS is NMOS.
16. current biasing circuit as claimed in claim 15, it is characterised in that: the 17th MOS~the 19th MOS (M17
~M19) first end is source electrode, the 17th MOS~the 19th MOS (M17~M19) second end is drain electrode, the described 17th
MOS (M17~M19) third of MOS~the 19th end is grid.
17. current biasing circuit as claimed in claim 6, it is characterised in that: the start-up circuit (10) includes the 20th MOS
(M20), the 21st MOS (M21) and resistance (Rp)；
Resistance (Rp) first end is as start-up circuit (10) first end (G), resistance (Rp) the second end connection second
Ten MOS (M20) second end and the 21st MOS (M21) third end, the 21st MOS (M21) second end is as the start-up circuit
(10) second end (H), the 20th (M20) the third end MOS is as start-up circuit (10) the third end (I), the 20th MOS (M20)
First end is connected as the 4th end (J) of start-up circuit (10) with the 21st MOS (M21) first end.
18. current biasing circuit as claimed in claim 17, it is characterised in that: the 20th MOS (M20) and the 21st
MOS (M21) is PMOS.
19. current biasing circuit as claimed in claim 18, it is characterised in that: the 20th MOS (M20) and the 21st
MOS (M21) first end is source electrode, and the 20th MOS (M20) and the 21st MOS (M21) second end are drain electrodes, described the
20 MOS (M20) and the 21st MOS (M21) third end are grids.
20. a kind of SUB-BGR with current biasing circuit described in claim 7-19 any one characterized by comprising
Current biasing circuit (IBIAS), positive temperature coefficient are voltage generator (PTAT), the 22nd MOS (M22) and the first triode
(TR)；
The current biasing circuit (IBIAS) and positive temperature coefficient are that voltage generator (PTAT) is connected to supply voltage (VDD)
Between ground (GND), reference current end (IREF) the connection positive temperature coefficient of the current biasing circuit (IBIAS) is that voltage produces
Raw device (PTAT) input terminal (VIN), the 22nd MOS (M22) first end connect supply voltage (VDD), and the described 20th
Two MOS (M22) second end connects the first triode (TR) first end and positive temperature coefficient is voltage generator (PTAT) input terminal
(VIN), the first triode (TR) second end and third end ground connection (GND), (M22) the third end the 22nd MOS connection electricity
The reference current end (IREF) of biasing circuit (IBIAS) is flowed, the positive temperature coefficient is voltage generator (PTAT) output end
(VREF) it is exported as the SUB-BGR.
21. SUB-BGR as claimed in claim 20, it is characterised in that: the 22nd MOS (M22) is PMOS.
22. SUB-BGR as claimed in claim 21, it is characterised in that: the 22nd MOS (M22) first end is source electrode,
22nd MOS (M22) second end is drain electrode, and the 22nd MOS (M22) the third end is grid.
23. SUB-BGR as claimed in claim 20, it is characterised in that: first triode is PNP triode.
24. SUB-BGR as claimed in claim 23, it is characterised in that: the first triode first end is emitter, described
First triode second end is collector, and the first triode first end is base stage.
25. SUB-BGR as claimed in claim 20, it is characterised in that: the positive temperature coefficient is voltage generator (PTAT)
Including the 23rd MOS of MOS~the 28th (M23-M28) and current source (CS)；
23rd MOS (M23) first end and the 24th MOS (M24) first end are grounded (GND) through current source (CS),
23rd MOS (M23) second end, the 25th MOS (M25) second end, the 25th (M25) the third end MOS and
(M26) the third end 26 MOS is connected, input terminal of (M23) the third end the 23rd MOS as the SUB-BGR
(VIN), the 24th MOS (M24) second end, the 24th (M24) the third end MOS and the 26th MOS (M26) second
The connected output end (VOUT) as the SUB-BGR in end, the 25th MOS (M25) first end, the 27th MOS (M27)
Second end, the 27th (M27) the third end MOS are connected with the 28th MOS (M28) third end, the 26th MOS
(M26) first end is connected with the 28th MOS (M28) second end, the 27th MOS (M27) first end and the 28th
MOS (M28) first end phase downlink connection supply voltage (VDD).
26. SUB-BGR as claimed in claim 25, it is characterised in that: the 23rd MOS (M23) and the 24th MOS
It (M24) is NMOS, the 25th MOS~the 28th MOS is PMOS.
27. SUB-BGR as claimed in claim 26, it is characterised in that: the 23rd MOS~the 28th MOS (M23-
M28) first end is source electrode, and the 23rd MOS~the 28th MOS (M23-M28) second end is to drain, the described 20th
MOS (M23-M28) third of three MOS~the 28th end is grid.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113114117A (en) * | 2021-04-08 | 2021-07-13 | 唐太平 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
| CN113342120A (en) * | 2021-06-25 | 2021-09-03 | 上海料聚微电子有限公司 | PTAT voltage generating circuit and band-gap reference circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110193544A1 (en) * | 2010-02-11 | 2011-08-11 | Iacob Radu H | Circuits and methods of producing a reference current or voltage |
| CN103399609A (en) * | 2013-08-15 | 2013-11-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Nanowatt magnitude band-gap reference voltage source with low power consumption and high stability |
| CN103809647A (en) * | 2014-03-13 | 2014-05-21 | 苏州芯动科技有限公司 | Reference voltage source with high power supply rejection ratio |
| CN105278606A (en) * | 2015-11-12 | 2016-01-27 | 桂林电子科技大学 | Sub-threshold full CMOS reference voltage source |
| CN105955391A (en) * | 2016-07-14 | 2016-09-21 | 泰凌微电子（上海）有限公司 | Band-gap reference voltage generation method and circuit |
| CN107479616A (en) * | 2017-08-08 | 2017-12-15 | 深圳市锦锐科技有限公司 | A kind of super low-power consumption band-gap reference circuit |
-
2018
- 2018-12-27 CN CN201811607531.1A patent/CN109725675A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110193544A1 (en) * | 2010-02-11 | 2011-08-11 | Iacob Radu H | Circuits and methods of producing a reference current or voltage |
| CN103399609A (en) * | 2013-08-15 | 2013-11-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Nanowatt magnitude band-gap reference voltage source with low power consumption and high stability |
| CN103809647A (en) * | 2014-03-13 | 2014-05-21 | 苏州芯动科技有限公司 | Reference voltage source with high power supply rejection ratio |
| CN105278606A (en) * | 2015-11-12 | 2016-01-27 | 桂林电子科技大学 | Sub-threshold full CMOS reference voltage source |
| CN105955391A (en) * | 2016-07-14 | 2016-09-21 | 泰凌微电子（上海）有限公司 | Band-gap reference voltage generation method and circuit |
| CN107479616A (en) * | 2017-08-08 | 2017-12-15 | 深圳市锦锐科技有限公司 | A kind of super low-power consumption band-gap reference circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113114117A (en) * | 2021-04-08 | 2021-07-13 | 唐太平 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
| CN113342120A (en) * | 2021-06-25 | 2021-09-03 | 上海料聚微电子有限公司 | PTAT voltage generating circuit and band-gap reference circuit |
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