CN103383583B - Pure CMOS reference voltage source based on threshold voltage and thermal voltage - Google Patents

Abstract

The invention relates to the field of integrated circuit design, particularly to a pure CMOS (Complementary Metal Oxide Semiconductor) reference voltage source based on threshold voltage and thermal voltage. The invention discloses the pure CMOS reference voltage source based on threshold voltage and thermal voltage and adopts the technical scheme that the pure CMOS reference voltage source based on threshold voltage and thermal voltage comprises 12 NMOS (N-Metal-Oxide-Semiconductor) tubes and 14 PMOS (P-Metal-Oxide-Semiconductor) tubes. The pure CMOS reference voltage source based on threshold voltage and thermal voltage achieves the purpose of reducing the temperature coefficient by utilizing different relationships between threshold voltage and temperature and between thermal voltage and temperature and outputting reference voltage through voltage superposition. The reference voltage source provided by the invention solves the problems of complex structure, higher power consumption, larger territory area, poor CMOS compatibility and the like of the traditional reference voltage source, and rids the traditional reference voltage source of dependence on resistors, bipolar transistors and other devices. The reference voltage source provided by the invention only adopts the MOS tubes, not only is completely compatible with the CMOS technology and saves chip area, but also solves the temperature-dependent nonlinear problem of VBE.

Description

Based on the reference voltage source of thermal voltage and threshold voltage

Technical field

The present invention relates to integrated circuit (IC) design field, particularly a kind of pure CMOS reference voltage source based on threshold voltage and thermal voltage.

Background technology

Reference voltage source is as unit module circuit indispensable in integrated circuit (IC) chip, and it plays conclusive impact to the performance of whole system.Reference voltage has determined the important system indexs such as the current value flowing through in the oscillation frequency, power tube of trigging signal, the oscillator of comparer under normal circumstances.Based on above situation, improve constantly for the requirement of reference voltage source circuit just, occurred a lot of circuit structures.

General conventional reference voltage source is the bandgap voltage reference of the employing BJT that proposes first of Widlar in 1971, it is that the difference of utilizing the voltage of the base-emitter of BJT to have two emitter junction voltages of negative temperature coefficient and different emitter junction areas has positive temperature coefficient (PTC), by both weighting summations, obtain the reference voltage of zero-temperature coefficient.But because BJT pipe is bad with the compatibility of CMOS technique, its development is restricted.Calendar year 2001 Filanovsky etc. points out below lower than a certain offset operation point, the gate source voltage of MOSFET and the relation of temperature that are offset to fixing leakage current are accurate exponential relationships, based on this achievement in research, can carry out design basis voltage source with the base-emitter voltage of the gate source voltage replacement BJT of MOSFET, realize the design of pure cmos device reference voltage source.

As shown in Figure 1, list of references " Tien-Yu Lo; Chung-Chih Hung; Mohammed Ismail.CMOS voltage reference based on threshold voltage and thermal voltage; Analog Integr.Circ.Sig.Process; 2010. " has proposed a kind of pure CMOS reference voltage source, although avoided use V _bEthe nonlinear problem of bringing, but still need to use resistance (R1～R5 in Fig. 1), and in the digital CMOS process of standard, resistance need to utilize low resistance silicide to realize, not only take larger chip area, be subject to process deviation influence very large, the coupling that also can increase substrate noise; In Fig. 1 circuit, used in addition two amplifiers (A0 in Fig. 1 and A1), not only power consumption can be larger, and the non-ideal factor of amplifier also can cause adverse effect to benchmark.

Summary of the invention

The object of the invention is the problems referred to above that exist in order to solve existing reference voltage source, proposed a kind of reference voltage source based on threshold voltage and thermal voltage.

The present invention solve the technical problem, and the technical scheme of employing is, based on the reference voltage source of thermal voltage and threshold voltage, it is characterized in that, comprising: 12 NMOS pipes and 14 PMOS manage; Concrete annexation is as follows:

The source of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 5th PMOS pipe, the 7th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe and the 13 PMOS pipe connects supply voltage; Source, the source of the 6th NMOS pipe and the equal earthing potential of drain terminal of the 14 PMOS pipe of the source of the grid end of the one PMOS pipe, the source of a NMOS pipe and drain terminal, the 2nd NMOS pipe, the source of the 3rd NMOS pipe, the 4th NMOS pipe; The drain terminal of the one PMOS pipe, the grid end of the 2nd PMOS pipe are all connected with the grid end of a NMOS pipe; The 2nd NMOS pipe grid end is all connected with the drain terminal of the 2nd PMOS pipe with the grid end of drain terminal, the 3rd NMOS pipe, the grid end of the 4th NMOS pipe, the drain terminal of the 4th PMOS pipe; The grid end of the 3rd PMOS pipe is all connected with the source of the 4th PMOS pipe with drain terminal; The grid end of the 4th PMOS pipe, the drain terminal of the 4th NMOS pipe are all connected with the drain terminal of the 8th PMOS pipe; The drain terminal of the 5th PMOS pipe is connected with the source of the 6th PMOS pipe; The drain terminal of the grid end of the 5th PMOS pipe, the grid end of the 6th PMOS pipe and drain terminal, the 3rd NMOS pipe is all connected with the grid end of the 8th PMOS pipe; The grid end of the grid end of the 7th PMOS pipe and drain terminal, the 9th PMOS pipe, the grid end of the tenth PMOS pipe, the grid end of the 11 PMOS pipe, the grid end of the 12 PMOS pipe, the grid end of the 13 PMOS pipe are all connected with the source of the 8th PMOS pipe; The grid end of the 5th NMOS pipe is all connected with the drain terminal of the 9th PMOS pipe with the grid end of drain terminal, the 6th NMOS pipe; The source of the 5th NMOS pipe, the drain terminal of the 6th NMOS pipe are all connected with the source of the 8th NMOS pipe; The grid end of the 7th NMOS pipe is all connected with the drain terminal of the tenth PMOS pipe with the grid end of drain terminal, the 8th NMOS pipe; The source of the 7th NMOS pipe, the drain terminal of the 8th NMOS pipe are all connected with the source of the tenth NMOS pipe; The grid end of the 9th NMOS pipe is all connected with the drain terminal of the 11 PMOS pipe with the grid end of drain terminal, the tenth NMOS pipe; The source of the 9th NMOS pipe, the drain terminal of the tenth NMOS pipe are all connected with the source of the 12 NMOS pipe; The grid end of the 11 NMOS pipe is all connected with the drain terminal of the 12 PMOS pipe with the grid end of drain terminal, the 12 NMOS pipe; The source of the 11 NMOS pipe, the drain terminal of the 12 NMOS pipe are all connected with the grid end of the 14 PMOS pipe; The source of the 14 PMOS pipe is connected with the drain terminal of the 13 PMOS pipe.

Further, described reference voltage source is made into integrated circuit.

Concrete, described integrated circuit adopts standard CMOS process to make.

The invention has the beneficial effects as follows, reference voltage source of the present invention overcome that traditional benchmark voltage source complex structure, power consumption are large, chip area is large, with the problem such as CMOS poor compatibility, broken away from the dependence for the device such as resistance, bipolar transistor in traditional benchmark voltage source.The present invention all adopts metal-oxide-semiconductor, and not only completely compatible with CMOS technique, saving chip area, has also overcome V _bEwith the nonlinear problem of temperature; Do not adopt resistance, and simple in structure, not only greatly reduce chip area, also reduce the impact of substrate noise coupling; Part branch road is operated in Subthreshold operation, and power consumption is very low, only has 5uw 25 DEG C time; Reference voltage is smaller to the sensitivity of supply voltage, and emulation is presented at 100k frequency range PSRR (Power Supply Rejection Ratio) more than 50db.

Brief description of the drawings

Fig. 1 is prior art reference voltage source structural representation;

Fig. 2 is reference voltage source circuit structural representation of the present invention.

Wherein: MN1～MN12 is respectively the first to the 12 NMOS pipe; MP1～MP14 is respectively the first to the 14 PMOS pipe.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

The present invention is based on the reference voltage source of threshold voltage and thermal voltage, particular circuit configurations as shown in Figure 2, comprising: 12 NMOS pipe: MN1～MN12,14 PMOS pipe: MP1～MP14.Concrete annexation is as follows:

The source of MP1, MP2, MP3, MP5, MP9, MP10, MP11, MP12, MP13 meets supply voltage VDD; The equal earthing potential VSS of drain terminal of the source of the source of the grid end of MP1, the source of MN1 and drain terminal, MN2, the source of MN3, MN4, the source of MN6, MP14; The drain terminal of MP1, the grid end of MP2 are all connected with the grid end of MN1; The grid end of MN2, MN3, MN4 and the drain terminal of MN3 are all connected with the drain terminal of MP2; The grid end of MP3 is all connected with the source of MP4 with drain terminal; The grid end of MP4, the drain terminal of MN4 are all connected with the drain terminal of MP8; The drain terminal of MP5 is connected with the source of MP6; The drain terminal of the grid end of MP5, the grid end of MP6 and drain terminal and MN3 is all connected with the grid end of MP8; The grid end of the grid end of the grid end of MP7 and the grid end of drain terminal, MP9, MP10, the grid end of MP11, MP12, the grid end of MP13 are all connected with the source of MP8; The grid end of MN5 is all connected with the drain terminal of MP9 with the grid end of drain terminal, MN6; The source of MN5, the drain terminal of MN6 are all connected with the source of MN8; The grid end of MN7 is all connected with the drain terminal of MP10 with the grid end of drain terminal, MN8; The source of MN7, the drain terminal of MN8 are all connected with the source of MN10; The grid end of MN9 is all connected with the drain terminal of MP11 with the grid end of drain terminal, MN10; The source of MN9, the drain terminal of MN10 are all connected with the source of MN12; The grid end of MN11 is all connected with the drain terminal of MP12 with the grid end of drain terminal, MN12; The source of MN11, the drain terminal of MN12 are all connected with the grid end of MP14; The source of MP14 is connected with the drain terminal of MP13.

NMOS pipe MN1 and PMOS pipe MP1, MP2 composition start-up circuit.In the time that VDD starts to rise by 0, because MP2 grid voltage is lower, MP2, to benchmark core circuit Injection Current, makes benchmark break away from zero degeneracy state; Along with the mos capacitance charging that MP1 constantly forms to MN1, the grid voltage of MP2 constantly raises and closes gradually, starts and finishes, and after the normal work of reference circuit, this start-up circuit does not have quiescent current.

NMOS pipe MN2, MN3, MN4 and PMOS pipe MP3, MP4, MP5, MP6, MP7, MP8 composition threshold value squared current produce circuit.The circuit core that wherein MP5, MP6, MP7, MP8, MN3, MN4 form generates and threshold voltage V _tHPbecome the electric current of quadratic relationship; By I is set ₁: I ₂=4:1 makes A point voltage in figure be biased in VDD-|V _tHP|, result is to have realized electric current I ₁and I ₂be direct proportion function; In addition, in order to reduce the difference of MN3, MN4 drain voltage, the voltage clamping circuit that MP3, MP4, MN2 form, has improved output reference voltage with power vd D amplitude of variation, has also improved to a certain extent the PSRR performance of reference circuit.

NMOS pipe MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12 level Four stepped construction form the PTAT voltage generation circuit proportional with temperature, and making B point voltage in Fig. 2 is one and thermal voltage V _tthe PTAT voltage being directly proportional, PMOS pipe MP9, MP10, MP11, MP12 provide bias current for each branch road.

The be inversely proportional to CTAT voltage generation circuit of relation of PMOS pipe MP13, MP14 composition and temperature, MP13 provides bias current for branch road, and the poor absolute value of MP14 gate source voltage is and threshold voltage absolute value | V _tHP| the CTAT voltage being directly proportional.

The grid that PTAT voltage is added to PMOS pipe MP14, the source voltage of MP14 is reference voltage V _rEF.

Specific works principle of the present invention and theoretical derivation are as follows:

MP5 is set and is operated in linear zone, MP6, MP7, MP8 are operated in saturation region and dimension scale is identical and enough large, i.e. (W/L) _p6=(W/L) _p7=(W/L) _p8.Arrange (W/L) _p3=(W/L) _p4=(W/L) _p6, (W/L) _n2=4 (W/L) _n3=(W/L) _n4therefore, I ₁=4I ₂, have:

|V _GSP6|-|V _THP|＝2(|V _GSP7,8|-|V _THP|) (1)

|V _DSP5|＝2|V _GSP7,8|-|V _GSP6|＝|V _THP| (2)

$I_1={\mathrm{\μ}}_P{C}_{\mathrm{OX}}{(W/L)}_{P5}\left[\left(\right|V_{\mathrm{GSP}5}|-|V_{\mathrm{THP}}\left|\right)\right|V_{\mathrm{THP}}|-\frac{1}{2}{\left|V_{\mathrm{THP}}\right|}^2]=\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}{(W/L)}_{P6}{\left(\right|V_{\mathrm{GSP}6}|-|V_{\mathrm{THP}}\left|\right)}^2---\left(3\right)$

$I_1=4I_2=\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}{(W/L)}_{P5}{(\sqrt{M}+\sqrt{M+1})}^2{\left|V_{\mathrm{THP}}\right|}^2---\left(4\right)$

Wherein, M is v _dSPifor the drain-source voltage of PMOS pipe MPi, V _gSPifor the gate source voltage of PMOS pipe MPi, (W/L) _pifor the breadth length ratio of PMOS pipe MPi, V _tHPfor the threshold voltage of PMOS pipe.

For PTAT voltage generation circuit, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12 are set, are operated in sub-threshold region, the bias current providing by MP9, MP10, MP11, MP12 mirror image equates, V _t=kT/q, has:

$V_{\mathrm{GSMN}6}-V_{\mathrm{GSMN}5}=\mathrm{\η}{V}_T\ln [4{\left(\frac{W}{L}\right)}_{N5}/{\left(\frac{W}{L}\right)}_{N6}]=\mathrm{\η}{V}_T{K}_1---\left(5\right)$

$V_{\mathrm{GSMN}8}-V_{\mathrm{GSMN}7}=\mathrm{\η}{V}_T\ln [3{\left(\frac{W}{L}\right)}_{N7}/{\left(\frac{W}{L}\right)}_{N8}]=\mathrm{\η}{V}_T{K}_2---\left(6\right)$

$V_{\mathrm{GSMN}10}-V_{\mathrm{GSMN}9}=\mathrm{\η}{V}_T\ln [2{\left(\frac{W}{L}\right)}_{N9}/{\left(\frac{W}{L}\right)}_{N10}]=\mathrm{\η}{V}_T{K}_3---\left(7\right)$

$V_{\mathrm{GSMN}12}-V_{\mathrm{GSMN}11}=\mathrm{\η}{V}_T\ln [{\left(\frac{W}{L}\right)}_{N11}/{\left(\frac{W}{L}\right)}_{N12}]=\mathrm{\η}{V}_T{K}_4---\left(8\right)$

V _B＝(V _GSMN6-V _GSMN5)+(V _GSMN8-V _GSMN7)+(V _GSMN10-V _GSMN9)+(V _GSMN12-V _GSMN11) (9)

For CTAT voltage generation circuit, MP13 is set, MP14 is operated in saturation region, and (W/L) _p13=m (W/L) _p7, have:

I ₃＝mI ₂ (10)

$\left|V_{\mathrm{GSP}14}\right|=\sqrt{\frac{2I_3}{{\mathrm{\μ}}_P{C}_{\mathrm{OX}}{\left(\frac{W}{L}\right)}_{P14}}}+\left|V_{\mathrm{THP}}\right|---\left(11\right)$

For voltage stack output circuit, can obtain output reference voltage V _rEFfor:

V _REF＝V _B+|V _GSP14|＝AV _T+B|V _THP| (12)

Wherein,

A＝η(K ₁+K ₂+K ₃+K ₄) (13)

$B=[1+(\sqrt{M}+\sqrt{M+1})\sqrt{\frac{m{(W/L)}_{P5}}{4{(W/L)}_{P14}}}]---\left(14\right)$

Can find out, by adjusting K ₁, K ₂, K ₃, K ₄, M, m, can obtain temperature independent reference voltage.

The present invention is based on the reference voltage source of thermal voltage and threshold voltage, owing to entering CMOS technique completely, can adopt standard CMOS integrated circuit technology that reference voltage source is made to integrated circuit, other functional circuits on same chip are combined, and form the integrated circuit (IC) products with specific function.

Claims (3)

1. the reference voltage source based on thermal voltage and threshold voltage, is characterized in that, comprising: 12 NMOS pipes and 14 PMOS pipes; Concrete annexation is as follows:

The source of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 5th PMOS pipe, the 7th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe and the 13 PMOS pipe connects supply voltage; Source, the source of the 6th NMOS pipe and the equal earthing potential of drain terminal of the 14 PMOS pipe of the source of the grid end of the one PMOS pipe, the source of a NMOS pipe and drain terminal, the 2nd NMOS pipe, the source of the 3rd NMOS pipe, the 4th NMOS pipe; The drain terminal of the one PMOS pipe, the grid end of the 2nd PMOS pipe are all connected with the grid end of a NMOS pipe; The 2nd NMOS pipe grid end is all connected with the drain terminal of the 2nd PMOS pipe with the grid end of drain terminal, the 3rd NMOS pipe, the grid end of the 4th NMOS pipe, the drain terminal of the 4th PMOS pipe; The grid end of the 3rd PMOS pipe is all connected with the source of the 4th PMOS pipe with drain terminal; The grid end of the 4th PMOS pipe, the drain terminal of the 4th NMOS pipe are all connected with the drain terminal of the 8th PMOS pipe; The drain terminal of the 5th PMOS pipe is connected with the source of the 6th PMOS pipe; The drain terminal of the grid end of the 5th PMOS pipe, the grid end of the 6th PMOS pipe and drain terminal, the 3rd NMOS pipe is all connected with the grid end of the 8th PMOS pipe; The grid end of the grid end of the 7th PMOS pipe and drain terminal, the 9th PMOS pipe, the grid end of the tenth PMOS pipe, the grid end of the 11 PMOS pipe, the grid end of the 12 PMOS pipe, the grid end of the 13 PMOS pipe are all connected with the source of the 8th PMOS pipe; The grid end of the 5th NMOS pipe is all connected with the drain terminal of the 9th PMOS pipe with the grid end of drain terminal, the 6th NMOS pipe; The source of the 5th NMOS pipe, the drain terminal of the 6th NMOS pipe are all connected with the source of the 8th NMOS pipe; The grid end of the 7th NMOS pipe is all connected with the drain terminal of the tenth PMOS pipe with the grid end of drain terminal, the 8th NMOS pipe; The source of the 7th NMOS pipe, the drain terminal of the 8th NMOS pipe are all connected with the source of the tenth NMOS pipe; The grid end of the 9th NMOS pipe is all connected with the drain terminal of the 11 PMOS pipe with the grid end of drain terminal, the tenth NMOS pipe; The source of the 9th NMOS pipe, the drain terminal of the tenth NMOS pipe are all connected with the source of the 12 NMOS pipe; The grid end of the 11 NMOS pipe is all connected with the drain terminal of the 12 PMOS pipe with the grid end of drain terminal, the 12 NMOS pipe; The source of the 11 NMOS pipe, the drain terminal of the 12 NMOS pipe are all connected with the grid end of the 14 PMOS pipe; The source of the 14 PMOS pipe is connected with the drain terminal of the 13 PMOS pipe.

2. the reference voltage source based on thermal voltage and threshold voltage according to claim 1, is characterized in that, described reference voltage source is made into integrated circuit.

3. the reference voltage source based on thermal voltage and threshold voltage according to claim 2, is characterized in that, described integrated circuit adopts standard CMOS process to make.