CN103383583A - Pure CMOS reference voltage source based on threshold voltage and thermal voltage - Google Patents

Pure CMOS reference voltage source based on threshold voltage and thermal voltage Download PDF

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CN103383583A
CN103383583A CN2013103023246A CN201310302324A CN103383583A CN 103383583 A CN103383583 A CN 103383583A CN 2013103023246 A CN2013103023246 A CN 2013103023246A CN 201310302324 A CN201310302324 A CN 201310302324A CN 103383583 A CN103383583 A CN 103383583A
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pipe
drain terminal
source
grid end
pmos pipe
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CN103383583B (en
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周泽坤
张其营
许天辉
苟超
崔佳男
石跃
明鑫
张波
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University of Electronic Science and Technology of China
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Abstract

The invention relates to the field of integrated circuit design, particularly to a pure CMOS (Complementary Metal Oxide Semiconductor) reference voltage source based on threshold voltage and thermal voltage. The invention discloses the pure CMOS reference voltage source based on threshold voltage and thermal voltage and adopts the technical scheme that the pure CMOS reference voltage source based on threshold voltage and thermal voltage comprises 12 NMOS (N-Metal-Oxide-Semiconductor) tubes and 14 PMOS (P-Metal-Oxide-Semiconductor) tubes. The pure CMOS reference voltage source based on threshold voltage and thermal voltage achieves the purpose of reducing the temperature coefficient by utilizing different relationships between threshold voltage and temperature and between thermal voltage and temperature and outputting reference voltage through voltage superposition. The reference voltage source provided by the invention solves the problems of complex structure, higher power consumption, larger territory area, poor CMOS compatibility and the like of the traditional reference voltage source, and rids the traditional reference voltage source of dependence on resistors, bipolar transistors and other devices. The reference voltage source provided by the invention only adopts the MOS tubes, not only is completely compatible with the CMOS technology and saves chip area, but also solves the temperature-dependent nonlinear problem of VBE.

Description

Reference voltage source based on thermal voltage and threshold voltage
Technical field
The present invention relates to the integrated circuit (IC) design field, particularly a kind of pure CMOS reference voltage source based on threshold voltage and thermal voltage.
Background technology
Reference voltage source is as unit module circuit indispensable in integrated circuit (IC) chip, and it plays conclusive impact to the performance of whole system.Generally reference voltage has determined the important system indexs such as current value that flow through in the oscillation frequency, power tube of trigging signal, the oscillator of comparer.Just be based on above situation, improving constantly for the requirement of reference voltage source circuit, a lot of circuit structures occurring.
General commonly used reference voltage source is the bandgap voltage reference of the employing BJT that proposes first of Widlar in 1971, it is that the difference of utilizing the voltage of the base-emitter of BJT to have two emitter junction voltages of negative temperature coefficient and different emitter junction areas has positive temperature coefficient (PTC), with both weighting summations, obtain the reference voltage of zero-temperature coefficient.But, compatible bad due to BJT pipe and CMOS technique, its development is restricted.Calendar year 2001 Filanovsky etc. points out below lower than a certain offset operation point, being offset to fixedly, the gate source voltage of the MOSFET of leakage current and the relation of temperature are accurate exponential relationships, based on this achievement in research, the base-emitter voltage that can replace with the gate source voltage of MOSFET BJT comes the design basis voltage source, realizes the design of pure cmos device reference voltage source.
As shown in Figure 1, list of references " Tien-Yu Lo; Chung-Chih Hung; Mohammed Ismail.CMOS voltage reference based on threshold voltage and thermal voltage; Analog Integr.Circ.Sig.Process; 2010. " has proposed a kind of pure CMOS reference voltage source, although avoided use V BEThe nonlinear problem of bringing, but still need to use resistance (R1 in Fig. 1~R5), and in the digital CMOS process of standard, resistance need to utilize the low resistance silicide to realize, not only take larger chip area, be subjected to process deviation influence very large, the coupling that also can increase substrate noise; Used in addition two amplifiers (A0 in Fig. 1 and A1) in Fig. 1 circuit, not only power consumption can be larger, and the non-ideal factor of amplifier also can cause adverse effect to benchmark.
Summary of the invention
The objective of the invention is to have proposed a kind of reference voltage source based on threshold voltage and thermal voltage in order to solve the problems referred to above of existing reference voltage source existence.
The present invention solve the technical problem, and the technical scheme of employing is that the reference voltage source based on thermal voltage and threshold voltage is characterized in that, comprising: 12 NMOS pipes and 14 PMOS pipes; Concrete annexation is as follows:
The source of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 5th PMOS pipe, the 7th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe and the 13 PMOS pipe connects supply voltage; The source of the source of the grid end of the one PMOS pipe, the source of a NMOS pipe and drain terminal, the 2nd NMOS pipe, the source of the 3rd NMOS pipe, the 4th NMOS pipe, the source of the 6th NMOS pipe and the equal earthing potential of drain terminal of the 14 PMOS pipe; The grid end of the drain terminal of the one PMOS pipe, the 2nd PMOS pipe all is connected with the grid end of a NMOS pipe; The 2nd NMOS pipe grid end all is connected with the drain terminal of the 2nd PMOS pipe with the grid end of drain terminal, the 3rd NMOS pipe, the grid end of the 4th NMOS pipe, the drain terminal of the 4th PMOS pipe; The grid end of the 3rd PMOS pipe all is connected with the source of the 4th PMOS pipe with drain terminal; The grid end of the 4th PMOS pipe, the drain terminal of the 4th NMOS pipe all are connected with the drain terminal of the 8th PMOS pipe; The drain terminal of the 5th PMOS pipe is connected with the source of the 6th PMOS pipe; The drain terminal of the grid end of the grid end of the 5th PMOS pipe, the 6th PMOS pipe and drain terminal, the 3rd NMOS pipe all is connected with the grid end of the 8th PMOS pipe; The grid end of the grid end of the 7th PMOS pipe and drain terminal, the 9th PMOS pipe, the grid end of the tenth PMOS pipe, the grid end of the 11 PMOS pipe, the grid end of the 12 PMOS pipe, the grid end of the 13 PMOS pipe all are connected with the source of the 8th PMOS pipe; , the grid end of the 5th NMOS pipe and the grid end of drain terminal, the 6th NMOS pipe all be connected with the drain terminal of the 9th PMOS pipe; The drain terminal of the source of the 5th NMOS pipe, the 6th NMOS pipe all is connected with the source of the 8th NMOS pipe; The grid end of the grid end of the 7th NMOS pipe and drain terminal, the 8th NMOS pipe all is connected with the drain terminal of the tenth PMOS pipe; The drain terminal of the source of the 7th NMOS pipe, the 8th NMOS pipe all is connected with the source of the tenth NMOS pipe; The grid end of the 9th NMOS pipe all is connected with the drain terminal of the 11 PMOS pipe with the grid end of drain terminal, the tenth NMOS pipe; The drain terminal of the source of the 9th NMOS pipe, the tenth NMOS pipe all is connected with the source of the 12 NMOS pipe; The grid end of the 11 NMOS pipe all is connected with the drain terminal of the 12 PMOS pipe with the grid end of drain terminal, the 12 NMOS pipe; The source of the 11 NMOS pipe, the drain terminal of the 12 NMOS pipe all are connected with the grid end of the 14 PMOS pipe; The source of the 14 PMOS pipe is connected with the drain terminal of the 13 PMOS pipe.
Further, described reference voltage source is made into integrated circuit.
Concrete, described integrated circuit adopts standard CMOS process to make.
The invention has the beneficial effects as follows, reference voltage source of the present invention overcome that traditional benchmark voltage source complex structure, power consumption are large, chip area is large, with the problem such as CMOS poor compatibility, broken away from the traditional benchmark voltage source dependence for devices such as resistance, bipolar transistors.The present invention all adopts metal-oxide-semiconductor, and not only fully compatible with CMOS technique, saving chip area has also overcome V BENonlinear problem with temperature; Do not adopt resistance, and simple in structure, not only greatly reduced chip area, also reduced the impact of substrate noise coupling; The part branch road is operated in Subthreshold operation, and power consumption is very low, only has 5uw in the time of 25 ℃; Reference voltage is smaller to the sensitivity of supply voltage, and emulation is presented at 100k frequency range PSRR(Power Supply Rejection Ratio) more than 50db.
Description of drawings
Fig. 1 is prior art reference voltage source structural representation;
Fig. 2 is reference voltage source circuit structural representation of the present invention.
Wherein: MN1~MN12 is respectively the first to the 12 NMOS pipe; MP1~MP14 is respectively the first to the 14 PMOS pipe.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
The present invention is based on the reference voltage source of threshold voltage and thermal voltage, particular circuit configurations comprises as shown in Figure 2: 12 NMOS pipe: MN1~MN12,14 PMOS pipe: MP1~MP14.Concrete annexation is as follows:
The source of MP1, MP2, MP3, MP5, MP9, MP10, MP11, MP12, MP13 meets supply voltage VDD; The equal earthing potential VSS of drain terminal of the source of the source of the grid end of MP1, the source of MN1 and drain terminal, MN2, the source of MN3, MN4, the source of MN6, MP14; The grid end of the drain terminal of MP1, MP2 all is connected with the grid end of MN1; The grid end of MN2, MN3, MN4 and the drain terminal of MN3 all are connected with the drain terminal of MP2; The grid end of MP3 all is connected with the source of MP4 with drain terminal; The grid end of MP4, the drain terminal of MN4 all are connected with the drain terminal of MP8; The drain terminal of MP5 is connected with the source of MP6; The drain terminal of the grid end of MP5, the grid end of MP6 and drain terminal and MN3 all is connected with the grid end of MP8; The grid end of the grid end of the grid end of MP7 and the grid end of drain terminal, MP9, MP10, the grid end of MP11, MP12, the grid end of MP13 all are connected with the source of MP8; The grid end of MN5 all is connected with the drain terminal of MP9 with the grid end of drain terminal, MN6; The source of MN5, the drain terminal of MN6 all are connected with the source of MN8; The grid end of MN7 all is connected with the drain terminal of MP10 with the grid end of drain terminal, MN8; The source of MN7, the drain terminal of MN8 all are connected with the source of MN10; The grid end of MN9 all is connected with the drain terminal of MP11 with the grid end of drain terminal, MN10; The source of MN9, the drain terminal of MN10 all are connected with the source of MN12; The grid end of MN11 all is connected with the drain terminal of MP12 with the grid end of drain terminal, MN12; The source of MN11, the drain terminal of MN12 all are connected with the grid end of MP14; The source of MP14 is connected with the drain terminal of MP13.
NMOS pipe MN1 and PMOS pipe MP1, MP2 form start-up circuit.When VDD began to rise by 0, because the MP2 grid voltage is lower, MP2 made benchmark break away from zero degeneracy state to benchmark core circuit Injection Current; Along with the mos capacitance charging that MP1 constantly forms to MN1, the grid voltage of MP2 constantly raises and closes gradually, starts to finish, and after the reference circuit normal operation, this start-up circuit does not have quiescent current.
NMOS pipe MN2, MN3, MN4 and PMOS pipe MP3, MP4, MP5, MP6, MP7, MP8 form the threshold value squared current and produce circuit.Wherein the circuit core of MP5, MP6, MP7, MP8, MN3, MN4 formation generates and threshold voltage V THPBecome the electric current of quadratic relationship; By I is set 1: I 2=4:1 makes that in figure, the A point voltage is biased in VDD-|V THP|, result is to have realized electric current I 1And I 2Be
Figure BDA00003524730500031
Direct proportion function; In addition, in order to reduce the difference of MN3, MN4 drain voltage, the voltage clamping circuit that MP3, MP4, MN2 consist of has improved output reference voltage with power vd D amplitude of variation, has also improved to a certain extent the PSRR performance of reference circuit.
NMOS pipe MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12 level Four stepped construction consist of the PTAT voltage generation circuit proportional with temperature, make in Fig. 2 the B point voltage be one with thermal voltage V TThe PTAT voltage that is directly proportional, PMOS pipe MP9, MP10, MP11, MP12 provide bias current for each branch road.
The CTAT voltage generation circuit of relation that PMOS pipe MP13, MP14 form and temperature is inversely proportional to, MP13 provides bias current for branch road, and the poor absolute value of MP14 gate source voltage is and the threshold voltage absolute value | V THP| the CTAT voltage that is directly proportional.
PTAT voltage is added to the grid of PMOS pipe MP14, the source voltage of MP14 is reference voltage V REF
Specific works principle of the present invention and theoretical derivation are as follows:
MP5 is set is operated in linear zone, MP6, MP7, MP8 are operated in the saturation region and dimension scale is identical and enough large, i.e. (W/L) P6=(W/L) P7=(W/L) P8Arrange (W/L) P3=(W/L) P4=(W/L) P6, (W/L) N2=4 (W/L) N3=(W/L) N4Therefore, I 1=4I 2, have:
|V GSP6|-|V THP|=2(|V GSP7,8|-|V THP|) (1)
|V DSP5|=2|V GSP7,8|-|V GSP6|=|V THP| (2)
I 1 = μ P C OX ( W / L ) P 5 [ ( | V GSP 5 | - | V THP | ) | V THP | - 1 2 | V THP | 2 ] = 1 2 μ P C OX ( W / L ) P 6 ( | V GSP 6 | - | V THP | ) 2 (3)
I 1 = 4 I 2 = 1 2 μ P C OX ( W / L ) P 5 ( M + M + 1 ) 2 | V THP | 2 (4)
Wherein, M is
Figure BDA00003524730500042
V DSPiBe the drain-source voltage of PMOS pipe MPi, V GSPiBe the gate source voltage of PMOS pipe MPi, (W/L) PiBe the breadth length ratio of PMOS pipe MPi, V THPThreshold voltage for the PMOS pipe.
For the PTAT voltage generation circuit, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12 are set, are operated in sub-threshold region, the bias current that provides by MP9, MP10, MP11, MP12 mirror image equates, V T=kT/q has:
V GSMN 6 - V GSMN 5 = ηV T ln [ 4 ( W L ) N 5 / ( W L ) N 6 ] = ηV T K 1 (5)
V GSMN 8 - V GSMN 7 = ηV T ln [ 3 ( W L ) N 7 / ( W L ) N 8 ] = ηV T K 2 (6)
V GSMN 10 - V GSMN 9 = ηV T ln [ 2 ( W L ) N 9 / ( W L ) N 10 ] = ηV T K 3 (7)
V GSMN 12 - V GSMN 11 = ηV T ln [ ( W L ) N 11 / ( W L ) N 12 ] = ηV T K 4 (8)
V B=(V GSMN6-V GSMN5)+(V GSMN8-V GSMN7)+(V GSMN10-V GSMN9)+(V GSMN12-V GSMN11) (9)
For the CTAT voltage generation circuit, MP13 is set, MP14 is operated in the saturation region, and (W/L) P13=m (W/L) P7, have:
I 3=mI 2 (10)
| V GSP 14 | = 2 I 3 μ P C OX ( W L ) P 14 + | V THP | (11)
For voltage stack output circuit, can obtain output reference voltage V REFFor:
V REF=V B+|V GSP14|=AV T+B|V THP| (12)
Wherein,
A=η(K 1+K 2+K 3+K 4) (13)
B = [ 1 + ( M + M + 1 ) m ( W / L ) P 5 4 ( W / L ) P 14 ] (14)
Can find out, by adjusting K 1, K 2, K 3, K 4, M, m,
Figure BDA00003524730500053
Can obtain temperature independent reference voltage.
The present invention is based on the reference voltage source of thermal voltage and threshold voltage, owing to entering CMOS technique fully, can adopt the standard CMOS integrated circuit technology that reference voltage source is made integrated circuit, other functional circuits on same chip are combined, and consist of the integrated circuit (IC) products with specific function.

Claims (3)

1. based on the reference voltage source of thermal voltage and threshold voltage, it is characterized in that, comprising: 12 NMOS pipes and 14 PMOS pipes; Concrete annexation is as follows:
The source of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 5th PMOS pipe, the 7th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe and the 13 PMOS pipe connects supply voltage; The source of the source of the grid end of the one PMOS pipe, the source of a NMOS pipe and drain terminal, the 2nd NMOS pipe, the source of the 3rd NMOS pipe, the 4th NMOS pipe, the source of the 6th NMOS pipe and the equal earthing potential of drain terminal of the 14 PMOS pipe; The grid end of the drain terminal of the one PMOS pipe, the 2nd PMOS pipe all is connected with the grid end of a NMOS pipe; The 2nd NMOS pipe grid end all is connected with the drain terminal of the 2nd PMOS pipe with the grid end of drain terminal, the 3rd NMOS pipe, the grid end of the 4th NMOS pipe, the drain terminal of the 4th PMOS pipe; The grid end of the 3rd PMOS pipe all is connected with the source of the 4th PMOS pipe with drain terminal; The grid end of the 4th PMOS pipe, the drain terminal of the 4th NMOS pipe all are connected with the drain terminal of the 8th PMOS pipe; The drain terminal of the 5th PMOS pipe is connected with the source of the 6th PMOS pipe; The drain terminal of the grid end of the grid end of the 5th PMOS pipe, the 6th PMOS pipe and drain terminal, the 3rd NMOS pipe all is connected with the grid end of the 8th PMOS pipe; The grid end of the grid end of the 7th PMOS pipe and drain terminal, the 9th PMOS pipe, the grid end of the tenth PMOS pipe, the grid end of the 11 PMOS pipe, the grid end of the 12 PMOS pipe, the grid end of the 13 PMOS pipe all are connected with the source of the 8th PMOS pipe; , the grid end of the 5th NMOS pipe and the grid end of drain terminal, the 6th NMOS pipe all be connected with the drain terminal of the 9th PMOS pipe; The drain terminal of the source of the 5th NMOS pipe, the 6th NMOS pipe all is connected with the source of the 8th NMOS pipe; The grid end of the grid end of the 7th NMOS pipe and drain terminal, the 8th NMOS pipe all is connected with the drain terminal of the tenth PMOS pipe; The drain terminal of the source of the 7th NMOS pipe, the 8th NMOS pipe all is connected with the source of the tenth NMOS pipe; The grid end of the 9th NMOS pipe all is connected with the drain terminal of the 11 PMOS pipe with the grid end of drain terminal, the tenth NMOS pipe; The drain terminal of the source of the 9th NMOS pipe, the tenth NMOS pipe all is connected with the source of the 12 NMOS pipe; The grid end of the 11 NMOS pipe all is connected with the drain terminal of the 12 PMOS pipe with the grid end of drain terminal, the 12 NMOS pipe; The source of the 11 NMOS pipe, the drain terminal of the 12 NMOS pipe all are connected with the grid end of the 14 PMOS pipe; The source of the 14 PMOS pipe is connected with the drain terminal of the 13 PMOS pipe.
2. the reference voltage source based on thermal voltage and threshold voltage according to claim 1, is characterized in that, described reference voltage source is made into integrated circuit.
3. the reference voltage source based on thermal voltage and threshold voltage according to claim 2, is characterized in that, described integrated circuit adopts standard CMOS process to make.
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CN105224006A (en) * 2015-10-28 2016-01-06 电子科技大学 A kind of low voltage CMOS reference source
CN106527572A (en) * 2016-12-08 2017-03-22 电子科技大学 CMOS subthreshold reference circuit with low power dissipation and low temperature drift
CN107015595A (en) * 2017-05-03 2017-08-04 苏州大学 It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source
WO2018032308A1 (en) * 2016-08-16 2018-02-22 深圳市汇顶科技股份有限公司 Linear regulator
CN108427471A (en) * 2018-06-05 2018-08-21 北京中电华大电子设计有限责任公司 A kind of zero-temperature coefficient super low-power consumption reference voltage circuit
CN110100219A (en) * 2017-11-28 2019-08-06 深圳市汇顶科技股份有限公司 Voltage-stablizer and power supply
CN110502056A (en) * 2019-08-22 2019-11-26 成都飞机工业(集团)有限责任公司 A kind of threshold voltage reference circuit

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Publication number Priority date Publication date Assignee Title
CN103701411A (en) * 2013-12-13 2014-04-02 电子科技大学 CMOS (complementary metal oxide semiconductor) relaxation oscillator with temperature and process self-compensating characteristics
CN103701411B (en) * 2013-12-13 2017-01-25 电子科技大学 CMOS (complementary metal oxide semiconductor) relaxation oscillator with temperature and process self-compensating characteristics
CN105224006A (en) * 2015-10-28 2016-01-06 电子科技大学 A kind of low voltage CMOS reference source
CN105224006B (en) * 2015-10-28 2017-02-15 电子科技大学 Low-voltage CMOS reference source
WO2018032308A1 (en) * 2016-08-16 2018-02-22 深圳市汇顶科技股份有限公司 Linear regulator
CN106527572A (en) * 2016-12-08 2017-03-22 电子科技大学 CMOS subthreshold reference circuit with low power dissipation and low temperature drift
CN106527572B (en) * 2016-12-08 2018-01-09 电子科技大学 A kind of low-power consumption Low Drift Temperature CMOS subthreshold value reference circuits
CN107015595A (en) * 2017-05-03 2017-08-04 苏州大学 It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source
CN110100219A (en) * 2017-11-28 2019-08-06 深圳市汇顶科技股份有限公司 Voltage-stablizer and power supply
US10599173B2 (en) 2017-11-28 2020-03-24 Shenzhen GOODIX Technology Co., Ltd. Voltage regulator and power supply
CN108427471A (en) * 2018-06-05 2018-08-21 北京中电华大电子设计有限责任公司 A kind of zero-temperature coefficient super low-power consumption reference voltage circuit
CN110502056A (en) * 2019-08-22 2019-11-26 成都飞机工业(集团)有限责任公司 A kind of threshold voltage reference circuit

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