CN107015595A - It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source - Google Patents

It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source Download PDF

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CN107015595A
CN107015595A CN201710305181.2A CN201710305181A CN107015595A CN 107015595 A CN107015595 A CN 107015595A CN 201710305181 A CN201710305181 A CN 201710305181A CN 107015595 A CN107015595 A CN 107015595A
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nmos tube
pmos
drain electrode
grid
connection
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吴晨健
戴晶星
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Suzhou University
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Suzhou University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

Subthreshold region high-precision low-power consumption low-voltage bandgap reference source is operated in present invention relates particularly to one kind, is designed to overcome the problem of traditional bandgap a reference source structure precision is not enough.The present invention, which is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, to be included：Current mirroring circuit, produces the PTAT generation circuits of positive temperature coefficient voltage, produces the CTAT generation circuits of negative temperature coefficient voltage, linear compensation circuit output offset, offset, positive temperature coefficient voltage and negative temperature coefficient voltage are done and, generation reference voltage VREF.The present invention is realized in the case of low supply voltage, stable output wide temperature range, high-accuracy voltage.

Description

It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source
Technical field
The invention belongs to analogue layout field, and in particular to it is low that one kind is operated in subthreshold region high-precision low-power consumption Voltage bandgap reference source.
Background technology
Bandgap voltage reference module is widely applied in various Analogous Integrated Electronic Circuits, the module be absorbed in set up one with Power supply, flow-route and temperature change unrelated DC voltage.The performance of reference voltage source module directly affects whole circuit system Precision.With current chip integrated level more and more higher, supply voltage is more and more lower, band-gap reference required precision more and more higher, The band-gap reference of traditional structure faces great challenge, it usually needs use high-order temperature compensated technology.
The traditional structure worked under low supply voltage state is as shown in figure 8, be by amplifier so that the current potential of both sides Equal, so that identical with the pressure drop on R2 by two side resistance R1, now the resistance R3 in PNP type triode can produce a pressure Drop, the pressure drop finally produced afterwards by current mirror on output resistance R4 is exactly reference voltage.But it is due to low-voltage state Lower amplifier is not only difficult to design but also can produce larger power consumption to influence performance.
The metal-oxide-semiconductor of subthreshold region work may can solve the problem that traditional structure problem encountered, but be due to that subthreshold region is difficult to It is stable, the problems such as introducing the new technological parameter related to temperature, the band-gap reference circuit for working in sub-threshold region is also difficult to set Meter, but it can be seen that the band gap reference for working in sub-threshold region can be a trend of future development.
In view of above-mentioned defect, the design people is actively subject to research and innovation, and subthreshold region height is operated in found one kind Precision low consumption low voltage band gap reference, makes it with more the value in industry.
The content of the invention
In order to solve the above technical problems, it is an object of the invention to provide a kind of temperature-compensating thinking of innovation, so as to realize The benchmark for exporting a zero-temperature coefficient is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source.
To achieve the above object of the invention, the present invention is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, bag Include：Current mirroring circuit, produces the PTAT generation circuits of positive temperature coefficient voltage, and the CTAT for producing negative temperature coefficient voltage produces electricity Road, linear compensation circuit output offset, offset, positive temperature coefficient voltage and negative temperature coefficient voltage are done and, generation base Quasi- voltage VREF；
Wherein, the current mirroring circuit includes PMOS M9, PMOS M8, PMOS M13, PMOS M14 and n PMOS, i.e. PMOS M101, PMOS M102 ... PMOSs M10n；PMOS M9, PMOS M8PMOS pipes M13, PMOS Pipe M14 and n PMOS source electrode connection VDD；PMOS M8 drain electrode connection PMOS M8 grid；PMOS M14's Drain electrode connection PMOS M14 grid；
PMOS M9, PMOS M8, PMOS M101, PMOS M102 ... PMOSs M10n grid and the first order are certainly The drain electrode for biasing the upper strata NMOS tube M3 of stacked structure is connected；PMOS M13, PMOS M14 grid and NMOS tube M15 leakage Extremely it is connected；PMOS M9 is connected with PNP type triode Q0 emitter stage；PMOS M101 drain electrode is stacked with second level automatic biasing The upper strata NMOS tube M111 of structure drain electrode is connected；PMOS M102 drain electrode and the upper strata of third level automatic biasing stacked structure NMOS tube M112 drain electrode is connected；... PMOS M10m drain electrode and the upper strata NMOS tube of n-th grade of automatic biasing stacked structure M11m drain electrode is connected；PMOS M10n drain electrode and the lower floor NMOS tube M12m of afterbody automatic biasing stacked structure drain electrode It is connected；PMOS M13 drain electrode is connected with PNP type triode Q1 emitter stage；PMOS M14 drain electrode is with NMOS tube M15's Drain electrode is connected；
PTAT generation circuits include m grade automatic biasing stacked structures, automatic biasing stacked structures at different levels include upper strata NMOS tube with Lower floor's NMOS tube, the source electrode of the upper strata NMOS tube of automatic biasing stacked structures at different levels is connected with the drain electrode of lower floor's NMOS tube；One-level is certainly Bias the drain electrode connection of the source electrode of lower floor's NMOS tube of stacked structure and lower floor's NMOS tube of previous stage automatic biasing stacked structure；The The upper strata NMOS tube M11m of m grades of automatic biasing stacked structures grid is connected to together with drain electrode, lower floor NMOS tube M12m grid PMOS M10n drain electrode；The upper strata NMOS tube M111 of second level automatic biasing stacked structure drain electrode and grid, lower floor's NMOS tube M121 grid all connects PMOS M101 drain electrode；... the upper strata NMOS tube M11m of m grades of automatic biasing stacked structures leakage Pole and grid, lower floor NMOS tube M12m grid all connect PMOS M10m drain electrode；First order automatic biasing stacked structure it is upper Layer NMOS tube M3 and lower floor NMOS tube M2 grid is connected to PNP type triode Q0 emitter stage together；First order automatic biasing heap The upper strata NMOS tube M3 of stack structure drain electrode connection PMOS M101 drain electrode；The lower floor NMOS of first order automatic biasing stacked structure Pipe M2 source electrode connection NMOS tube M1 drain electrode；M=n-1；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0；PNP type triode Q0 colelctor electrode, base stage connection ground；PNP type triode Q0 emitter stage connection PMOS M9 drain electrode；NMOS tube M3 and NMOS Pipe M2 grid is connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode； NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode；NMOS Pipe M1 source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1；The pole of positive-negative-positive three Pipe Q1 emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector；NMOS tube M15 and NMOS tube M16 grid connection PNP type triode Q1 emitter stage；NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connection NMOS tube M17 drain electrode；NMOS tube M17 grid and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.
In a specific embodiment, current mirroring circuit includes PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M102, PMOS M13, PMOS M14；PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103, PMOS M13, PMOS M14 source electrode connection VDD；PMOS M9, PMOS M8, PMOS M101, PMOS Pipe M102, PMOS M103 grid are connected with NMOS tube M3 drain electrode；PMOS M13 and PMOS M14 grid and NMOS Pipe M15 drain electrode is connected；PMOS M9 drain electrodes are connected with PNP type triode Q0 emitter stage；PMOS M8 drain electrode and NMOS Pipe M3 drain electrode is connected；PMOS M101 drain electrode is connected with NMOS tube M111 drain electrode；PMOS M102 drain electrode and NMOS Pipe M112 drain electrode is connected；PMOS M102 drain electrode is connected with NMOS tube M112 drain electrode；PMOS M103 drain electrode with NMOS tube M122 drain electrode is connected；PMOS M13 drain electrode is connected with PNP type triode Q1 emitter stage；PMOS M14 leakage Pole is connected with NMOS tube M15 drain electrode；
PTAT voltage circuit include NMOS tube M111, NMOS tube M112, NMOS tube M121, NMOS tube M122, NMOS tube M3, NMOS tube M2；NMOS tube M111 drain electrode is connected to PMOS M101 drain electrode together with grid, NMOS tube M121 grid； NMOS tube M112 drain electrode is connected to PMOS M102 drain electrode together with grid, NMOS tube M122 grid；NMOS tube M112 Drain electrode PMOS M10m drain electrode is connected to together with grid, NMOS tube M122 grid；NMOS tube M111 source electrode with NMOS tube M121 drain electrode is connected；NMOS tube M112 source electrode is connected with NMOS tube M122 drain electrode；NMOS tube M112 source electrode Drain electrode with NMOS tube M122 is connected；NMOS tube M122 source electrode is connected to NMOS tube M121 drain electrode；NMOS tube M122 source Pole is connected to NMOS tube M121 drain electrode；NMOS tube M121 source electrode connection NMOS tube M2 drain electrode；NMOS tube M3 and NMOS tube M2 grid is connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode, NMOS Pipe M3 source electrode connects M2 drain electrode；NMOS tube M2 source electrode connection NMOS tube M1 drain electrode；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0；PNP type triode Q0 colelctor electrode, base stage connection ground；PNP type triode Q0 emitter stage connection PMOS M9 drain electrode；NMOS tube M3 and NMOS Pipe M2 grid is connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode； NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode；NMOS Pipe M1 source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1；The pole of positive-negative-positive three Pipe Q1 emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector；NMOS tube M15 and NMOS tube M16 grid connection PNP type triode Q1 emitter stage；NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connection NMOS tube M17 drain electrode；NMOS tube M17 grid and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.
Preferably, it is positive integer that PTAT voltage circuit, which includes m grades of automatic biasing stacked structures, m >=2, and m,；N >=3, and n is Positive integer.
By such scheme, the present invention be operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source at least have with Lower advantage：
The present invention is rational in infrastructure, and low in energy consumption, chip area is minimum shared by circuit, realizes in the case of low supply voltage, Stable output wide temperature range, high-accuracy voltage.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention, And can be practiced according to the content of specification, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after.
Brief description of the drawings
Fig. 1 is circuit diagram of the present invention using n grades of PTAT blocks；
Fig. 2 is the linearity compensation schematic diagram of band gap reference in the present invention；
Fig. 3 is that the automatic biasing in the present invention in PTAT block stacks (self-cascode) structure；
Fig. 4 is circuit diagram of the present invention using three-level PTAT block；
Fig. 5 is circuit diagram of the present invention using 6 grades of PTAT blocks；
Fig. 6 is the voltage accuracy analogous diagram of the present invention；
Fig. 7 is the bandgap voltage reference and input voltage graph of a relation of the present invention；
Fig. 8 is conventional low voltage band-gap reference circuit figure.
Embodiment
With reference to the accompanying drawings and examples, the embodiment to the present invention is described in further detail.Implement below Example is used to illustrate the present invention, but is not limited to the scope of the present invention.
It is of the present invention to be operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source referring to shown in Fig. 1 to 3, Including：Current mirroring circuit, produces the PTAT generation circuits of positive temperature coefficient voltage, and the CTAT for producing negative temperature coefficient voltage is produced Circuit, linear compensation circuit output offset, offset, positive temperature coefficient voltage and negative temperature coefficient voltage are done and, generation Reference voltage VREF；
Wherein, the current mirroring circuit includes PMOS M9, PMOS M8, PMOS M13, PMOS M14 and n PMOS, i.e. PMOS M101, PMOS M102 ... PMOSs M10n；PMOS M9, PMOS M8PMOS pipes M13, PMOS Pipe M14 and n PMOS source electrode connection VDD；PMOS M8 drain electrode connection PMOS M8 grid；PMOS M14's Drain electrode connection PMOS M14 grid；
PMOS M9, PMOS M8, PMOS M101, PMOS M102 ... PMOSs M10n grid and the first order are certainly The drain electrode for biasing the upper strata NMOS tube M3 of stacked structure is connected；PMOS M13, PMOS M14 grid and NMOS tube M15 leakage Extremely it is connected；PMOS M9 is connected with PNP type triode Q0 emitter stage；PMOS M101 drain electrode is stacked with second level automatic biasing The upper strata NMOS tube M111 of structure drain electrode is connected；PMOS M102 drain electrode and the upper strata of third level automatic biasing stacked structure NMOS tube M112 drain electrode is connected；... PMOS M10m drain electrode and the upper strata NMOS tube of n-th grade of automatic biasing stacked structure M11m drain electrode is connected；PMOS M10n drain electrode and the lower floor NMOS tube M12m of afterbody automatic biasing stacked structure drain electrode It is connected；PMOS M13 drain electrode is connected with PNP type triode Q1 emitter stage；PMOS M14 drain electrode is with NMOS tube M15's Drain electrode is connected；
PTAT generation circuits include m grade automatic biasing stacked structures, automatic biasing stacked structures at different levels include upper strata NMOS tube with Lower floor's NMOS tube, the source electrode of the upper strata NMOS tube of automatic biasing stacked structures at different levels is connected with the drain electrode of lower floor's NMOS tube；One-level is certainly Bias the drain electrode connection of the source electrode of lower floor's NMOS tube of stacked structure and lower floor's NMOS tube of previous stage automatic biasing stacked structure；The The upper strata NMOS tube M11m of m grades of automatic biasing stacked structures grid is connected to together with drain electrode, lower floor NMOS tube M12m grid PMOS M10n drain electrode；The upper strata NMOS tube M111 of second level automatic biasing stacked structure drain electrode and grid, lower floor's NMOS tube M121 grid all connects PMOS M101 drain electrode；... the upper strata NMOS tube M11m of m grades of automatic biasing stacked structures leakage Pole and grid, lower floor NMOS tube M12m grid all connect PMOS M10m drain electrode；First order automatic biasing stacked structure it is upper Layer NMOS tube M3 and lower floor NMOS tube M2 grid is connected to PNP type triode Q0 emitter stage together；First order automatic biasing heap The upper strata NMOS tube M3 of stack structure drain electrode connection PMOS M101 drain electrode；The lower floor NMOS of first order automatic biasing stacked structure Pipe M2 source electrode connection NMOS tube M1 drain electrode；M=n-1；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0；PNP type triode Q0 colelctor electrode, base stage connection ground；PNP type triode Q0 emitter stage connection PMOS M9 drain electrode；NMOS tube M3 and NMOS Pipe M2 grid is connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode； NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode；NMOS Pipe M1 source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1；The pole of positive-negative-positive three Pipe Q1 emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector；NMOS tube M15 and NMOS tube M16 grid connection PNP type triode Q1 emitter stage；NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connection NMOS tube M17 drain electrode；NMOS tube M17 grid and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.
It is positive integer that PTAT voltage circuit, which includes m grades of automatic biasing stacked structures, m >=2, and m,；N >=3, and n is positive integer.
In the present invention, NMOS tube M3, NMOS tube M2, PTAT was not only belonged to but also had belonged to CTAT, the two transistors are both to constitute PTAT pith, is the pith for constituting CTAT again, is multiplex circuit structure.
Subthreshold region high-precision low-power consumption low-voltage bandgap reference source is operated in described in a preferred embodiment of the present invention, with three It is shown in Figure 4 exemplified by the circuit diagram of level PTAT block：
Current mirroring circuit includes PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103, PMOS Pipe M13, PMOS M14；PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103, PMOS M13, PMOS M14 source electrode connection VDD；PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103, PMOS M13 grid is connected with NMOS tube M3 drain electrode；PMOS M13 and PMOS M14 grid and NMOS tube M15 leakage Extremely it is connected；PMOS M9 drain electrodes are connected with triode PNP type triode Q0 emitter stage；PMOS M8 drain electrode and NMOS tube M3 Drain electrode be connected；PMOS M101 drain electrode is connected with NMOS tube M111 drain electrode；PMOS M102 drain electrode and NMOS tube M112 drain electrode is connected；PMOS M103 drain electrode is connected with NMOS tube M122 drain electrode；PMOS M13 drain electrode and triode PNP type triode Q1 emitter stage is connected；PMOS M14 drain electrode is connected with NMOS tube M15 drain electrode；
PTAT voltage circuit include NMOS tube M112, NMOS tube M122, NMOS tube M111, NMOS tube M121, NMOS tube M3, NMOS tube M2；NMOS tube M112 grid is connected to PMOS M1102 drain electrode, NMOS tube together with NMOS tube M122 grid M112 source electrode is connected with NMOS tube M122 drain electrode, and NMOS tube M122 source electrode is connected to NMOS tube M121 drain electrode；NMOS Pipe M111 drain electrode is connected together to PMOS M101 drain electrode with grid, NMOS tube M121 grid；NMOS tube M111's Source electrode connection NMOS tube M121 drain electrode；NMOS tube M121 source electrode connection NMOS tube M2 drain electrode；NMOS tube M3 and NMOS tube M2 grid is connected to triode PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 leakage Pole, NMOS tube M3 source electrode connects M2 drain electrode；NMOS tube M2 source electrode connection NMOS tube M1 drain electrode；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, triode PNP type triode Q0；Triode PNP type triode Q0 colelctor electrode, base stage connection ground；Triode PNP type triode Q0 emitter stage connection PMOS M9 leakage Pole；NMOS tube M3 and NMOS tube M2 grid are connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode；NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS Pipe M2 source electrode；NMOS tube M1 source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, triode PNP type triode Q1；Three Pole pipe PNP type triode Q1 emitter stage connection PMOS M13 drain electrode, triode PNP type triode Q1 base stage and current collection Pole is grounded；NMOS tube M15 and NMOS tube M16 grid connecting triode PNP type triode Q1 emitter stage；NMOS tube M15's Drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connects Connect NMOS tube M17 drain electrode；NMOS tube M17 grid and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source electrode Ground connection.
The metal-oxide-semiconductor drain terminal current formula typically operated under weak anti-type state can be expressed as：
PTAT voltage module have NMOS tube M112, NMOS tube M122, NMOS tube M111, NMOS tube M121, NMOS tube M3, NMOS tube M2.It is main by self-cascode structure compositions, as shown in Figure 3.NMOS tube M112 and NMOS tube M122 in Fig. 4 It is exactly wherein one-level self-cascode.NMOS in structure is all in subthreshold region, the NMOS tube M112 on upper strata VDSMore than 3 times Thermal voltage, so the latter half in drain terminal current formula can be omitted approximately, the NMOS tube M122 of lower floor VDSLess than 3 times Thermal voltage, so the latter half in drain terminal current formula can not be omitted, so as to obtain lower floor metal-oxide-semiconductor M122 source and drain Voltage：
A is a constant more than 1 in above formula, it is clear that the source-drain voltage and temperature positive correlation.When after multiple stacking The direct proportion coefficient value of PTAT voltage module can be accordingly increased.
CTAT voltage module is by PMOS M9, PMOS M8, NMOS tube M3, NMOS tube M2, NMOS tube M1, the pole of positive-negative-positive three Pipe Q0 is constituted, and wherein PMOS M8 and PMOS M9 constitute a current mirror, and NMOS tube M3, NMOS tube M2, NMOS tube M1 locate In subthreshold region, PNP type triode short circuit is equivalent to diode and used, and NMOS tube M3 breadth length ratio is much larger than NMOS in the structure shown here Pipe M2, NMOS tube M1 breadth length ratio.NMOS tube M1 breadth length ratio is identical with NMOS tube M2 breadth length ratio.Obviously, in the structure shown here Due to the influence of current mirror, the electric current of two-way defers to the proportionate relationship between PMOS M9 and PMOS M8 breadth length ratio.Generally The voltage equation of diode can be expressed as：
So as to also can just sort out NMOS tube M1 source-drain voltage：
Wherein b is a constant, and c is a number related to PMOS M9 and PMOS M8 breadth length ratio ratio, But the technological parameter related to temperature is there is in c, although varied less in ln functions, but after required precision is very high Influence can be produced on precision.
Linearity compensation module is by PMOS M13, PMOS M14, NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP Type triode Q1 is constituted.Wherein PMOS M13 and PMOS M14 constitute a current mirror, NMOS tube M15, NMOS tube M16, NMOS tube M17 is all in subthreshold region, and PNP type triode short circuit is equivalent to diode and used, in the structure shown here NMOS tube M15 width Long ratio is much larger than NMOS tube M16, NMOS tube M17 breadth length ratio.NMOS tube M16 breadth length ratio and NMOS tube M17 breadth length ratio phase Together.The source-drain voltage formula for the M17 that the obvious structure is finally produced is identical with CTAT voltage module, but now when adjustment electric current Proportionate relationship between mirror breadth length ratio causes the ratio of linearity compensation module to be more than the ratio of CTAT generation modules so that NMOS Pipe M17 and NMOS tube M1 make the difference, then can just offset the technological parameter related to temperature in ln functions, now ln functions In value be less than 1 due to the proportionate relationship of current mirror before so that the Successful construct splendid CTAT voltage of one linearity.
Deformed on the basis of above-described embodiment, can be by the way that PTAT connected series be increased into higher defeated to obtain Go out reference voltage and bigger temperature range.Shown in Figure 5, PTAT block is 6 level structures.In addition, PTAT block can be with For 4,5,7,8 etc., any hierarchical organization, particular circuit configurations those skilled in the art can reasonable speculation obtain, herein no longer Repeat.
Fig. 6 is the voltage accuracy analogous diagram of 6 level structure of the invention, it can be seen that the present invention has very wide temperature Spend scope (- 100 DEG C to 150 DEG C) and very high precision (about 10ppm)；Fig. 7 is bandgap voltage reference and the input of the present invention Voltage relationship figure, can as seen from the figure, and when input voltage is more than 1V, output bandgap voltage reference keeps stablizing constant.
Described above is only the preferred embodiment of the present invention, is not intended to limit the invention, it is noted that for this skill For the those of ordinary skill in art field, without departing from the technical principles of the invention, can also make it is some improvement and Modification, these improvement and modification also should be regarded as protection scope of the present invention.

Claims (3)

1. one kind is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, it is characterised in that including：Current mirror electricity Road, produces the PTAT generation circuits of positive temperature coefficient voltage, produces the CTAT generation circuits of negative temperature coefficient voltage, linear compensation Circuit output offset, offset, positive temperature coefficient voltage and negative temperature coefficient voltage are done and, produce reference voltage VREF；
Wherein, the current mirroring circuit includes PMOS M9, PMOS M8, PMOS M13, PMOS M14 and n PMOS Pipe, i.e. PMOS M101, PMOS M102 ... PMOSs M10n；PMOS M9, PMOS M8PMOS pipes M13, PMOS M14 And the source electrode connection VDD of n PMOS；PMOS M8 drain electrode connection PMOS M8 grid；PMOS M14 drain electrode connects Connect PMOS M14 grid；
PMOS M9, PMOS M8, PMOS M101, PMOS M102 ... PMOSs M10n grid and first order automatic biasing The upper strata NMOS tube M3 of stacked structure drain electrode is connected；The drain electrode phase of PMOS M13, PMOS M14 grid and NMOS tube M15 Even；PMOS M9 is connected with PNP type triode Q0 emitter stage；PMOS M101 drain electrode and second level automatic biasing stacked structure Upper strata NMOS tube M111 drain electrode be connected；PMOS M102 drain electrode and the upper strata NMOS tube of third level automatic biasing stacked structure M112 drain electrode is connected；... PMOS M10m drain electrode and the upper strata NMOS tube M11m of n-th grade of automatic biasing stacked structure leakage Extremely it is connected；PMOS M10n drain electrode is connected with the lower floor NMOS tube M12m of afterbody automatic biasing stacked structure drain electrode； PMOS M13 drain electrode is connected with PNP type triode Q1 emitter stage；PMOS M14 drain electrode and NMOS tube M15 drain electrode phase Even；
PTAT generation circuits include m grades of automatic biasing stacked structures, and automatic biasing stacked structures at different levels include upper strata NMOS tube and lower floor NMOS tube, the source electrode of the upper strata NMOS tube of automatic biasing stacked structures at different levels is connected with the drain electrode of lower floor's NMOS tube；One-level automatic biasing The drain electrode connection of the source electrode of lower floor's NMOS tube of stacked structure and lower floor's NMOS tube of previous stage automatic biasing stacked structure；M grades The upper strata NMOS tube M11m of automatic biasing stacked structure grid is connected to PMOS together with drain electrode, lower floor NMOS tube M12m grid Pipe M10n drain electrode；The upper strata NMOS tube M111 of second level automatic biasing stacked structure drain electrode and grid, lower floor NMOS tube M121 Grid all connect PMOS M101 drain electrode；... the upper strata NMOS tube M11m of m grades of automatic biasing stacked structures drain electrode with Grid, lower floor NMOS tube M12m grid all connect PMOS M10m drain electrode；The upper strata of first order automatic biasing stacked structure NMOS tube M3 and lower floor NMOS tube M2 grid are connected to PNP type triode Q0 emitter stage together；First order automatic biasing is stacked The upper strata NMOS tube M3 of structure drain electrode connection PMOS M101 drain electrode；Lower floor's NMOS tube of first order automatic biasing stacked structure M2 source electrode connection NMOS tube M1 drain electrode；M=n-1；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0；PNP type triode Q0's Colelctor electrode, base stage connection ground；PNP type triode Q0 emitter stage connection PMOS M9 drain electrode；NMOS tube M3 and NMOS tube M2 Grid be connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode；NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode；NMOS tube M1's Source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1；PNP type triode Q1 Emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector；NMOS tube M15 and NMOS tube M16 grid connection PNP type triode Q1 emitter stage；NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connection NMOS tube M17 drain electrode；NMOS tube M17 grid Pole and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.
2. according to claim 1 be operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, it is characterised in that Current mirroring circuit include PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M102, PMOS M13, PMOS M14；PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103, PMOS M13, PMOS M14 source electrode connection VDD；PMOS M9, PMOS M8, PMOS M101, PMOS M102, PMOS M103 grid with NMOS tube M3 drain electrode is connected；PMOS M13 and PMOS M14 grid are connected with NMOS tube M15 drain electrode；PMOS M9 leaks Pole is connected with PNP type triode Q0 emitter stage；PMOS M8 drain electrode is connected with NMOS tube M3 drain electrode；PMOS M101's Drain electrode is connected with NMOS tube M111 drain electrode；PMOS M102 drain electrode is connected with NMOS tube M112 drain electrode；PMOS M102 Drain electrode be connected with NMOS tube M112 drain electrode；PMOS M103 drain electrode is connected with NMOS tube M122 drain electrode；PMOS M13 Drain electrode be connected with PNP type triode Q1 emitter stage；PMOS M14 drain electrode is connected with NMOS tube M15 drain electrode；
PTAT voltage circuit includes NMOS tube M111, NMOS tube M112, NMOS tube M121, NMOS tube M122, NMOS tube M3, NMOS Pipe M2；NMOS tube M111 drain electrode is connected to PMOS M101 drain electrode together with grid, NMOS tube M121 grid；NMOS tube M112 drain electrode is connected to PMOS M102 drain electrode together with grid, NMOS tube M122 grid；NMOS tube M112 drain electrode PMOS M10m drain electrode is connected to together with grid, NMOS tube M122 grid；NMOS tube M111 source electrode and NMOS tube M121 drain electrode is connected；NMOS tube M112 source electrode is connected with NMOS tube M122 drain electrode；NMOS tube M112 source electrode and NMOS Pipe M122 drain electrode is connected；NMOS tube M122 source electrode is connected to NMOS tube M121 drain electrode；NMOS tube M122 source electrode connection To NMOS tube M121 drain electrode；NMOS tube M121 source electrode connection NMOS tube M2 drain electrode；NMOS tube M3 and NMOS tube M2 grid Pole is connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode, NMOS tube M3's Source electrode connects M2 drain electrode；NMOS tube M2 source electrode connection NMOS tube M1 drain electrode；
CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0；PNP type triode Q0's Colelctor electrode, base stage connection ground；PNP type triode Q0 emitter stage connection PMOS M9 drain electrode；NMOS tube M3 and NMOS tube M2 Grid be connected to PNP type triode Q0 emitter stage together；NMOS tube M3 drain electrode connection PMOS M8 drain electrode；NMOS tube M3 source electrode connection NMOS tube M2 drain electrode；NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode；NMOS tube M1's Source ground；
Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1；PNP type triode Q1 Emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector；NMOS tube M15 and NMOS tube M16 grid connection PNP type triode Q1 emitter stage；NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tube M15 source electrode connection NMOS tube M16 drain electrode；NMOS tube M16 source electrode connection NMOS tube M17 drain electrode；NMOS tube M17 grid Pole and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.
3. according to claim 2 be operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, it is characterised in that It is positive integer that PTAT voltage circuit, which includes m grades of automatic biasing stacked structures, m >=2, and m,；N >=3, and n is positive integer.
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Application publication date: 20170804