CN114356014A - Low-voltage reference voltage generating circuit and chip - Google Patents
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Abstract
The invention discloses a low-voltage reference voltage generating circuit and a chip, wherein the circuit comprises a reference current source module, a buffer module and a high-order temperature compensation module, wherein the reference current source module is used for respectively providing zero-temperature current for the buffer module and the high-order temperature compensation module and providing negative temperature characteristic voltage for the buffer module; the buffer module is used for generating an offset voltage with positive temperature characteristics according to the zero-temperature current and superposing the offset voltage and the negative temperature characteristic voltage to output a first band gap reference voltage; the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current so as to enable the buffer module to output the low-temperature floating bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and the circuit design complexity and the power consumption can be reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-voltage reference voltage generating circuit and a chip.
Background
Band gap reference voltage circuit can provide a and technology, voltage and temperature irrelevant reference voltage, thereby by the wide application in various analog circuit, along with the rapid development of industrial field high accuracy data acquisition system, the sampling precision of chip and the sampling precision seriously rely on the high accuracy reference source on the chip along with the change of temperature among the acquisition system, in order to guarantee that the chip is at wide temperature range during operation, absolute sampling precision does not change along with the temperature, need urgently to develop a low temperature drift, the high accuracy band gap reference voltage source of wide warm area work, and simultaneously, along with the constantly shrinking of technology node, chip operating voltage also reduces gradually, higher requirement has also been proposed to the minimum operating voltage of chip reference source.
However, in the existing solutions of related bandgap reference sources, a high-order temperature compensation loop is usually added to a conventional bandgap reference source circuit to implement high-order temperature compensation of bandgap reference voltage, so as to improve the precision of the reference source.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, a first objective of the present invention is to provide a low voltage reference voltage generating circuit, which not only can output a low temperature floating bandgap reference voltage, but also can make a low operating voltage in a wide operating voltage range, and at the same time can reduce the complexity of circuit design and power consumption.
A second objective of the present invention is to provide a chip.
In order to achieve the above object, a first embodiment of the present invention provides a low voltage reference voltage generating circuit, which includes a reference current source module, a buffer module and a high-order temperature compensation module, wherein the reference current source module is configured to provide zero temperature current to the buffer module and the high-order temperature compensation module, respectively, and provide a negative temperature characteristic voltage to the buffer module; the buffer module is used for generating an offset voltage with positive temperature characteristics according to the zero-temperature current and superposing the offset voltage and the negative temperature characteristic voltage to output a first band gap reference voltage; the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current so as to enable the buffer module to output the low-temperature floating bandgap reference voltage.
According to the low-voltage reference voltage generating circuit provided by the embodiment of the invention, the reference current source module is used for respectively providing zero-temperature current to the buffer module and the high-order temperature compensation module and providing negative temperature characteristic voltage to the buffer module, the buffer module generates offset voltage with positive temperature characteristic according to the zero-temperature current and superposes the offset voltage and the negative temperature characteristic voltage provided by the reference current source module to output first bandgap reference voltage, and the high-order temperature compensation module is used for carrying out high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current so as to enable the buffer module to output low-temperature floating bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and the circuit design complexity and the power consumption can be reduced.
According to one embodiment of the invention, the buffer module comprises at least one buffer.
According to one embodiment of the invention, when the buffer is multiple, the multiple buffers are cascaded.
According to one embodiment of the present invention, a buffer includes: the source electrode of the first transistor is connected to a preset power supply, and the grid electrode of the first transistor is connected with the reference current source module; the source electrode of the second transistor is connected with the source electrode of the third transistor and then connected to the drain electrode of the first transistor, the grid electrode of the second transistor is connected with the reference current source module, and the grid electrode of the third transistor is connected with the drain electrode and then used as the cascade output end of the buffer; a grid electrode of the fourth transistor is connected with the drain electrode of the second transistor after being connected with the drain electrode, and a source electrode of the fourth transistor is grounded; and the grid electrode of the fifth transistor is connected with the grid electrode of the fourth transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the third transistor, and the source electrode of the fifth transistor is grounded.
According to an embodiment of the invention, the first transistor, the second transistor and the third transistor are all PMOS transistors, and the fourth transistor and the fifth transistor are all NMOS transistors.
According to one embodiment of the present invention, the second transistor, the third transistor, the fourth transistor, and the fifth transistor operate in a sub-threshold region.
According to one embodiment of the present invention, the size ratio of the second transistor to the third transistor is 1: m, the size ratio of the fourth transistor to the fifth transistor is P: 1, wherein M and P are positive integers greater than 1.
According to one embodiment of the present invention, a reference current source module includes: the source electrode of the sixth transistor is connected with the source electrode of the seventh transistor and then connected to a preset power supply, and the grid electrode of the sixth transistor is connected with the grid electrode of the seventh transistor and provided with a first node; an emitter of the eighth transistor is connected with a drain of the sixth transistor and is provided with a second node, and a base of the eighth transistor is connected with a collector and then is grounded; a first resistor, one end of which is connected with the drain of the seventh transistor and is provided with a third node; an emitter of the ninth transistor is connected with the other end of the first resistor, and a base of the ninth transistor is connected with a collector and then grounded; the positive input end of the error amplifier is connected with the third node, the negative input end of the error amplifier is connected with the second node, and the output end of the error amplifier is connected with the first node and then connected to the grid electrode of the first transistor; one end of the second resistor is connected with the negative input end of the error amplifier; one end of the third resistor is connected with the positive input end of the error amplifier, the other end of the third resistor is connected with the other end of the second resistor and is provided with a fourth node, and the fourth node is connected to the grid electrode of the second transistor; and one end of the fourth resistor is connected with the fourth node, and the other end of the fourth resistor is grounded.
According to one embodiment of the present invention, a ratio of emitter areas of the eighth transistor and the ninth transistor is 1: and N, wherein N is an integer greater than 1.
According to one embodiment of the invention, the higher order temperature compensation module comprises: a tenth transistor, a source of which is connected to a preset power supply, and a gate of which is connected to an output terminal of the error amplifier; an eleventh transistor, an emitter of which is connected to a drain of the tenth transistor and has a fifth node, and a collector of which is connected to a base and then grounded; one end of the fifth resistor is connected with the fifth node, and the other end of the fifth resistor is connected with the second node; and one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the third node.
According to an embodiment of the present invention, the eighth transistor, the ninth transistor, and the eleventh transistor are all bipolar transistors.
According to an embodiment of the invention, the sixth transistor, the seventh transistor and the tenth transistor are all PMOS transistors and are equal in size.
According to an embodiment of the present invention, the final low temperature floating bandgap reference voltage outputted by the buffer module is determined according to an emitter-base voltage of the eighth transistor, an emitter-base voltage of the eleventh transistor, a resistance value of the second resistor, a resistance value of the fourth resistor, a resistance value of the fifth resistor, and a difference between a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
In order to achieve the above object, a second embodiment of the present invention provides a chip, which includes a low voltage reference voltage generating circuit as in the first embodiment.
According to the chip provided by the embodiment of the invention, the low-voltage reference voltage generating circuit can not only realize the output of low-temperature floating band gap reference voltage, but also enable the low working voltage to be in a wide working voltage range, and simultaneously can reduce the circuit design complexity and power consumption.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a low voltage reference voltage generating circuit according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a low voltage reference voltage generating circuit according to a second embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The low voltage reference voltage generating circuit and the chip according to the embodiments of the present invention will be described with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a low voltage reference voltage generating circuit according to a first embodiment of the present invention. As shown in fig. 1, the low voltage reference voltage generating circuit includes a reference current source module 100, a buffer module 200, and a high-order temperature compensation module 300.
The reference current source module 100 is configured to provide zero temperature current to the buffer module 200 and the high-order temperature compensation module 300, and provide negative temperature characteristic voltage to the buffer module 200; the buffer module 200 is configured to generate an offset voltage with a positive temperature characteristic according to the zero-temperature current, and superimpose the offset voltage and a negative temperature characteristic voltage to output a first bandgap reference voltage; the high-order temperature compensation module 300 is configured to perform high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module 300 outputs a low-temperature floating bandgap reference voltage.
Specifically, when the low voltage reference voltage generating circuit works, the reference current source module 100 may generate a current that does not change with temperature, i.e. a zero temperature current, and may form a voltage having a negative temperature characteristic, the buffer module 200 is connected to the reference current source module 100 and is configured to receive the zero temperature current and the voltage having the negative temperature characteristic generated by the reference current source module 100, and the buffer module 200 may form an offset voltage having a positive temperature characteristic according to the received zero temperature current, and superimpose the offset voltage having the positive temperature characteristic with the voltage having the negative temperature characteristic directly obtained from the reference current source module 100 to form a first bandgap reference voltage, and since the first bandgap reference voltage is formed by superimposing the offset voltage having the positive temperature characteristic and the voltage having the negative temperature characteristic, a bandgap reference voltage having the zero temperature characteristic is finally formed, therefore, the application of the high-order temperature compensation module 300 in a wide working voltage range can be realized, the high-order temperature compensation module 300 is respectively connected with the reference current source module 100 and the buffer module 200, the high-order temperature compensation module 300 can perform high-order temperature compensation on the first band gap reference voltage formed by the buffer module 200 according to the zero temperature current obtained from the reference current source module 100, the accurate compensation of the band gap reference voltage is realized, and finally the buffer module 300 outputs the band gap reference voltage with low temperature drift.
According to the low-voltage reference voltage generating circuit provided by the embodiment of the invention, the reference current source module is used for respectively providing zero-temperature current to the buffer module and the high-order temperature compensation module and providing negative temperature characteristic voltage to the buffer module, the buffer module generates offset voltage with positive temperature characteristic according to the zero-temperature current and superposes the offset voltage and the negative temperature characteristic voltage provided by the reference current source module to output first bandgap reference voltage, and the high-order temperature compensation module is used for carrying out high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current so as to enable the buffer module to output low-temperature floating bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and the circuit design complexity and the power consumption can be reduced.
In some embodiments, buffer module 200 includes at least one buffer; when there are multiple buffers, the multiple buffers are cascaded, and the number of the buffers can be set according to actual requirements, for example, as shown in fig. 2, the buffer module 200 includes two buffers.
Further, with continued reference to fig. 2, each buffer includes: a first transistor (e.g., M1), a second transistor (e.g., M2), a third transistor (e.g., M3), a fourth transistor (e.g., M4), and a fifth transistor (e.g., M5), wherein a source of the first transistor (e.g., M1) is connected to a preset power VDD, and a gate of the first transistor (e.g., M1) is connected to the reference current source module 100; the source of the second transistor (e.g., M2) is connected to the source of the third transistor (e.g., M3) and then connected to the drain of the first transistor (e.g., M1), the gate of the second transistor (e.g., M2) is connected to the reference current source module 100, and the gate and the drain of the third transistor (e.g., M3) are connected and then used as the cascade output terminal of the buffer; the grid electrode and the drain electrode of the fourth transistor (such as M4) are connected and then connected to the drain electrode of the second transistor (such as M2), and the source electrode of the fourth transistor (such as M4) is grounded GND; the gate of the fifth transistor (e.g., M5) is connected to the gate of the fourth transistor (e.g., M4), the drain of the fifth transistor (e.g., M5) is connected to the drain of the third transistor (e.g., M3), and the source of the fifth transistor (e.g., M5) is connected to GND.
Specifically, taking the buffer module 200 as an example including two buffers, referring to fig. 2, the two buffers are a first buffer and a second buffer, the two buffers are connected in cascade, the sources of the transistor M1 in the first buffer and the transistor M1 ' in the second buffer are both connected to a preset power VDD, the gates of the transistor M1 and the transistor M1 ' are connected to the reference current source module 100, the sources of the transistor M2 and the transistor M3 in the first buffer are connected to the drain of the transistor M1, the gate of the transistor M2 is connected to the reference current source module 100, the gate of the transistor M3 is connected to the drain of the transistor M2 ' in the second buffer, the gate and the drain of the transistor M4 in the first buffer are connected to the drain of the transistor M2, the source of the transistor M4 is grounded, the gate of the transistor M5 in the first buffer is connected to the gate of the transistor M4, the drain electrode of the transistor M5 is connected with the drain electrode of the transistor M3, and the source electrode of the transistor M5 is grounded to GND; the sources of the transistor M2 'and the transistor M3' in the second buffer are connected and then connected to the drain of the transistor M1 ', the gate and the drain of the transistor M3' are connected and then serve as the cascade output end of the buffer, the gate and the drain of the transistor M4 'in the second buffer are connected and then connected to the drain of the transistor M2', the source of the transistor M4 'is grounded GND, the gate of the transistor M5' in the second buffer is connected to the gate of the transistor M4 ', the drain of the transistor M5' is connected to the drain of the transistor M3 ', and the source of the transistor M5' is grounded GND.
In some embodiments, the first transistor (e.g., M1), the second transistor (e.g., M2), and the third transistor (e.g., M3) are PMOS transistors, and the fourth transistor (e.g., M4) and the fifth transistor (e.g., M5) are NMOS transistors. That is, as shown in fig. 2, the transistors M1, M2 and M3 in the first buffer are all PMOS transistors, and the transistors M4 and M5 are all NMOS transistors; the transistors M1 ', M2 ' and M3 ' in the second buffer are all PMOS tubes, and the transistors M4 ' and M5 ' are all NMOS tubes.
In some embodiments, the second transistor (e.g., M2), the third transistor (e.g., M3), the fourth transistor (e.g., M4), and the fifth transistor (e.g., M5) operate in the sub-threshold region. That is, as shown in fig. 2, the transistors M2, M3, M4, and M5 in the first buffer operate in the subthreshold region; the second buffer, M2 ', M3', M4 'and M5', operates in the subthreshold region.
In some embodiments, the size ratio of the second transistor (e.g., M2) to the third transistor (e.g., M3) is 1: m, the size ratio of the fourth transistor (e.g., M4) to the fifth transistor (e.g., M5) is P: 1, wherein M and P are positive integers greater than 1. That is, as shown in fig. 2, the size ratio of the transistor M2 to the transistor M3 in the first buffer is 1: m, the size ratio of the transistor M4 to the transistor M5 is P: 1; the size ratio of the transistor M2 'to the transistor M3' in the second buffer is 1: m, the size ratio of the transistor M4 'to the transistor M5' is P: 1.
specifically, when the buffer module 200 operates, the transistor M1 in the first buffer and the transistor M1' in the second buffer are controlled by the reference current source module 100 and flow the same current, the transistors M2, M3, M4 and M5 in the first buffer operate in the sub-threshold region, and by utilizing the characteristic that the transistors operate in the sub-threshold region, by designing the size ratio of the transistors, for example, the size ratio of the transistor M2 to the transistor M3 in the first buffer is set to 1: m, the size ratio of the transistor M4 to the transistor M5 is P: 1, an offset voltage with positive temperature characteristic can be generated; the structure of the second buffer is the same as that of the first buffer, the transistors M2 ', M3 ', M4 ' and M5 ' in the second buffer also work in the subthreshold region, so that an offset voltage with a positive temperature characteristic can be generated, the gate of the transistor M2 ' in the second buffer is connected with the gate of the transistor M3 in the first buffer, so as to realize the cascade connection of the buffers, and finally, the negative temperature characteristic voltage formed by the reference current source module 100 is superposed according to the offset voltage with the positive temperature characteristic formed by the first buffer and the second buffer, so that a bandgap reference voltage with a zero temperature characteristic, namely a first bandgap reference voltage, is obtained.
In some embodiments, as shown in fig. 2, the reference current source module 100 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first resistor R1, a ninth transistor M9, an error amplifier a, a second resistor R2, a third resistor R3, and a fourth resistor R4.
A source of the sixth transistor M6 is connected to a source of the seventh transistor M7 and then to the preset power VDD, and a gate of the sixth transistor M6 is connected to a gate of the seventh transistor M7 and has a first node; an emitter of the eighth transistor M8 is connected to a drain of the sixth transistor M6 and has a second node, and a base of the eighth transistor M8 is connected to a collector and then grounded to GND; one end of the first resistor R1 is connected to the drain of the seventh transistor M7 and has a third node; an emitter of the ninth transistor M9 is connected with the other end of the first resistor R1, and a base of the ninth transistor M9 is connected with a collector and then grounded to GND; the positive input end of the error amplifier A is connected with the third node, the negative input end of the error amplifier A is connected with the second node, and the output end of the error amplifier A is connected with the first node and then connected to the grid electrode of the first transistor (such as M1); one end of the second resistor R2 is connected with the negative input end of the error amplifier A; one end of the third resistor R3 is connected to the positive input terminal of the error amplifier a, the other end of the third resistor R3 is connected to the other end of the second resistor R2 and has a fourth node, and the fourth node is connected to the gate of the second transistor (e.g., M2); one end of the fourth resistor R4 is connected to the fourth node, and the other end of the fourth resistor R4 is grounded to GND.
Specifically, the output terminal of the operational amplifier a is connected to the sixth transistor M6 and the seventh transistor M7, respectively, the sixth transistor M6 and the seventh transistor M7 are both controlled by the operational amplifier a, and the magnitude of the generated current is proportional to the size of the transistor, the eighth transistor M8 and the ninth transistor M9 generate a current proportional to the temperature, i.e., a positive temperature current, and transmit the current to the first resistor R1, while the second resistor R2, the third resistor R3 and the fourth resistor R4 generate a negative temperature current, and the current in the seventh transistor M7 is the sum of the currents flowing through the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, so that by adjusting the proportions of the first resistor R1 and the second resistor R2, the third resistor R3 and the fourth resistor R4, a first-order zero temperature current can be obtained and transmitted to the buffer module 200 and the temperature compensation module 300 respectively.
In some embodiments, the ratio of the emitter areas of the eighth transistor M8 to the ninth transistor M9 is 1: and N, wherein N is an integer greater than 1. That is, the ratio of the saturation currents of the eighth transistor M8 and the ninth transistor M9 is 1: and N is added.
In some embodiments, as shown in fig. 2, the higher order temperature compensation module 300 includes: a tenth transistor M10, an eleventh transistor M11, a fifth resistor R5, and a sixth resistor R6.
Wherein, the source of the tenth transistor M10 is connected to the preset power supply VDD, and the gate of the tenth transistor M10 is connected to the output terminal of the error amplifier a; an emitter of the eleventh transistor M11 is connected to a drain of the tenth transistor M10 and has a fifth node, and a collector of the eleventh transistor M11 is connected to a base and then grounded to GND; one end of a fifth resistor R5 is connected with the fifth node, and the other end of the fifth resistor R5 is connected with the second node; one end of the sixth resistor R6 is connected to the fifth node, and the other end of the sixth resistor R6 is connected to the third node.
Specifically, the output terminal of the operational amplifier a is connected to the tenth transistor M10, the tenth transistor M10 is controlled by the operational amplifier a, so that the current in the seventh transistor M7 can be mirrored to the tenth transistor M10, the tenth transistor M10 can provide a zero temperature coefficient current to the eleventh transistor M11, the connection of the emitters of the eighth transistor M8 and the ninth transistor M9 to the emitter of the eleventh transistor M11 is realized through the fifth resistor R5 and the sixth resistor R6, respectively, and the high-order temperature compensation of the bandgap reference voltage is realized based on the difference between the positive temperature coefficient current in the eighth transistor M8 and the zero temperature coefficient current 11 in the ninth transistor M9 and the zero temperature coefficient current in the eleventh transistor M11.
In some embodiments, the eighth transistor M8, the ninth transistor M9, and the eleventh transistor M11 are all bipolar transistors.
In some embodiments, the sixth transistor M6, the seventh transistor M7, and the tenth transistor M10 are all PMOS transistors and are equal in size.
In some embodiments, the final low temperature floating bandgap reference voltage output by the buffer module 200 is determined according to the emitter-base voltage of the eighth transistor M8, the emitter-base voltage of the eleventh transistor M11, the resistance value of the second resistor R2, the resistance value of the fourth resistor R4, the resistance value of the fifth resistor R5, and the difference between the gate-source voltage of the third transistor (e.g., M3) and the gate-source voltage of the fourth transistor (e.g., M4).
As a specific example, as shown in fig. 2, assuming that the gain of the operational amplifier a is large enough and the input impedance is infinite, the voltages of the positive input terminal and the negative input terminal of the operational amplifier a are equal, neglecting mismatches in the circuit, such as mismatch between resistors, mismatch between transistors, and mismatch between bipolar transistors, assuming that the emitter-base voltage of the eighth transistor M8 is VEB1The emitter-base voltage of the ninth transistor M9 is VEB2The emitter-base voltage of the eleventh crystal M11 is VEB3The relation between the collector current of a bipolar transistor and its emitter-base voltage is:
wherein, ICIs the collector current of a bipolar transistor, ISIs the saturation current of a bipolar transistor, VTIs a thermal voltage, VTKT/q, q is the electronic charge, VEBIs the emitter-base voltage of the bipolar transistor, K is the boltzmann constant, and T is the absolute temperature.
The current in a bipolar transistor is:
wherein, IQFor bipolar transistor current, IEFor bipolar transistor emitter current, IBIs a base current of a bipolar transistor, betaFIs the current amplification factor.
The emitter-base voltage of the bipolar transistor can thus be deduced to be:
the current for a transistor operating in the subthreshold region is:
wherein, IdsIs the drain-source voltage of the transistor, ID0Is the saturation current of the drain of the transistor,
the n-sub-threshold ramp factor, which is the width-to-length ratio of the transistor, is a process-dependent constant, typically 1-1.5, VGSK is the boltzmann constant, T is the absolute temperature, and q is the electronic charge.
Neglecting the channel length effect of the transistors, in the present application, the size ratio of the transistor M2 to the transistor M3 in the first buffer is 1: m, the size ratio of the transistor M4 to the transistor M5 is P: combining the above formula, the offset voltage with positive temperature characteristic formed by the first buffer can be obtained:
ΔVGS＝VGS1-VGS2＝nVTln[P×M]
wherein, is Δ VGSOffset voltage, V, of positive temperature characteristicGS1Is the gate-source voltage, V, of the third transistor M3GS2Is the gate-source voltage of the fourth transistor M4. It should be noted that the offset voltage of the positive temperature characteristic formed by the second buffer is the same as the offset voltage of the positive temperature characteristic formed by the second buffer.
Superposing the offset voltage with positive temperature characteristic and the voltage with negative temperature characteristic formed by the two buffers to obtain a first band gap reference voltage:
wherein, VEB1Is the emitter-base voltage of the eighth transistor M8, R2 is the second resistor, and R4 is the fourth resistor.
Since the sixth transistor M6, the seventh transistor M7, and the tenth transistor M10 are PMOS transistors with equal sizes, the currents of the three transistors are also equal, and the current I of the eighth transistor M8 is equalM8And a ninth transistor M9 current IM9For positive temperature current, the current I in the second resistor R2R2For negative temperature current, by adjusting the size of the second resistor R2, a current weakly correlated with temperature can be obtained:
wherein, IM6The sixth transistor M6 has a current, IM7The seventh transistor M7 current, IM10The tenth transistor M10 has a current, VEB1Is the emitter-base voltage, V, of the eighth transistor M8EB2Is the emitter-base voltage of the ninth transistor M9, R1 is a first resistor, R2 is a second resistor, and R4 is a fourth resistor.
Carrying out high-order temperature compensation on the first band gap reference voltage according to the zero-temperature current to finally obtain a low-temperature drift band gap reference voltage:
wherein, VEB1Is the emitter-base voltage, V, of the eighth transistor M8EB3Is the emitter-base voltage of the eleventh transistor M11, R2 is the second resistor, R4 is the fourth resistor, R4 is the fifth resistor, Δ VGSAn offset voltage with positive temperature characteristics.
In summary, according to the low voltage reference voltage generating circuit in the embodiment of the invention, the reference current source module provides zero temperature current to the buffer module and the high-order temperature compensation module, respectively, and provides negative temperature characteristic voltage to the buffer module, the buffer module generates an offset voltage with positive temperature characteristic according to the zero temperature current, and superimposes the offset voltage and the negative temperature characteristic voltage provided by the reference current source module to output the first bandgap reference voltage, and the high-order temperature compensation module performs high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module outputs the low-temperature floating bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and the circuit design complexity and the power consumption can be reduced.
The embodiment of the invention also provides a chip which comprises the low-voltage reference voltage generating circuit.
In this application, the chip may be an ADC chip, or may be a reference voltage source chip, a switching power supply chip, or other chips that can generate a reference voltage, and is not limited herein.
According to the chip provided by the embodiment of the invention, the low-voltage reference voltage generating circuit can not only realize the output of low-temperature floating band gap reference voltage, but also enable the low working voltage to be in a wide working voltage range, and simultaneously can reduce the circuit design complexity and power consumption.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (14)
1. A low voltage reference voltage generating circuit comprises a reference current source module, a buffer module and a high-order temperature compensation module,
the reference current source module is used for respectively providing zero-temperature current to the buffer module and the high-order temperature compensation module and providing negative temperature characteristic voltage to the buffer module;
the buffer module is used for generating an offset voltage with positive temperature characteristics according to the zero-temperature current and superposing the offset voltage and the negative-temperature characteristic voltage to output a first band gap reference voltage;
the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current so as to enable the buffer module to output a low-temperature floating bandgap reference voltage.
2. The low voltage reference voltage generating circuit according to claim 1, wherein said buffer module comprises at least one buffer.
3. The low voltage reference voltage generating circuit according to claim 2, wherein when said buffer is plural, a plurality of said buffers are cascaded.
4. The low voltage reference voltage generating circuit according to claim 2 or 3, wherein the buffer comprises:
the source electrode of the first transistor is connected to a preset power supply, and the grid electrode of the first transistor is connected with the reference current source module;
the source electrode of the second transistor is connected with the source electrode of the third transistor and then connected to the drain electrode of the first transistor, the grid electrode of the second transistor is connected with the reference current source module, and the grid electrode of the third transistor is connected with the drain electrode and then used as the cascade output end of the buffer;
a gate and a drain of the fourth transistor are connected and then connected to the drain of the second transistor, and a source of the fourth transistor is grounded;
a fifth transistor, a gate of the fifth transistor is connected to a gate of the fourth transistor, a drain of the fifth transistor is connected to a drain of the third transistor, and a source of the fifth transistor is grounded.
5. The low voltage reference voltage generating circuit according to claim 4, wherein said first transistor, said second transistor and said third transistor are all PMOS transistors, and said fourth transistor and said fifth transistor are all NMOS transistors.
6. The low voltage reference voltage generating circuit according to claim 5, wherein the second transistor, the third transistor, the fourth transistor and the fifth transistor operate in a sub-threshold region.
7. The low voltage reference voltage generating circuit according to claim 5, wherein a size ratio of the second transistor to the third transistor is 1: m, the size ratio of the fourth transistor to the fifth transistor is P: 1, wherein M and P are positive integers greater than 1.
8. The low voltage reference voltage generating circuit according to claim 4, wherein the reference current source module comprises:
the source electrode of the sixth transistor is connected with the source electrode of the seventh transistor and then connected to the preset power supply, and the grid electrode of the sixth transistor is connected with the grid electrode of the seventh transistor and provided with a first node;
an eighth transistor, an emitter of which is connected to a drain of the sixth transistor and has a second node, and a base of which is connected to a collector and then grounded;
a first resistor having one end connected to the drain of the seventh transistor and a third node;
an emitter of the ninth transistor is connected with the other end of the first resistor, and a base of the ninth transistor is connected with a collector and then grounded;
the positive input end of the error amplifier is connected with the third node, the negative input end of the error amplifier is connected with the second node, and the output end of the error amplifier is connected with the first node and then connected to the grid electrode of the first transistor;
one end of the second resistor is connected with the negative input end of the error amplifier;
one end of the third resistor is connected with the positive input end of the error amplifier, the other end of the third resistor is connected with the other end of the second resistor and is provided with a fourth node, and the fourth node is connected to the grid electrode of the second transistor;
and one end of the fourth resistor is connected with the fourth node, and the other end of the fourth resistor is grounded.
9. The low voltage reference voltage generation circuit according to claim 8, wherein a ratio of emitter areas of the eighth transistor to the ninth transistor is 1: and N, wherein N is an integer greater than 1.
10. The low voltage reference voltage generating circuit according to claim 8, wherein said high order temperature compensation module comprises:
a tenth transistor, a source of the tenth transistor is connected to the preset power supply, and a gate of the tenth transistor is connected to an output terminal of the error amplifier;
an eleventh transistor, an emitter of which is connected to a drain of the tenth transistor and has a fifth node, and a collector of which is connected to a base and then grounded;
one end of the fifth resistor is connected with the fifth node, and the other end of the fifth resistor is connected with the second node;
and one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the third node.
11. The low voltage reference voltage generating circuit according to claim 10, wherein said eighth transistor, said ninth transistor and said eleventh transistor are all bipolar transistors.
12. The low voltage reference voltage generating circuit according to claim 10, wherein said sixth transistor, said seventh transistor and said tenth transistor are all PMOS transistors and are equal in size.
13. The low voltage reference voltage generating circuit according to claim 10, wherein the final low temperature floating bandgap reference voltage outputted by the buffer module is determined according to an emitter-base voltage of the eighth transistor, an emitter-base voltage of the eleventh transistor, a resistance value of the second resistor, a resistance value of the fourth resistor, a resistance value of the fifth resistor, and a difference between a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
14. A chip comprising a low voltage reference voltage generation circuit according to any one of claims 1 to 13.
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