CN110109500B - Band-gap reference voltage source capable of self-excitation compensation - Google Patents

Band-gap reference voltage source capable of self-excitation compensation Download PDF

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CN110109500B
CN110109500B CN201910345265.8A CN201910345265A CN110109500B CN 110109500 B CN110109500 B CN 110109500B CN 201910345265 A CN201910345265 A CN 201910345265A CN 110109500 B CN110109500 B CN 110109500B
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pmos
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CN110109500A (en
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黄海生
惠强
李鑫
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Xian University of Posts and Telecommunications
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Abstract

In order to solve the technical problems that an operational amplifier exists in a traditional band-gap reference voltage source circuit, and the temperature characteristic and the output voltage stability of the band-gap reference voltage source are limited by factors such as offset voltage (offset) of the operational amplifier, power supply voltage rejection ratio (PSRR) and the like to a great extent, the invention provides a band-gap reference voltage source capable of self-excitation compensation, which comprises the traditional band-gap reference voltage source; the traditional band-gap reference voltage source comprises an operational amplifier OP, a power input port VDD and a voltage output port Vref; it is characterized in that: the circuit also comprises a switching circuit and a self-excitation compensation circuit; the self-excitation compensation circuit is used for providing feedback to one input VIN of the operational amplifier OP so as to ensure that the input VIN and the other input VIP of the operational amplifier OP are maintained at the same voltage value; the switching circuit is used for controlling the operation and the disconnection of the self-excitation compensation circuit.

Description

Band-gap reference voltage source capable of self-excitation compensation
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a self-excitation compensation band-gap reference voltage source.
Background
The reference source comprises a reference current source and a reference voltage source, which respectively provide reference current and reference voltage for the circuit, and is an essential basic component in an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a phase-locked loop (PLL), an Oscillator (OSC), a linear voltage regulator, a memory and a power management chip.
With the rapid development of Systems On Chip (SOC), CMOS processes are required to design analog integrated circuit cells. Conventional Reference voltage sources such as Zener Reference sources (Zener references) and Buried Zener Reference sources (Buried Zener references) are not suitable for use in the design of present day CMOS integrated circuits due to their high voltage, high power consumption and incompatibility with CMOS fabrication processes. The bandgap reference source is widely used in CMOS circuits due to its advantages in terms of temperature characteristics, power supply voltage rejection, power consumption, and process implementation.
The band-gap reference source is a key unit module in the design of an analog circuit and provides a direct current reference for a system. Its accuracy, temperature stability and supply voltage rejection ratio affect the accuracy and performance of the overall system. Taking an analog-to-digital converter (ADC) as an example, a high-speed high-precision ADC is a development trend of a data conversion system at present, and how to accurately quantize an analog signal in the high-speed high-precision ADC is a key for realizing high precision of the data conversion system. In analog-to-digital converter (ADC) systems, speed and accuracy are two important performance metrics. As a basic module in an analog-to-digital converter (ADC), because a reference voltage generated by a bandgap reference voltage source is related to an analog signal and a digital signal, the temperature stability and the power noise resistance of the bandgap reference voltage source are key factors influencing the conversion precision and directly influencing the performance of the whole ADC. However, the conventional bandgap reference voltage source circuit has an operational amplifier, and the temperature characteristics and the output voltage stability of the bandgap reference voltage source are limited by the offset voltage (offset) of the operational amplifier and the power supply voltage rejection ratio (PSRR).
Disclosure of Invention
In order to solve the technical problems that an operational amplifier exists in a traditional band-gap reference voltage source circuit, and the temperature characteristic and the output voltage stability of the band-gap reference voltage source are limited by factors such as offset voltage (offset) of the operational amplifier, power supply voltage rejection ratio (PSRR) and the like to a great extent, the invention provides a band-gap reference voltage source capable of self-excitation compensation.
The technical scheme of the invention is as follows:
a self-excitation compensation band-gap reference voltage source comprises a traditional band-gap reference voltage source; the traditional band-gap reference voltage source comprises an operational amplifier OP, a power input port VDD, a voltage output port Vref, PMOS tubes M6, M7 and M8, triodes Q1, Q2 and Q3, resistors R1, R2, R3 and R4; it is characterized in that: the circuit also comprises a switching circuit and a self-excitation compensation circuit;
the self-excitation compensation circuit is used for providing feedback to one input VIN of the operational amplifier OP so as to ensure that the input VIN and the other input VIP of the operational amplifier OP are maintained at the same voltage value;
the switching circuit is used for controlling the operation and the disconnection of the self-excitation compensation circuit.
Furthermore, the low-pass filter circuit is further included and is used for filtering high-frequency alternating-current signals of the power input port VDD and the voltage output port Vref.
Further, the self-excitation compensation circuit comprises PMOS tubes M9, M10, M11 and M12, and NMOS tubes M13, M14 and M15;
the grid of the PMOS tube M9 is connected with the enabling signal voltage EN output by the switch circuit and the enabling end of the operational amplifier OP, the source of the PMOS tube M9 is connected with a power input port VDD, the drain of the PMOS tube M9 is connected with the source of the PMOS tube M12, the grid and the drain of the PMOS tube M12 are connected with the drain of the NMOS tube M13, the grid of the M14, the drain of the M14 and the grid of the M15, the sources of the NMOS tubes M13, M14 and M15 are all grounded GND, the grid of the NMOS tube M13 is connected with the input VIN of the operational amplifier OP, the drain of the NMOS tube M15 is connected with the drain of the PMOS tube M10, the grid of the M10 and the grid of the M11, the source of the tube M11 is connected with the power input port VDD, and the drain of the PMOS tube M11;
PMOS tubes M10 and M11 form a group of current mirrors, and NMOS tubes M14 and M15 form a group of current mirrors respectively; the width-length ratio of the NMOS tubes M13, M14 and M15 is 1: 1: 1, the width-length ratio of the PMOS tubes M10 and M11 is 1: 1, the width-to-length ratio of the PMOS tubes M9 and M12 is (2 × 10)6) (1.3X), X is the resistance value of the resistor R1.
Further, the switch circuit comprises PMOS tubes M1, M3 and M5, and NMOS tubes M2 and M4;
the gates of the PMOS tube M1 and the NMOS tube M2 are both connected with an enable signal voltage EN, the drain ends of the PMOS tube M1 and the NMOS tube M2 are both connected with the gates of the PMOS tube M3 and the NMOS tube M4, the drains of the PMOS tube M3 and the NMOS tube M4 are both connected with the gate of the PMOS tube M5, and the drain of the PMOS tube M5 is connected with the gate ends of the PMOS tubes M6 and M7 of the traditional band gap reference voltage source; the sources of the PMOS tubes M1, M3 and M5 are all connected with a power input port VDD, and the sources of the NMOS tubes M2 and M4 are all grounded GND;
the PMOS transistor M1 and the NMOS transistor M2 form an inverter, and the PMOS transistor M3 and the NMOS transistor M4 form an inverter.
Further, the low-pass filter circuit comprises capacitors C1, C2 and a resistor R5; one end of the capacitor C1 is connected with a power input port VDD, and the other end is connected with the drain electrode of the PMOS tube M5 and the gate ends of the PMOS tubes M6 and M7 of the traditional band-gap reference voltage source; the resistor R5 and the capacitor C2 constitute a low-pass filter and are provided at the voltage output port Vref.
Further, R5 ═ 28.5K Ω, and C2 ═ 2.1 pF.
Compared with the prior art, the invention has the advantages that:
1. on the traditional band-gap reference voltage source circuit, the invention compensates the current on the resistor through which the voltage of the input end of the operational amplifier flows by using the MOS tube current mirror principle, thereby ensuring the common-mode input of the operational amplifier and weakening the offset voltage (offset) of the operational amplifier.
2. According to the invention, the capacitors are added to the power input port and the power output port, so that the power supply voltage suppression ratio under a high-frequency condition is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a self-excitation-compensated bandgap reference voltage source of the present invention.
Fig. 2 is a schematic structural diagram of an embodiment of the operational amplifier OP in fig. 1.
In fig. 1 and 2:
VDD is 3.3V power supply voltage;
SUB is the substrate voltage of all NMOS tubes;
EN is a circuit enabling signal voltage, and is 3.3V at a high level and 0V at a low level;
Vrefis the reference voltage finally output by the circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the self-excitation compensating bandgap reference voltage source provided by the present invention is added with a self-excitation compensating circuit 104, a switching circuit 103, a capacitor C1 and a low-pass filter 102 on the basis of a conventional bandgap reference voltage source 101.
The conventional bandgap reference voltage source 101 comprises PMOS transistors M6, M7, M8, an operational amplifier OP, resistors R1, R2, R3, R4, and triodes Q1, Q2 and Q3; VIN and VIP are two input ports of the operational amplifier OP, and the output VOUT of the operational amplifier OP can provide voltage for the gates of the PMOS transistors M6, M7 and M8, so that the PMOS transistors M6, M7 and M8 can work in a saturation region; the transistors Q1, Q2 are two identical transistors (I)SS1＝ISS2) The width-length ratios and the working states of the PMOS tubes M6, M7 and M8 are all consistent.
VREF＝VBE3+I8×R4 (1)
VBE1＝VTln(I6/ISS1) (2)
VBE2＝VTln(I7/ISS2) (3)
Figure GDA0002524475180000041
In the above formula:
VBE1、VBE2、VBE3base-emitter voltages of transistors Q1, Q2, Q3, respectively;
ISS1、ISS2the saturation currents of the triodes Q1 and Q2 are respectively;
VTis a thermal voltage, VTKT/q (K is boltzmann's constant, T is thermodynamic temperature, q is electrical quantity);
n is the area ratio of transistor Q2 to Q1.
I6、I7、I8The current flows through PMOS tubes M6, M7 and M8;
VR3is the voltage across resistor R3.
Figure GDA0002524475180000051
Figure GDA0002524475180000052
In the above formula: k is the width to length ratio of M3 to M2. Therefore:
Figure GDA0002524475180000053
as can be seen from the above formula (7), the reference voltage VrefForward voltage drop of PN junction only, resistance R4And R3The ratio of (a) to (b), the width-to-length ratio k of the MOS transistors M3 and M2, and the area ratio n of the transistors Q2 and Q1 are independent of the input voltage. First item VBE3Has a negative temperature coefficient of about-1.8 at room temperaturemV/. degree.C., V in the second termTThe band-gap reference voltage source 101 has a positive temperature coefficient which is about +0.086 mV/DEG C at room temperature, and according to the analysis, the positive temperature coefficient and the negative temperature coefficient of the traditional band-gap reference voltage source 101 can be offset by adjusting the width-length ratio of R4 and R3 and the value of n, so that a reference voltage which is independent of temperature is obtained.
The self-excited compensation circuit 104 is used to provide feedback for the input VIN of the operational amplifier OP in the conventional bandgap reference voltage source 101, so that the input VIN and the other input VIP of the operational amplifier OP are maintained at the same voltage value, thereby ensuring the common-mode input of the operational amplifier OP and reducing the offset voltage (offset) of the operational amplifier OP. The self-excitation compensation circuit 104 comprises PMOS tubes M9, M10, M11 and M12, and NMOS tubes M13, M14 and M15; the gate of the PMOS transistor M9 is connected to the enable signal voltage EN and the enable end of the operational amplifier OP, the source of the PMOS transistor M9 is connected to the power input port VDD, the drain of the PMOS transistor M9 is connected to the source of the PMOS transistor M12, the gate and the drain of the PMOS transistor M12 are connected to the drain of the NMOS transistor M13, the gate of the NMOS transistor M14, the drain of the NMOS transistor M14 and the gate of the NMOS transistor M15, the sources of the NMOS transistors M13, M14 and M15 are all grounded GND, the gate of the NMOS transistor M13 is connected to the input VIN of the operational amplifier OP, the drain of the NMOS transistor M15 is connected to the drain of the PMOS transistor M10, the gate of the transistor M10 and the gate of the transistor M11, the source of the PMOS transistor M11 is connected to the power input port VDD, and the drain of; the PMOS transistors M10 and M11 form a current mirror, and the NMOS transistors M14 and M15 form a current mirror. The width-length ratio of the NMOS tubes M13, M14 and M15 is 1: 1: 1, the width-length ratio of the PMOS tubes M10 and M11 is 1: 1, the width-to-length ratio of the PMOS tubes M9 and M12 is (2 × 10)6) (1.3X), X is the resistance value of the resistor R1.
The switching circuit 103 is used for controlling the operation and the switching off of the self-excitation compensation circuit 104 and the conventional bandgap reference voltage source 101. The switch circuit 103 comprises PMOS tubes M1, M3, M5 and NMOS tubes M2 and M4, the gates of the PMOS tubes M1 and NMOS tube M2 are connected with enable signal voltage EN, the drain terminals of the PMOS tubes M1 and NMOS tube M2 are connected with the gates of the PMOS tube M3 and NMOS tube M4, the drains of the PMOS tube M3 and NMOS tube M4 are connected with the gate of the PMOS tube M5, and the drain terminal of the PMOS tube M5 is connected with the gate terminals of the PMOS tubes M6 and M7 of the traditional band-gap reference voltage source 101; the sources of the PMOS tubes M1, M3 and M5 are all connected with the power input port VDD, and the sources of the NMOS tubes M2 and M4 are all connected with GND. The PMOS transistor M1 and the NMOS transistor M2 form an inverter, and the PMOS transistor M3 and the NMOS transistor M4 form an inverter, where the two-stage cascaded inverter can reduce the delay of the switch circuit 103 and enhance the reproducibility of the switch circuit 103 (ensuring that an interfered signal gradually converges back to one of the rated levels after passing through a plurality of logic stages).
The capacitor C1 is arranged at the power input port VDD and used for filtering high-frequency alternating current signals of the power input port VDD, and the alternating current signals in the power can be effectively prevented from influencing output.
The low-pass filter 102 is used for filtering the high-frequency ac signal at the voltage output port Vref, and includes a resistor R5 and a capacitor C2, which are used for effectively preventing the high-frequency signal from affecting the output port. Wherein R5-28.5K Ω and C2-2.1 pF, according to the formula
Figure GDA0002524475180000072
The characteristic frequency omega can be obtained0Is 2.66 MHz. This shows that the low pass filter 102 has a very good rejection at frequencies above 2.66 MHz.
The capacitor C1 and the low-pass filter 102 reduce the influence of the high-frequency alternating current signals of the power input port VDD and the voltage output port Vref on the conventional bandgap reference voltage source 101, and improve the power supply voltage rejection ratio (PSRR).
As shown in fig. 2, the operational amplifier OP mainly includes a sleeve-type cascode operational amplification unit 201, a switch circuit 202, and a first current mirror circuit 203;
the cascode operational amplifier unit 201 is composed of PMOS transistors M29, M30, M34, M35 and NMOS transistors M31, M32, M36, M37, M28 and M33, wherein the NMOS transistors M28 and M33 constitute a current mirror.
The switch circuit 202 is used for controlling the operation and the turn-off of the operational amplifier unit 201, and is composed of NMOS transistors M17, M20, M23, M27, and a PMOS transistor M19.
The first current mirror circuit 203 includes PMOS transistors M21, M22, M24, and M25.
The drain terminal voltage of the PMOS tube M16 provides gate terminal voltage bias for the PMOS tubes M22, M25, M30 and M35; the drain terminal voltage of the PMOS transistor M25 provides gate terminal voltage bias for the NMOS transistors M26, M31 and M36; the drain terminal voltage of the PMOS tube M22 provides gate terminal voltage bias for the PMOS tubes M21 and M24, and the drain terminal voltage of the PMOS tube M30 provides gate terminal voltage bias for the PMOS tubes M29 and M34; the source voltage of the NMOS transistor M26 provides a gate voltage bias for the NMOS transistors M28 and M33, so as to ensure that all transistors operate in the saturation region when the operational amplifier OP operates normally.
When the enable signal voltage EN is at a low level, M18 and M19 both operate in a saturation region, and at this time, the drain voltage of M19 is M17, M20, M23, and M27 all provide gate voltage bias, so that M17, M20, M23, and M27 operate in the saturation region, and at this time, the operational amplification unit 201 operates normally. The gain of the operational amplification unit 201 satisfies the following equation:
Figure GDA0002524475180000071
calculated | Av|＝695mdB。
When the enable signal voltage EN is high, M18, M19, M17, M20, M23 and M27 are all in an off state, and I is in this case11＝I12＝I17When the current is not flowing in the operational amplification unit 201, the operational amplification unit 201 is in the off state at this time, i.e., 0.
The principle of the self-excitation compensation band-gap reference voltage source of the invention is as follows:
when the enable signal voltage EN is at a high level, the voltage output to the gate of the PMOS transistor M5 through the two-stage cascaded inverter in the switch circuit 103 is also at a high level, i.e. the PMOS transistor M5 is in an off state, and the drain of M5 is assimilated by the output voltage of the operational amplifier OP, which does not affect the conventional bandgap reference voltage source 101.
When EN is at a high level, the self-excited compensation circuit 104 normally operates, and at this time, the PMOS transistor M9 and the PMOS transistor M12 both operate in a saturation region:
I9＝I12＝I13+I14 (9)
I10＝I11＝I14＝I15 (10)
Figure GDA0002524475180000081
in the above formula (11):
Coxis unit width overlap capacitance, VTH13Is the threshold voltage of NMOS transistor M13, W is the gate width of NMOS transistor M13, L is the channel length of NMOS transistor M13, wherein IXThe current flowing through the MOS tube MX is the current (the value of X is consistent with the serial number of the MOS tube).
Since PMOS transistors M9 and M12 both operate in saturation region, I9＝I12And the constant value is kept unchanged. When VIN increases by 1V, I13The ratio of 1/R1 is increased, and the I is9＝I12＝I13+I14Therefore I is14Will reduce 1/R1, i.e. the current I fed back to VIN11Will also decrease by 1/R1 to ensure that the voltage of VIN is equal to the voltage of VIP; conversely, when VIN is decreased by 1V, I13Also reduces 1/R1, again because of I9＝I12＝I13+I14Therefore I is14Will increase 1/R1, i.e. the current I fed back to VIN11Will also increase 1/R1 to ensure that the voltage of VIN is equal to the voltage of VIP. Meanwhile, when the operational amplifier OP works normally, the output VOUT of the operational amplifier OP provides voltage bias of a grid end for the PMOS tubes M6 and M7, the whole self-excitation compensation band-gap reference voltage source circuit is in a running state, and normal reference voltage Vref can be output; the self-excited compensation circuit 104 feeds back VIN, which ensures that VIN is maintained at the same voltage value as VIP, and ensures the common-mode input of the operational amplifier OP, thereby attenuating the offset voltage (offset) of the operational amplifier.
When EN is at a low level, the switching circuit 103, the self-excited compensation circuit 104, and the operational amplifier OP are all in an off state, and correspondingly, the whole bandgap reference voltage source circuit is in an off state at this time.

Claims (5)

1. A self-excitation compensation band-gap reference voltage source comprises a traditional band-gap reference voltage source; the traditional band-gap reference voltage source comprises an operational amplifier OP, a power input port VDD, a voltage output port Vref, PMOS tubes M6, M7 and M8, triodes Q1, Q2 and Q3, resistors R1, R2, R3 and R4;
the output end VOUT of the operational amplifier OP is simultaneously connected with the grids of the PMOS tubes M6, M7 and M8; a first input port VIN of the operational amplifier OP is connected with a drain electrode of the PMOS transistor M6, and is also connected with an emitter electrode of the triode Q1 through a resistor R1; a second input port VIP of the operational amplifier OP is connected with the drain electrode of the PMOS transistor M7 and is simultaneously connected with the emitter electrode of the triode Q2 through resistors R2 and R3;
the sources of the PMOS tubes M6, M7 and M8 are all connected with a power input port VDD;
the grid electrode of the PMOS pipe M8 is connected with the emitter electrode of the triode Q3 through a resistor R4;
bases and collectors of the triodes Q1, Q2 and Q3 are all grounded GND;
the method is characterized in that:
the circuit also comprises a switching circuit and a self-excitation compensation circuit;
the switching circuit is used for controlling the operation and the turn-off of the self-excitation compensation circuit;
the self-excitation compensation circuit is used for providing feedback to one input VIN of the operational amplifier OP so as to ensure that the input VIN and the other input VIP of the operational amplifier OP are maintained at the same voltage value;
the self-excitation compensation circuit comprises PMOS tubes M9, M10, M11 and M12, and NMOS tubes M13, M14 and M15;
the grid of the PMOS tube M9 is connected with the enabling signal voltage EN output by the switch circuit and the enabling end of the operational amplifier OP, the source of the PMOS tube M9 is connected with a power input port VDD, the drain of the PMOS tube M9 is connected with the source of the PMOS tube M12, the grid and the drain of the PMOS tube M12 are connected with the drain of the NMOS tube M13, the grid of the M14, the drain of the M14 and the grid of the M15, the sources of the NMOS tubes M13, M14 and M15 are all grounded GND, the grid of the NMOS tube M13 is connected with the input VIN of the operational amplifier OP, the drain of the NMOS tube M15 is connected with the drain of the PMOS tube M10, the grid of the M10 and the grid of the M11, the source of the tube M11 is connected with the power input port VDD, and the drain of the PMOS tube M11;
PMOS tubes M10 and M11 form a group of current mirrors, and NMOS tubes M14 and M15 form a group of current mirrors respectively;
the width-length ratio of the NMOS tubes M13, M14 and M15 is 1: 1: 1, the width-length ratio of the PMOS tubes M10 and M11 is 1: 1, the width-to-length ratio of the PMOS tubes M9 and M12 is (2 × 10)6) (1.3X), X is the resistance value of the resistor R1.
2. A self-excitation-compensated bandgap reference voltage source as claimed in claim 1, wherein: the low-pass filter circuit is used for filtering high-frequency alternating current signals of the power input port VDD and the voltage output port Vref.
3. A self-excitation-compensated bandgap reference voltage source as claimed in claim 2, wherein: the switch circuit comprises PMOS tubes M1, M3 and M5, and NMOS tubes M2 and M4;
the gates of the PMOS tube M1 and the NMOS tube M2 are both connected with an enable signal voltage EN, the drain ends of the PMOS tube M1 and the NMOS tube M2 are both connected with the gates of the PMOS tube M3 and the NMOS tube M4, the drains of the PMOS tube M3 and the NMOS tube M4 are both connected with the gate of the PMOS tube M5, and the drain of the PMOS tube M5 is connected with the gate ends of the PMOS tubes M6 and M7 of the traditional band gap reference voltage source; the sources of the PMOS tubes M1, M3 and M5 are all connected with a power input port VDD, and the sources of the NMOS tubes M2 and M4 are all grounded GND;
the PMOS transistor M1 and the NMOS transistor M2 form an inverter, and the PMOS transistor M3 and the NMOS transistor M4 form an inverter.
4. A self-excitation-compensated bandgap reference voltage source as claimed in claim 3, wherein: the low-pass filter circuit comprises capacitors C1 and C2 and a resistor R5; one end of the capacitor C1 is connected with a power input port VDD, and the other end is connected with the drain electrode of the PMOS tube M5 and the gate ends of the PMOS tubes M6 and M7 of the traditional band-gap reference voltage source; the resistor R5 and the capacitor C2 constitute a low-pass filter and are provided at the voltage output port Vref.
5. A self-excitation-compensated bandgap reference voltage source as claimed in claim 4, wherein: r5 ═ 28.5K Ω, and C2 ═ 2.1 pF.
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