CN219016862U - Exponential temperature compensation band-gap reference circuit without operational amplifier - Google Patents
Exponential temperature compensation band-gap reference circuit without operational amplifier Download PDFInfo
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- CN219016862U CN219016862U CN202223315026.4U CN202223315026U CN219016862U CN 219016862 U CN219016862 U CN 219016862U CN 202223315026 U CN202223315026 U CN 202223315026U CN 219016862 U CN219016862 U CN 219016862U
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Abstract
The utility model discloses an exponential temperature compensation band-gap reference circuit without an operational amplifier, which solves the problems of complex circuit and high offset voltage in the prior art. The utility model comprises a starting circuit, a band-gap reference core circuit, a temperature compensation circuit and an output circuit, wherein the temperature compensation is to utilize the base current of a triode to carry out curvature correction so as to obtain an exponential-type temperature compensated band-gap reference voltage source circuit. The circuit has the advantages that an operational amplifier structure is not adopted, and the influence of offset voltage on reference voltage is weakened; the exponential temperature compensation circuit is simple, and can greatly improve the precision of the band gap reference source.
Description
Technical Field
The application relates to a circuit technology, in particular to a simple band gap reference circuit without an operational amplifier and an exponential type temperature compensation method.
Background
The band gap reference source is widely applied to various circuits and provides a precise and stable reference voltage independent of external environments such as power supply, temperature and the like for the circuits.
The basic principle of the conventional bandgap reference circuit is that two PNP transistors are utilized as shown in FIG. 1The difference between the base-emitter voltages generates a positive temperature coefficient current, the current is copied to an output circuit through a current mirror, the positive temperature coefficient voltage is generated through a resistor in the output circuit, and then the positive temperature coefficient voltage is connected with a V of a triode in the output circuit BE The superposition generates a reference voltage subjected to first-order temperature compensation in an output circuit, and the formula can be expressed as follows:
in the above, V ref Is the reference voltage, V BE3 Is the base-emitter voltage of PNP triode Q3, V T Is thermal voltage, V OS The input offset voltage of the operational amplifier is N, and N is the number of parallel triodes Q1.
From the formula (1), the existence of the operational amplifier not only introduces the input offset voltage V OS Affecting the temperature coefficient of the reference voltage also increases the difficulty of circuit design and the power consumption of the circuit.
Actual triode V BE There are also temperature-dependent higher order components that cannot convert V BE The higher-order components in the circuit are counteracted, so that the reference voltage still has a larger temperature drift coefficient, and the requirement of a modern high-precision circuit cannot be met. Therefore, in order to solve the above problems, a simple exponential temperature compensation circuit is designed, and no extra consumption current is needed, so that temperature compensation of the circuit is realized.
Disclosure of Invention
In order to solve the technical problems of the circuit, an exponential temperature compensation band-gap reference circuit without an operational amplifier is provided, and the temperature drift coefficient of a reference source is reduced, and the detailed technical scheme of the utility model is as follows:
an exponential temperature compensation band-gap reference circuit without an operational amplifier comprises a band-gap reference core circuit, a temperature compensation circuit, a starting circuit and an output circuit, wherein:
the bandgap reference core circuit is used for generating a temperature coefficient current positively correlated with temperature, copying the current to the output circuit, and generating a voltage positively correlated with temperature in a resistor in the output circuit.
The temperature compensation circuit is to generate negative temperature current with exponential relation with temperature by utilizing exponential relation of triode current gain, so as to realize high-order compensation in the voltage reference source.
The starting circuit is used for providing proper bias for the core circuit, the temperature compensation circuit and the output circuit, completing the pull-down when the circuit starts to start, providing current for the circuit, and automatically closing the circuit after working.
The output circuit is formed by superposing the currents obtained by the core circuit and the temperature compensation circuit and then connecting the superposed currents with the V of the triode BE And superposing to generate a reference voltage source.
Further, the bandgap reference core circuit mainly comprises PMOS: MP1, MP2, MP3, MP4; NPN tube: q1 and Q2; and a resistor R1. The low-voltage folding common-source common-gate current mirror structure is realized by MP1, MP2, MP3 and MP4, the source stages of MP1 and MP2 are connected with VDD, the grid electrodes of MP1 and MP2 are connected with the drain electrodes of MP3, MP5 and MN1, the drain electrodes of MP1 and MP2 are respectively connected with the source stages of MP3 and MP4, the grid electrodes of MP3 and MP4 are obtained by biasing MP5 in a starting circuit, the drain electrode of MP3 is connected with the collector electrode of Q1, the drain electrode of MP4 is connected with the collector electrode of Q2, and the base electrodes of Q1 and Q2 in a temperature compensation circuit are connected with the source electrode of MN 5. The other ends of the emitter connecting resistors R1 and R1 of the Q1 are grounded, and the emitter of the Q2 is grounded.
Furthermore, the temperature compensation circuit comprises PMOS (P-channel metal oxide semiconductor) MP7 and MP10; NMOS, MN5; NPN tertiary tube: q1 and Q2; the drain electrode of the MN5 is a connected low-voltage folding common-source common-gate tube, the source electrodes of the MP7 and the MP10 are connected with the VDD, the grid electrode is connected to the drain electrodes of the MP10 and the MN5, the drain end of the MP7 is connected to the source end of the MP10, the grid end of the MP10 is connected with the self-bias voltage of the MP5 in the starting circuit, and the source stage of the MN5 is connected to the base electrodes of the NPN triodes Q1 and Q2.
Furthermore, the starting circuit comprises NMOS (N-channel metal oxide semiconductor) of MN1, MN2, MN3 and MN4; PMOS, MP5, MP6; r3 is a resistor; one end of the resistor R3 is connected with the VDD, the other end is connected with the drain electrode of the MN2, the grid electrode of the MN2 is connected with the grid electrode and the drain electrode of the MN3, the grid electrode of the MN4 and the drain electrode of the MP6, the drain electrode of the MP3 is connected with the collector electrode of the Q1, the source electrode of the MP6 is connected with the VDD, the drain electrode of the MN4 is connected with the grid electrode and the drain electrode of the MP5, the source electrodes of the MP5 are grounded, and the source electrodes of the MN1, the MN2, the MN3 and the MN4 are grounded.
Furthermore, the output circuit comprises PMOS (P-channel metal oxide semiconductor) MP8, MP9, MP11 and MP12; NPN pipe Q3, resistance: r2; the source terminals of MP8 and MP9 are connected with VDD, the gate terminal of MP8 is connected with the gate terminal of MP7, the gate terminal of MP9 is connected with MP1, the drain terminal of MP8 is connected with the source terminal of MP11, the drain terminal of MP9 is connected with the source terminal of MP12, the gate terminals of MP11 and MP12 are connected with the gate terminal of MP5 in the starting circuit, the drain terminals of MP11 and MP12 are connected with the base and collector of NPN triode Q3, the emitter of NPN triode Q3 is connected with the first terminal of resistor R2, and the second terminal of resistor R2 is connected with GND.
The utility model has the advantages and beneficial effects as follows:
the temperature compensation circuit is realized through the negative feedback constructed by the simple NMOS tube, and the temperature coefficient of the reference circuit is reduced while a new circuit and power consumption are not additionally increased. The utility model does not use an operational amplifier, and avoids input offset caused by operational amplifier differential input mismatch. The circuit has simple structure, can be realized in any CMOS process, has smaller chip area and saves cost.
Drawings
Fig. 1 is a schematic diagram of a bandgap reference voltage source commonly used in the prior art.
Fig. 2 is a schematic diagram of an exponential temperature compensated bandgap reference circuit without op amp.
Detailed Description
The utility model will now be described in detail with reference to the drawings and the accompanying specific examples.
The technical scheme for solving the technical problems is as follows:
the first-order bandgap reference in the embodiments of the present application utilizes the difference between the base-emitter voltages of two NPN transistors to generate a positive temperature coefficient current I PTAT Positive temperature coefficient voltage V generated by positive temperature coefficient current flowing through resistor PTAT Generating a negative temperature coefficient voltage V by using the base-emitter voltage of the triode with short base-collector CTAT To the negative temperature coefficient voltage V CTAT And positive temperature coefficient voltage V PTAT And weighting to obtain the first-order band gap reference voltage. The base currents of NPN triodes Q1 and Q2 in the band-gap reference core circuit are led into the output circuit to compensate the band-gap reference voltage by utilizing the fact that the triode current gain beta increases exponentially along with the temperature increase, so that the temperature coefficient of the reference voltage is effectively reduced.
Embodiments of the present utility model will be further described below with reference to the drawings.
Examples
Referring to fig. 2, the present utility model includes: a bandgap reference core circuit 1, a temperature compensation circuit 2, an output circuit 3 and a start-up circuit 4.
Referring to fig. 2, the bandgap reference core circuit 1 includes a PMOS transistor: MP1, MP2, MP3, MP4; NPN tertiary tube: q1 and Q2; a resistor R1; wherein the grid electrodes of MP1 and MP2 are connected to form a current mirror structure, the source electrodes of MP1 and MP2 are commonly connected to VDD, the drain electrode of MP1 is connected with the source electrode of MP3, and the drain electrode of MP2 is connected with the source electrode of MP4; the grid electrodes of MP3 and MP4 are commonly connected to the grid electrode and the drain electrode of MP5 in the starting circuit 4; the drain electrode of MP3 is connected with collector electrode of NPN triode Q1, grid electrodes of MP1 and MP2 respectively, and the drain electrode of MP4 is connected with collector electrode of triode Q2; the bases of the NPN triode Q1 and the NPN triode Q2 are connected with the source electrode of the MN5 in the temperature compensation circuit 2; the first end of a resistor R1 of the NPN triode Q1 is connected, and the second end of the resistor R1 is connected with GND; the source of NPN triode Q2 is connected to GND.
MP1 and MP2 form a current mirror structure, the two PMOS tube devices have the same size, the grid electrodes of MP3 and MP4 are connected, the two PMOS tube devices have the same size, and furthermore, MP1, MP2, MP3 and MP4 form a common-source common-gate current mirror. The current I1 flowing through MP1 is the same as the current I2 flowing through MP 2. The number ratio of NPN triode Q1 to NPN triode Q2 is N:1, thus generating DeltaV at two ends of resistor R1 BE Is a voltage difference of (2):
ΔV BE ＝V T lnN (2)
the current flowing through the resistor R1 is a positive temperature coefficient current, and the value thereof is:
referring to fig. 2, the exponential temperature compensation circuit 2 includes a PMOS transistor: MP7, MP10; NMOS tube: MN5; NPN tertiary tube: q1 and Q2; the source electrode of MP7 is connected with VDD, the grid electrode of MP7 is connected with drain electrode of MP10, drain electrode of MN5 and grid electrode of MP8 in output circuit 3 respectively, the drain electrode of MP7 is connected with source electrode of MP10; the grid electrode in MP10 is connected with the grid electrode of MP5 in the starting circuit 4; the grid electrode of the MN5 is respectively connected with the drain electrode of MP4 and the collector electrode of triode Q2 in the band-gap reference core circuit 1, and the source electrode of the MN5 is respectively connected with the base electrodes of NPN tertiary tubes Q1 and Q2 in the band-gap reference core circuit (1).
MP7 and MP8 in the output circuit 3 form a current mirror structure, and the two PMOS tube devices have the same size, MP10 and MP11 in the output circuit 3 form a current mirror structure, and the two PMOS tube devices have the same size, and further MP7, MP8, MP10 and MP11 form a cascode current mirror. The current of the branch where MN5 is located is the base current of NPN transistors Q1, Q2 in band gap reference core circuit 1.
The current amplification factor β of a transistor is a function of temperature, β (t) can be expressed as follows:
beta in ∞ And delta E G Are constant independent of temperature, ΔE G Is a reduction factor of the emitter forbidden band width.
The base currents of NPN transistors Q1, Q2 are:
the base currents of Q1 and Q2 in the band-gap reference core circuit 1 are copied to an output circuit through a temperature compensation circuit to compensate V BE Higher-order terms of (2).
Referring to fig. 2, the output unit circuit 3 includes a PMOS transistor: MP8, MP9, MP11, MP12; a triode Q3; a resistor R2; wherein the sources of MP8 and MP9 are connected with VDD, the grid of MP8 is connected with the grid of MP7 in the temperature compensation circuit 2, the drain of MP8 is connected with the source of MP 11; the grid electrode of MP9 is connected with the grid electrode of MP1 in the band gap reference core circuit 1; the drain electrode of MP9 is connected with the source electrode of MP12; the grid electrodes of MP11 and MP12 are connected with the grid electrode of MP5 in the starting circuit 4, and the drain electrodes of MP11 and MP12 are connected with the base electrode and collector electrode of NPN triode Q3; an emitter of the NPN triode Q3 is connected with a first end of a resistor R2, and a second end of the resistor R2 is connected with GND.
MP1 and MP9 form a current mirror structure, the width-to-length ratio of the two PMOS tubes is 1:M, the gates of the MP3 and MP12 are connected, the width-to-length ratio of the two PMOS tubes is 1:M, and further, MP1, MP3, MP9 and MP12 form a common-source common-gate current mirror.
The positive temperature coefficient current generated by the band-gap reference core circuit 1 is copied to R2 in the output circuit 3 through a current mirror to generate a positive temperature coefficient voltage V PTAT Will positive temperature coefficient voltage V PTAT And negative temperature coefficient voltage V BE Superposition to generate a first-order bandgap reference voltage V ref Expressed as:
V ref ＝V BE +M·I PTAT ·R2 (6)
the triode current gain beta increases exponentially with the temperature, and base currents of NPN triodes Q1 and Q2 in the band-gap reference core circuit 1 are copied to an output circuit through a temperature compensation circuit to compensate V BE Higher-order terms of (2). Compensated bandgap reference voltage V ref Expressed as:
in the above
Adjusting resistance value, triode emission junction area and current proportion to realize V BE Is a counter-act of (a).
Referring to fig. 2, the start-up circuit 4 includes a PMOS transistor: MP5 and MP6; NMOS tube: MN1, MN2, MN3, MN4; resistance: r3; the source electrode of MP5 is connected with VDD, the grid electrode and drain electrode of MP5 are respectively connected with drain electrode of MN4, grid electrode of MP3 in band gap reference core unit 1, grid electrode of MP4, grid electrode of MP11 in output circuit 3 and grid electrode of MP12; the source electrode of the MN4 is connected with GND, and the grid electrode of the MN4 is respectively connected with the grid electrode and the drain electrode of the MN3, the drain electrode of the MP6 and the grid electrode of the MN 2; the source of MN3 is connected with GND; the source electrode of MP6 is connected with VDD, the grid electrode of MP6 is connected with the drain electrode of MN1 and the drain electrode of MP3 in band gap reference core circuit 1 respectively; the source electrode of the MN2 is connected with GND, and the drain electrode of the MN2 is respectively connected with the grid electrode of the MN1 and the second end of the resistor R3; the first terminal of resistor R3 is connected to VDD and the source terminal of MN1 is connected to GND.
MP5 converts the current of the branch circuit into voltage, and provides bias voltage for the grid electrode of MP3, the grid electrode of MP4, the grid electrode of MP11 and the grid electrode of MP12 in the output circuit 3 in the band gap reference core unit 1.
When the circuit is electrified, the MN1 transistor is conducted, the potential of the drain end of the MP3 tube is pulled down, the MP1 and MP2 tube branches are conducted, and the circuit enters a working state. MP6 pipe is conducted, MN3 pipe converts branch current into voltage to make MN2 pipe conducted, gate end of MN1 pipe is pulled down to low potential, and starting circuit is closed.
The first end and the second end of all the resistors are defined according to the flowing direction of the current, one end of the resistor through which the current passes first is the first end, and the other end is the second end.
The above description is only a preferred embodiment of the present utility model and does not constitute any limitation of the present utility model, and various changes and modifications can be made to the circuit under the concept of the present utility model, but these are all within the scope of the present utility model.
Claims (12)
1. An exponential temperature compensated bandgap reference circuit without op amp, comprising:
band gap reference core circuit (1) for generating positive temperature coefficient current I PTAT ；
A temperature compensation circuit (2) which compensates the temperature drift of the reference voltage source voltage by adopting the base current of the triode;
an output circuit (3) for copying the positive temperature coefficient current and the temperature compensation current generated by the band-gap reference core circuit (1) to R2 in the output circuit (3) through a current mirror, and generating voltage and negative temperature coefficient voltage V BE Adding to generate a zero temperature coefficient voltage;
and the starting circuit (4) is used for providing starting current for the band-gap reference core circuit (1).
2. A bandgap reference circuit as claimed in claim 1, wherein: the band gap reference core circuit (1) comprises a PMOS tube: MP1, MP2, MP3, MP4; NPN tertiary tube: q1 and Q2; a resistor R1; the grid electrodes of the MP1 and the MP2 are respectively connected with the drain electrode of the MP3, the collector electrode of the NPN transistor Q1, the drain electrode of the MN1 in the starting circuit (4) and the grid electrode of the MP9 in the output circuit (3), the drain electrode of the MP1 is connected with the source electrode of the MP3, and the drain electrode of the MP2 is connected with the source electrode of the MP4; the grid electrodes of the MP3 and the MP4 are respectively connected with the grid electrode and the drain electrode of MP5 in the starting circuit (4), the grid electrode of MP10 in the temperature compensation circuit (2) and the grid electrodes of MP11 and MP12 in the output circuit (3); the drain electrode of MP4 is connected with the collector electrode of triode Q2 and the grid electrode of MN5 in temperature compensation circuit (2); the bases of the NPN triode Q1 and the NPN triode Q2 are connected with the source electrode of the MN5 in the temperature compensation circuit (2); NPN triode Q1 links with first end of the resistance R1, the second end of the resistance R1 links with GND; the source of transistor Q2 is connected to GND.
3. A bandgap reference circuit as claimed in claim 2, wherein: the base voltages of NPN transistor Q1 and NPN transistor Q2 in the band gap reference core circuit (1) are the same, so the voltage at two ends of resistor R1 is DeltaV BE ＝V T lnN，ΔV BE The current flowing through the branch where the resistor R1 is positioned is in direct proportion to the temperature and is positive temperature coefficient current
4. A bandgap reference circuit as claimed in claim 2, wherein: MP1 and MP2 in the band gap reference core circuit (1) and MP9 in the output circuit (3) form a current mirror.
5. A bandgap reference circuit as claimed in claim 1, wherein: the temperature compensation circuit (2) comprises a PMOS tube: MP7, MP10; NMOS tube: MN5; NPN tertiary tube: q1 and Q2; the source electrode of MP7 is connected with VDD, the grid electrode of MP7 is connected with drain electrode of MP10, drain electrode of MN5 and grid electrode of MP8 in output circuit (3), the drain electrode of MP7 is connected with source electrode of MP10; the grid electrode of the MN5 is respectively connected with the drain electrode of MP4 and the collector electrode of NPN triode Q2 in the band-gap reference core circuit (1), and the source electrode of the MN5 is respectively connected with the base electrodes of NPN triodes Q1 and Q2 in the band-gap reference core circuit (1).
6. A bandgap reference circuit as claimed in claim 5, wherein: MP7 in the temperature compensation circuit (2) and MP8 in the output circuit (3) form a current mirror, and base currents of Q1 and Q2 in the band gap reference core circuit (1) are copied into the output circuit (3) through the temperature compensation circuit (2).
7. A bandgap reference circuit as claimed in claim 5, wherein: the band gap reference core circuit (1) and the temperature compensation circuit (2) share NPN triodes Q1 and Q2.
8. A bandgap reference circuit as claimed in claim 1, wherein: the output circuit (3) comprises a PMOS tube: MP8, MP9, MP11, MP12; NPN transistor Q3; a resistor R2; wherein the source electrode of MP8 is connected with VDD, the grid electrode of MP8 is connected with grid electrode of MP7, drain electrode of MP10 and drain electrode of MN5 in the temperature compensation circuit (2), the drain electrode of MP8 is connected with the source electrode of MP 11; the source electrode of MP9 is connected with VDD, the drain electrode of MP9 is connected with the source electrode of MP12; the grids of MP11 and MP12 are respectively connected with the grids of MP3 and MP4 of the band-gap reference core circuit (1), the grid and drain of MP5 in the starting circuit (4) and the grid of MP10 in the temperature compensation circuit (2), and the drains of MP11 and MP12 are connected with the output V ref Base and collector of NPN triode Q3Are connected; an emitter of the NPN triode Q3 is connected with a first end of a resistor R2, and a second end of the resistor R2 is connected with GND.
9. A bandgap reference circuit as claimed in claim 8, wherein: the positive temperature coefficient current generated by R1 in the band-gap reference core circuit and the base currents of NPN triodes Q1 and Q2 are copied to R2 in the output circuit (3) through a current mirror, and the generated voltage and the base-emitter voltage V of the NPN triode Q3 BE The addition produces a zero temperature coefficient voltage.
10. A bandgap reference circuit as claimed in claim 1, wherein: the starting circuit (4) comprises a PMOS tube: MP5 and MP6; NMOS tube: MN1, MN2, MN3, MN4; resistance: r3; the source electrode of MP5 is connected with VDD, the grid electrode and drain electrode of MP5 are respectively connected with the drain electrode of MN4, grid electrode of MP3 in band gap reference core unit (1), grid electrode of MP4, grid electrode of MP11 in output circuit (3) and grid electrode of MP12; the source electrode of the MN4 is connected with GND, and the grid electrode of the MN4 is respectively connected with the grid electrode and the drain electrode of the MN3, the drain electrode of the MP6 and the grid electrode of the MN 2; the source of MN3 is connected with GND; the source electrode of MP6 is connected with VDD, the grid electrode of MP6 is connected with the drain electrode of MN1, the grid electrodes of MP1 and MP2 in the band gap reference core circuit (1), the drain electrode of MP3, the collector electrode of NPN transistor Q1, and the grid electrode of MP9 in the output circuit (3) respectively; the source electrode of the MN2 is connected with GND, and the drain electrode of the MN2 is respectively connected with the grid electrode of the MN1 and the second end of the resistor R3; the first terminal of resistor R3 is connected to VDD and the source terminal of MN1 is connected to GND.
11. A bandgap reference circuit as claimed in claim 10, wherein: the gate terminal voltage of MP5 provides bias voltage for gate terminals of MP3, MP4 in the band gap reference core unit (1) and MP11, MP12 in the output circuit (3); MN4 forms a current mirror with MN3, MN 2.
12. A bandgap reference circuit as claimed in claim 10, wherein: when the power supply VDD is electrified, the starting circuit (4) enables the band gap reference core circuit (1) to be separated from a zero degeneracy point, so that the reference circuit enters a normal working state, and the starting circuit is turned off after the power supply VDD is electrified.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116931642A (en) * | 2023-09-13 | 2023-10-24 | 浙江地芯引力科技有限公司 | Band-gap reference voltage source and band-gap reference circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116931642A (en) * | 2023-09-13 | 2023-10-24 | 浙江地芯引力科技有限公司 | Band-gap reference voltage source and band-gap reference circuit |
| CN116931642B (en) * | 2023-09-13 | 2023-12-19 | 浙江地芯引力科技有限公司 | Band-gap reference voltage source and band-gap reference circuit |
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