CN113934249A - Band-gap reference voltage source suitable for low-current gain type NPN triode - Google Patents

Abstract

The invention belongs to the technical field of reference sources, and particularly relates to a band-gap reference voltage source suitable for a low-current gain type NPN triode. The invention utilizes a local self-bias circuit in the traditional Wildar type band-gap reference voltage source framework to offset the base current imbalance in the traditional Wildar type band-gap reference voltage source framework, and utilizes the base current extracted by the local self-bias to feed back to the circuit to further improve the precision of the output reference, namely finally obtain the high-precision reference voltage irrelevant to the Beta absolute value, so that the traditional Wildar type reference voltage source framework is insensitive to the triode current gain coefficient Beta, and simultaneously still keeps the characteristics of more loose input mismatch and noise requirements on the rear-stage operational amplifier, and is suitable for the application scene of low power supply voltage.

Description

Band-gap reference voltage source suitable for low-current gain type NPN triode

Technical Field

The invention belongs to the technical field of reference sources, and particularly relates to a band-gap reference voltage source suitable for a low-current gain type NPN triode.

Background

A band gap reference voltage source (Bandgap) is widely used in the chip field as a voltage reference due to its high precision characteristic. In a chip, designers often need to keep certain voltages within a set range through loop control, or need to generate high-precision current, or realize comparison and monitoring of certain voltage signals, which are all independent of an on-chip Bandgap reference voltage source (Bandgap). A band-gap reference voltage source in a chip is usually used for a triode (BJT) as a key device, and the principle is that a triode base-emitter Voltage (VBE) with negative temperature characteristic and a base-emitter voltage difference (delta _ VBE) with positive temperature characteristic are added to create a high-precision voltage value independent of temperature. In the band-gap reference voltage source, the NPN type triode can obtain higher precision or better offset noise suppression by matching with different band-gap reference architectures due to a flexible three-terminal connection method, that is, unlike a parasitic PNP type triode, a collector (collector) can only be connected with a substrate (substrate), and only a traditional band-gap reference architecture can be built. For example, the NPN transistor can obtain a high-precision reference voltage by using a Brokaw-type bandgap reference architecture or a Widlar-type bandgap reference architecture to suppress offset and noise of the subsequent stage operational amplifier. However, due to cost considerations or process limitations, NPN transistors are often encountered in designs that do not have a high transistor current gain coefficient (Beta value). Some bandgap reference architectures require a Beta value greater than 20 or 50 or even higher to neglect the effect of the Beta variation on the final output reference voltage in the ideal formula, thereby limiting the application of high-precision reference architectures, such as the Wildar type. Meanwhile, as the power supply voltage required to operate is lower and lower, a part of bandgap reference structures, such as Brokaw type, cannot be satisfied. How to obtain a band-gap reference architecture which is high in precision and compatible with low-voltage operation under the condition of only a low-current gain type NPN triode is an urgent problem to be solved.

The Brokaw architecture utilizes the gain of a triode per se to reduce the requirements on the offset and the noise of a rear-stage operational amplifier, and because a base electrode is biased by the output of the operational amplifier, the finally output reference voltage is insensitive to the change of a current gain coefficient Beta of the triode, but the requirement of low working voltage cannot be applied to the high-precision reference design of low power supply voltage; the Wildar architecture has good characteristics suitable for low power supply voltage, has low requirements on post-stage operational amplifier imbalance and noise, but is limited by the characteristic that a triode current gain coefficient Beta is sensitive and cannot be adopted under the condition of a low-current gain type NPN triode. The Brokaw architecture (as shown in fig. 1) utilizes the self-transistor gain to reduce the requirements on the offset and noise of the rear-stage operational amplifier, and the base is biased by the operational amplifier output, so the finally output reference voltage is insensitive to the change of the transistor current gain coefficient Beta, but the requirement of low operating voltage cannot be applied to the low-power-supply-voltage high-precision reference design, that is, in fig. 1, the power supply voltage VDD needs to be higher than the reference output voltage VOUT by at least the Vgs voltage of M3 tube plus the Vdsat voltage of M2 tube, and VDD needs to be higher than the reference output voltage VOUT by the Vgs voltage of M1 tube minus Q1 to ensure the Vbc voltage in the amplification region, so that the Brokaw architecture can normally operate, compared with the case that Wildar only needs to be higher than the reference output voltage VOUT by one Vdsat, the difference between the VDD requirements of the two typical architectures is about 0.8V, so the Brokaw architecture is not suitable for the low-voltage requirement; while the Wildar architecture (as shown in fig. 2) has a good characteristic suitable for low power supply voltage, and also has a low requirement on the post-stage operational amplifier imbalance and noise, but is limited by the characteristic that the current gain coefficient Beta of the transistor is sensitive and cannot be adopted under the condition of a low-current gain type NPN transistor, that is, in fig. 2, the current flowing through R2 is Q1 collector current plus Q1 base current plus Q2 base current, and the current flowing through R3 is Q2 collector current plus Q3 base current, that is, if the transistor current gain is small and the influence of the base current is not negligible, the current flowing through R2 and R3 differs by 1 part of the base current, and higher precision also has a strict requirement on the current flowing through Q3, so the traditional Wildar architecture is limited by the characteristic that the current gain coefficient Beta of the transistor cannot be adopted.

The prior art designs a low-voltage high-precision band-gap reference voltage source under the condition of only a low-current gain type NPN triode:

1. a conventional bandgap reference architecture, that is, a bandgap reference architecture of a parasitic PNP with a shorted base and collector or an NPN with a shorted base and collector, is adopted, as shown in fig. 3: because the collector and the base are short-circuited in the structure, the current gain coefficient Beta of the triode is not influenced in the formula. Meanwhile, the traditional band-gap reference supports lower working voltage. The disadvantage is that because the amplifier is not provided with a gain, the input imbalance and equivalent input noise of the rear-stage operational amplifier have great influence on the finally output reference voltage, so that a large area or power consumption expense is needed for inhibiting the influence, and even a complex chopper method is adopted, certain noise ripple of the output voltage needs to be inhibited.

2. A current type bandgap reference architecture is adopted, that is, the base-emitter Voltage (VBE) and the base-emitter voltage difference (delta _ VBE) of the triode are converted into current signals, and then added to obtain a reference voltage, as shown in fig. 4. The advantage is that it can operate at very low supply voltages, even below the bandgap voltage VBG. The disadvantage is still high offset and noise requirements for the later stages of amplification.

Disclosure of Invention

The invention utilizes a local self-bias (local source follower) composed of an intrinsic NMOS (Native NMOS) tube in the traditional Wildar type band-gap reference voltage source framework to offset the base current imbalance in the traditional Wildar type band-gap reference voltage source framework, and utilizes the base current extracted by the local self-bias to feed back to a proper position of a circuit to further improve the precision of an output reference, namely finally obtain a high-precision reference voltage irrelevant to the absolute value of Beta, so that the traditional Wildar type reference voltage source framework is insensitive to the current gain coefficient Beta of a triode, and simultaneously keeps the characteristics of more loose input mismatch and noise requirements on a rear-stage operational amplifier, and is suitable for a low power supply voltage application scene. The intrinsic NMOS (Native NMOS) tube is a self-contained device defaulted by most processes, extra process cost is not increased, and compared with a common threshold NMOS, the intrinsic NMOS tube has fewer process doping levels and small mutual offset, so that the influence of an additional structure on precision is small; the low threshold characteristic (generally close to 0V) also enables the proposed bandgap reference voltage source architecture to still support very low operating power supply voltage.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a band-gap reference voltage source suitable for a low-current gain type NPN triode comprises a Wildar type band-gap reference voltage source and is characterized by further comprising a local self-biasing circuit, wherein the local self-biasing circuit is used for offsetting base current imbalance in the Wildar type band-gap reference voltage source, and meanwhile base current extracted by the local self-biasing circuit is fed back to a circuit to improve the precision of output reference, namely high-precision reference voltage irrelevant to the absolute value of Beta is finally obtained, so that the Wildar type reference voltage source is insensitive to a triode current gain coefficient Beta.

Further, the Wildar band gap reference voltage source comprises a first triode Q1, a second triode Q2, a third triode Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and an error amplifier; the emitter of the first triode Q1 is grounded, and the collector of the first triode Q1 is connected with the output of the error amplifier after passing through the second resistor R2; the base electrode of the second triode Q2 is connected with the base electrode of the first triode Q1, the emitter electrode of the second triode Q2 is grounded after passing through the first resistor R1, the collector electrode of the second triode Q2 is connected with the inverting input end of the error amplifier, and the collector electrode of the second triode Q2 is connected with the output of the error amplifier after passing through the third resistor R3; the emitter of the third triode is grounded, the collector of the third triode is connected with the non-inverting input end of the error amplifier, and the collector of the third triode is connected with the output of the error amplifier after passing through a fourth resistor R4;

the local self-biasing circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9 and a tenth MOS transistor M10; the grid electrode of the first MOS tube M1 is connected with the collector electrode of the first triode Q1, the source electrode of the first MOS tube M1 is connected with the base electrodes of the first triode Q1 and the second triode Q2, and the drain electrode of the first MOS tube M1 is connected with the drain electrode of the fourth MOS tube M4; the grid electrode of the second MOS tube M2 is connected with the collector electrode of the second triode Q2, the source electrode of the second MOS tube M2 is connected with the base electrode of the third triode Q3, and the drain electrode of the second MOS tube M2 is connected with the drain electrode of the fourth MOS tube M4; the drain electrode of the third MOS tube M3 is connected with a power supply VDD, the grid electrode of the third MOS tube M3 is connected with the output end of the error amplifier, and the source electrode of the third MOS tube M3 is connected with the drain electrode of the tenth MOS tube M10; the source electrode of the fourth MOS tube M4 is connected with a power supply VDD, and the grid electrode and the drain electrode thereof are interconnected; the source electrode of the fifth MOS tube M5 is connected with a power supply VDD, and the grid electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourth MOS tube M4; the drain electrode and the grid electrode of the sixth MOS tube M6 are interconnected, the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fifth MOS tube M5, and the source electrode of the sixth MOS tube M6 is grounded; the drain electrode of the seventh MOS transistor M7 is connected with the collector electrode of the first triode Q1, the grid electrode of the seventh MOS transistor M7 is connected with the drain electrode of the fifth MOS transistor M5, and the source electrode of the seventh MOS transistor M7 is grounded; the drain electrode of the eighth MOS transistor M8 is connected to the collector electrode of the second triode Q2, the gate electrode of the eighth MOS transistor M8 is connected to the drain electrode of the fifth MOS transistor M5, and the source electrode of the eighth MOS transistor M8 is grounded; the drain electrode of the ninth MOS tube M9 is connected with the collector electrode of the third triode Q3, the grid electrode of the ninth MOS tube M9 is connected with the drain electrode of the fifth MOS tube M5, and the source electrode of the ninth MOS tube M9 is grounded; the grid electrode of the tenth MOS transistor M10 is connected with the drain electrode of the fifth MOS transistor M5, and the source electrode of the tenth MOS transistor M10 is grounded; the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are intrinsic NMOS transistors, and the length-width ratio is 2:1: 1; the connection point of the source of the third MOS transistor M3 and the drain of the tenth MOS transistor M10 is the output end of the reference voltage source.

In the scheme of the invention, local self-bias (local self-power) formed by an intrinsic NMOS (Native NMOS) tube is utilized to offset the base current imbalance in the traditional Wildar band-gap reference voltage source framework, and simultaneously, the base current extracted by the local self-bias is fed back to a proper position of a circuit to further improve the precision of output reference; here, Native NMOS is the default of most processes, and does not add extra process cost, and the low threshold and low offset characteristics greatly contribute to the overall output accuracy and the lowest operating power supply voltage.

The invention has the beneficial effects that: the invention utilizes a local self-bias (local source follower) composed of an intrinsic NMOS (Native NMOS) tube in the traditional Wildar type band-gap reference voltage source framework to offset the base current imbalance in the traditional Wildar type band-gap reference voltage source framework, and utilizes the base current extracted by the local self-bias to feed back to a proper position of a circuit to further improve the precision of an output reference, namely finally obtain a high-precision reference voltage irrelevant to the absolute value of Beta, so that the traditional Wildar type reference voltage source framework is insensitive to the current gain coefficient Beta of a triode, and simultaneously keeps the characteristics of more loose input mismatch and noise requirements on a rear-stage operational amplifier, and is suitable for a low power supply voltage application scene. The intrinsic NMOS (Native NMOS) tube is a self-contained device defaulted by most processes, extra process cost is not increased, and compared with a common threshold NMOS, the intrinsic NMOS tube has fewer process doping levels and small mutual offset, so that the influence of an additional structure on precision is small; the low threshold characteristic (generally close to 0V) also enables the proposed bandgap reference voltage source architecture to still support very low operating power supply voltage.

Drawings

FIG. 1 is a generalized Brokaw-type bandgap reference architecture;

FIG. 2 is a generalized Wildar-type bandgap reference architecture;

FIG. 3 is a conventional bandgap reference architecture employing parasitic PNPs or NPNs;

FIG. 4 is a current mode bandgap reference architecture;

fig. 5 is a general Wildar bandgap reference voltage modified architecture with local source follower optimization and feedback compensation of the base current.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings:

fig. 5 is an optimization of the general Wildar bandgap reference voltage architecture of fig. 2, that is, a general Wildar bandgap reference voltage modified architecture for optimizing the compensated base current by local self-bias (local self-power) composed of Native NMOS transistors. The basic framework of the Wildar band-gap reference voltage is shown in the figure, self-bias and feedback compensation of base current are realized by innovatively adding M1-M10, and finally the traditional Wildar band-gap reference voltage source framework is insensitive to a triode current gain coefficient Beta.

The specific working principle is as follows: M1-M3 are intrinsic NMOS transistors (Native NMOS) with the aspect ratio of M1, M2 and M3 being 2:1: 1. The local self-bias circuit (local self-bias) formed by M1 provides the base currents of Q1 and Q2 and the local self-bias circuit (local self-bias) formed by M2 provides the base current of Q3, because M1 provides 2 parts of base current and M2 provides 1 part of base current, the optimal aspect ratio of M1 and M2 is 2: 1. The current mirror circuit formed by M4-M5 can extract base current of Q1-Q3, and then the base current is further fed back to the circuit through M6-M9, so that the accuracy of output voltage is improved, namely, the current which needs to flow through ideal R2, R3 and R4 is completely equal to emitter current, and if M6-M9 is lacked, only collector current exists, and the output voltage has errors. The ideal state can be approached by compensating 1 part of base current in each of M6-M9. M10 forms a Level shifter by mirroring one path of base current as the load of an intrinsic NMOS transistor M3, the mirrored current is proportional to the current flowing through M1 and M2, so that the M1-M3 are ensured to have the same gate-source voltage Vgs, and finally, an output reference voltage value irrelevant to the threshold value of the intrinsic NMOS transistor (Native NMOS) is obtained.

Claims (2)

1. A band-gap reference voltage source suitable for a low-current gain type NPN triode comprises a Wildar type band-gap reference voltage source and is characterized by further comprising a local self-biasing circuit, wherein the local self-biasing circuit is used for offsetting base current imbalance in the Wildar type band-gap reference voltage source, and meanwhile base current extracted by the local self-biasing circuit is fed back to a circuit to improve the precision of output reference, namely high-precision reference voltage irrelevant to the absolute value of Beta is finally obtained, so that the Wildar type reference voltage source is insensitive to a triode current gain coefficient Beta.

2. The band-gap reference voltage source suitable for the low-current gain type NPN triode of claim 1, wherein the Wildar band-gap reference voltage source comprises a first triode Q1, a second triode Q2, a third triode Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and an error amplifier; the emitter of the first triode Q1 is grounded, and the collector of the first triode Q1 is connected with the output of the error amplifier after passing through the second resistor R2; the base electrode of the second triode Q2 is connected with the base electrode of the first triode Q1, the emitter electrode of the second triode Q2 is grounded after passing through the first resistor R1, the collector electrode of the second triode Q2 is connected with the inverting input end of the error amplifier, and the collector electrode of the second triode Q2 is connected with the output of the error amplifier after passing through the third resistor R3; the emitter of the third triode is grounded, the collector of the third triode is connected with the non-inverting input end of the error amplifier, and the collector of the third triode is connected with the output of the error amplifier after passing through a fourth resistor R4;

the local self-biasing circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9 and a tenth MOS transistor M10; the grid electrode of the first MOS tube M1 is connected with the collector electrode of the first triode Q1, the source electrode of the first MOS tube M1 is connected with the base electrodes of the first triode Q1 and the second triode Q2, and the drain electrode of the first MOS tube M1 is connected with the drain electrode of the fourth MOS tube M4; the grid electrode of the second MOS tube M2 is connected with the collector electrode of the second triode Q2, the source electrode of the second MOS tube M2 is connected with the base electrode of the third triode Q3, and the drain electrode of the second MOS tube M2 is connected with the drain electrode of the fourth MOS tube M4; the drain electrode of the third MOS tube M3 is connected with a power supply VDD, the grid electrode of the third MOS tube M3 is connected with the output end of the error amplifier, and the source electrode of the third MOS tube M3 is connected with the drain electrode of the tenth MOS tube M10; the source electrode of the fourth MOS tube M4 is connected with a power supply VDD, and the grid electrode and the drain electrode thereof are interconnected; the source electrode of the fifth MOS tube M5 is connected with a power supply VDD, and the grid electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourth MOS tube M4; the drain electrode and the grid electrode of the sixth MOS tube M6 are interconnected, the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fifth MOS tube M5, and the source electrode of the sixth MOS tube M6 is grounded; the drain electrode of the seventh MOS transistor M7 is connected with the collector electrode of the first triode Q1, the grid electrode of the seventh MOS transistor M7 is connected with the drain electrode of the fifth MOS transistor M5, and the source electrode of the seventh MOS transistor M7 is grounded; the drain electrode of the eighth MOS transistor M8 is connected to the collector electrode of the second triode Q2, the gate electrode of the eighth MOS transistor M8 is connected to the drain electrode of the fifth MOS transistor M5, and the source electrode of the eighth MOS transistor M8 is grounded; the drain electrode of the ninth MOS tube M9 is connected with the collector electrode of the third triode Q3, the grid electrode of the ninth MOS tube M9 is connected with the drain electrode of the fifth MOS tube M5, and the source electrode of the ninth MOS tube M9 is grounded; the grid electrode of the tenth MOS transistor M10 is connected with the drain electrode of the fifth MOS transistor M5, and the source electrode of the tenth MOS transistor M10 is grounded; the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are intrinsic NMOS transistors, and the length-width ratio is 2:1: 1; the connection point of the source of the third MOS transistor M3 and the drain of the tenth MOS transistor M10 is the output end of the reference voltage source.

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